From 8b148b99ca5057089becb8d890dfeb9356fec277 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Wed, 16 Feb 2022 10:47:56 +0100
Subject: [PATCH] Added MP to bsn_aligner_v2 + minor improvements

---
 .../tb_lofar2_unb2b_sdp_station_xsub_ring.vhd |   50 +-
 .../src/vhdl/lofar2_unb2b_sdp_station.vhd     |  228 +-
 .../src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd |   94 +-
 .../qsys_lofar2_unb2b_sdp_station_pkg.vhd     |   56 +-
 .../lofar2_unb2c_sdp_station.fpga.yaml        |    8 +-
 .../qsys_lofar2_unb2c_sdp_station_cpu_0.ip    |    4 +-
 ...ar2_unb2c_sdp_station_reg_bsn_align_v2.ip} |   46 +-
 ..._reg_bsn_monitor_v2_bsn_align_v2_input.ip} |   28 +-
 ...reg_bsn_monitor_v2_bsn_align_v2_output.ip} |   28 +-
 ...station_reg_bsn_monitor_v2_xst_offload.ip} |   28 +-
 .../qsys_lofar2_unb2c_sdp_station.qsys        | 5691 +++++++++--------
 .../lofar2_unb2c_sdp_station_adc/hdllib.cfg   |    8 +-
 .../lofar2_unb2c_sdp_station_bf/hdllib.cfg    |    8 +-
 .../lofar2_unb2c_sdp_station_fsub/hdllib.cfg  |    8 +-
 .../lofar2_unb2c_sdp_station_full/hdllib.cfg  |    8 +-
 .../hdllib.cfg                                |    8 +-
 .../hdllib.cfg                                |    8 +-
 .../src/vhdl/lofar2_unb2c_sdp_station.vhd     |  228 +-
 .../src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd |   94 +-
 .../qsys_lofar2_unb2c_sdp_station_pkg.vhd     |  898 +--
 .../lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd |    8 +-
 .../vhdl/tb_sdp_crosslets_subband_select.vhd  |    4 +-
 libraries/base/dp/dp.peripheral.yaml          |    8 +-
 .../base/dp/src/vhdl/dp_bsn_align_v2.vhd      |   44 +-
 .../base/dp/src/vhdl/dp_fifo_fill_eop.vhd     |   96 +-
 .../base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd  |   39 +-
 26 files changed, 3900 insertions(+), 3828 deletions(-)
 rename applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/{qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip => qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip} (97%)
 rename applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/{qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip => qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip} (98%)
 rename applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/{qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip => qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip} (98%)
 rename applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/{qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.ip => qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip} (97%)

diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
index 70f33ea248..ba5e595a62 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -328,7 +328,7 @@ BEGIN
     ----------------------------------------------------------------------------
       FOR I IN 0 TO c_sdp_P_sq-1 LOOP
         IF I >= c_P_sq THEN
-          mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_ALIGN", I, 0, tb_clk);
+          mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_ALIGN_V2", I, 0, tb_clk);
         END IF;
       END LOOP;
 
@@ -452,31 +452,31 @@ BEGIN
     ----------------------------------------------------------------------------
     FOR RN IN 0 TO c_nof_rn-1 LOOP
       FOR J IN 0 TO c_P_sq-1 LOOP  -- bsn_monitor index
-        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+0, rd_data, tb_clk); --status bits
-        REPORT "sync_timeout = " & INTEGER'IMAGE(TO_UINT(rd_data(2 DOWNTO 2)))  & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
-        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+1, rd_data, tb_clk); --bsn at sync
-        REPORT "bsn_at_sync  = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
-        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+3, rd_data, tb_clk); --nof_sop
-        REPORT "nof_sop      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
-        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+4, rd_data, tb_clk); --nof_valid
-        REPORT "nof_valid    = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
-        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+5, rd_data, tb_clk); --nof_err
-        REPORT "nof_err      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
-        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+6, rd_data, tb_clk); --latency
-        REPORT "latency      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
+        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+0, rd_data, tb_clk); --status bits
+        REPORT "sync_timeout = " & INTEGER'IMAGE(TO_UINT(rd_data(2 DOWNTO 2)))  & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
+        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+1, rd_data, tb_clk); --bsn at sync
+        REPORT "bsn_at_sync  = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
+        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+3, rd_data, tb_clk); --nof_sop
+        REPORT "nof_sop      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
+        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+4, rd_data, tb_clk); --nof_valid
+        REPORT "nof_valid    = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
+        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+5, rd_data, tb_clk); --nof_err
+        REPORT "nof_err      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
+        mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+6, rd_data, tb_clk); --latency
+        REPORT "latency      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;  
       END LOOP;
-      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 0, rd_data, tb_clk); --status bits
-      REPORT "sync_timeout = " & INTEGER'IMAGE(TO_UINT(rd_data(2 DOWNTO 2)))  & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;  
-      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 1, rd_data, tb_clk); --bsn at sync
-      REPORT "bsn_at_sync  = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;  
-      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 3, rd_data, tb_clk); --nof_sop
-      REPORT "nof_sop      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;  
-      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 4, rd_data, tb_clk); --nof_valid
-      REPORT "nof_valid    = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;  
-      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 5, rd_data, tb_clk); --nof_err
-      REPORT "nof_err      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE; 
-      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 6, rd_data, tb_clk); --latency
-      REPORT "latency      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE; 
+      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 0, rd_data, tb_clk); --status bits
+      REPORT "sync_timeout = " & INTEGER'IMAGE(TO_UINT(rd_data(2 DOWNTO 2)))  & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;  
+      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 1, rd_data, tb_clk); --bsn at sync
+      REPORT "bsn_at_sync  = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;  
+      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 3, rd_data, tb_clk); --nof_sop
+      REPORT "nof_sop      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;  
+      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 4, rd_data, tb_clk); --nof_valid
+      REPORT "nof_valid    = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;  
+      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 5, rd_data, tb_clk); --nof_err
+      REPORT "nof_err      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE; 
+      mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 6, rd_data, tb_clk); --latency
+      REPORT "latency      = " & INTEGER'IMAGE(TO_UINT(rd_data))  & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE; 
     END LOOP;
 
     ---------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 60e6034c10..194c7142c9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -360,18 +360,18 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
   SIGNAL reg_stat_hdr_dat_xst_miso      : t_mem_miso;
 
   -- XST bsn aligner_v2
-  SIGNAL  reg_bsn_align_copi                          : t_mem_mosi;
-  SIGNAL  reg_bsn_align_cipo                          : t_mem_miso;
+  SIGNAL  reg_bsn_align_v2_copi                       : t_mem_mosi;
+  SIGNAL  reg_bsn_align_v2_cipo                       : t_mem_miso;
    
   -- XST bsn aligner_v2 bsn monitors
-  SIGNAL  reg_bsn_monitor_v2_bsn_align_input_copi                      : t_mem_mosi;
-  SIGNAL  reg_bsn_monitor_v2_bsn_align_input_cipo                      : t_mem_miso;
-  SIGNAL  reg_bsn_monitor_v2_bsn_align_output_copi                     : t_mem_mosi;
-  SIGNAL  reg_bsn_monitor_v2_bsn_align_output_cipo                     : t_mem_miso;
+  SIGNAL  reg_bsn_monitor_v2_bsn_align_v2_input_copi  : t_mem_mosi;
+  SIGNAL  reg_bsn_monitor_v2_bsn_align_v2_input_cipo  : t_mem_miso;
+  SIGNAL  reg_bsn_monitor_v2_bsn_align_v2_output_copi : t_mem_mosi;
+  SIGNAL  reg_bsn_monitor_v2_bsn_align_v2_output_cipo : t_mem_miso;
 
   -- XST UDP offload bsn monitor
-  SIGNAL  reg_xst_udp_monitor_copi                    : t_mem_mosi;
-  SIGNAL  reg_xst_udp_monitor_cipo                    : t_mem_miso;
+  SIGNAL  reg_bsn_monitor_v2_xst_offload_copi         : t_mem_mosi;
+  SIGNAL  reg_bsn_monitor_v2_xst_offload_cipo         : t_mem_miso;
 
   -- XST ring lane info
   SIGNAL  reg_ring_lane_info_xst_copi                 : t_mem_mosi;
@@ -637,104 +637,104 @@ BEGIN
 
     -- mm buses for signal flow blocks
     -- Jesd ip status/control
-    jesd204b_mosi                              => jesd204b_mosi,
-    jesd204b_miso                              => jesd204b_miso,
-    jesd_ctrl_mosi                             => jesd_ctrl_mosi,
-    jesd_ctrl_miso                             => jesd_ctrl_miso,
-    reg_dp_shiftram_mosi                       => reg_dp_shiftram_mosi,
-    reg_dp_shiftram_miso                       => reg_dp_shiftram_miso,
-    reg_bsn_source_v2_mosi                     => reg_bsn_source_v2_mosi,
-    reg_bsn_source_v2_miso                     => reg_bsn_source_v2_miso,
-    reg_bsn_scheduler_mosi                     => reg_bsn_scheduler_wg_mosi,
-    reg_bsn_scheduler_miso                     => reg_bsn_scheduler_wg_miso,
-    reg_wg_mosi                                => reg_wg_mosi,
-    reg_wg_miso                                => reg_wg_miso,
-    ram_wg_mosi                                => ram_wg_mosi,
-    ram_wg_miso                                => ram_wg_miso,
-    reg_bsn_monitor_input_mosi                 => reg_bsn_monitor_input_mosi,
-    reg_bsn_monitor_input_miso                 => reg_bsn_monitor_input_miso,
-    ram_diag_data_buf_bsn_mosi                 => ram_diag_data_buf_bsn_mosi,
-    ram_diag_data_buf_bsn_miso                 => ram_diag_data_buf_bsn_miso,
-    reg_diag_data_buf_bsn_mosi                 => reg_diag_data_buf_bsn_mosi,
-    reg_diag_data_buf_bsn_miso                 => reg_diag_data_buf_bsn_miso,
-    ram_st_histogram_mosi                      => ram_st_histogram_mosi,
-    ram_st_histogram_miso                      => ram_st_histogram_miso,
-    reg_aduh_monitor_mosi                      => reg_aduh_monitor_mosi,
-    reg_aduh_monitor_miso                      => reg_aduh_monitor_miso,
-    ram_st_sst_mosi                            => ram_st_sst_mosi,   
-    ram_st_sst_miso                            => ram_st_sst_miso,   
-    ram_fil_coefs_mosi                         => ram_fil_coefs_mosi,   
-    ram_fil_coefs_miso                         => ram_fil_coefs_miso,   
-    reg_si_mosi                                => reg_si_mosi,   
-    reg_si_miso                                => reg_si_miso,
-    ram_equalizer_gains_mosi                   => ram_equalizer_gains_mosi,   
-    ram_equalizer_gains_miso                   => ram_equalizer_gains_miso,   
-    reg_dp_selector_mosi                       => reg_dp_selector_mosi,   
-    reg_dp_selector_miso                       => reg_dp_selector_miso,
-    reg_sdp_info_mosi                          => reg_sdp_info_mosi,          
-    reg_sdp_info_miso                          => reg_sdp_info_miso, 
-    reg_ring_info_copi                         => reg_ring_info_copi,
-    reg_ring_info_cipo                         => reg_ring_info_cipo,          
-    ram_ss_ss_wide_mosi                        => ram_ss_ss_wide_mosi,        
-    ram_ss_ss_wide_miso                        => ram_ss_ss_wide_miso,        
-    ram_bf_weights_mosi                        => ram_bf_weights_mosi,        
-    ram_bf_weights_miso                        => ram_bf_weights_miso,        
-    reg_bf_scale_mosi                          => reg_bf_scale_mosi,          
-    reg_bf_scale_miso                          => reg_bf_scale_miso,          
-    reg_hdr_dat_mosi                           => reg_hdr_dat_mosi,           
-    reg_hdr_dat_miso                           => reg_hdr_dat_miso,           
-    reg_dp_xonoff_mosi                         => reg_dp_xonoff_mosi,         
-    reg_dp_xonoff_miso                         => reg_dp_xonoff_miso,         
-    ram_st_bst_mosi                            => ram_st_bst_mosi,            
-    ram_st_bst_miso                            => ram_st_bst_miso,            
-    reg_nw_10GbE_mac_mosi                      => reg_nw_10GbE_mac_mosi,      
-    reg_nw_10GbE_mac_miso                      => reg_nw_10GbE_mac_miso,      
-    reg_nw_10GbE_eth10g_mosi                   => reg_nw_10GbE_eth10g_mosi,   
-    reg_nw_10GbE_eth10g_miso                   => reg_nw_10GbE_eth10g_miso,   
-    ram_scrap_mosi                             => ram_scrap_mosi,
-    ram_scrap_miso                             => ram_scrap_miso,
-    reg_stat_enable_sst_mosi                   => reg_stat_enable_sst_mosi,
-    reg_stat_enable_sst_miso                   => reg_stat_enable_sst_miso,
-    reg_stat_hdr_dat_sst_mosi                  => reg_stat_hdr_dat_sst_mosi,
-    reg_stat_hdr_dat_sst_miso                  => reg_stat_hdr_dat_sst_miso,
-    reg_stat_enable_xst_mosi                   => reg_stat_enable_xst_mosi,
-    reg_stat_enable_xst_miso                   => reg_stat_enable_xst_miso,
-    reg_stat_hdr_dat_xst_mosi                  => reg_stat_hdr_dat_xst_mosi,
-    reg_stat_hdr_dat_xst_miso                  => reg_stat_hdr_dat_xst_miso,
-    reg_stat_enable_bst_mosi                   => reg_stat_enable_bst_mosi,
-    reg_stat_enable_bst_miso                   => reg_stat_enable_bst_miso,
-    reg_stat_hdr_dat_bst_mosi                  => reg_stat_hdr_dat_bst_mosi,
-    reg_stat_hdr_dat_bst_miso                  => reg_stat_hdr_dat_bst_miso,
-    reg_crosslets_info_mosi                    => reg_crosslets_info_mosi, 
-    reg_crosslets_info_miso                    => reg_crosslets_info_miso,
-    reg_nof_crosslets_mosi                     => reg_nof_crosslets_mosi, 
-    reg_nof_crosslets_miso                     => reg_nof_crosslets_miso, 
-    reg_bsn_sync_scheduler_xsub_mosi           => reg_bsn_sync_scheduler_xsub_mosi, 
-    reg_bsn_sync_scheduler_xsub_miso           => reg_bsn_sync_scheduler_xsub_miso,
-    reg_bsn_align_copi                         => reg_bsn_align_copi, 
-    reg_bsn_align_cipo                         => reg_bsn_align_cipo, 
-    reg_bsn_monitor_v2_bsn_align_input_copi    => reg_bsn_monitor_v2_bsn_align_input_copi, 
-    reg_bsn_monitor_v2_bsn_align_input_cipo    => reg_bsn_monitor_v2_bsn_align_input_cipo, 
-    reg_bsn_monitor_v2_bsn_align_output_copi   => reg_bsn_monitor_v2_bsn_align_output_copi, 
-    reg_bsn_monitor_v2_bsn_align_output_cipo   => reg_bsn_monitor_v2_bsn_align_output_cipo, 
-    reg_xst_udp_monitor_copi                   => reg_xst_udp_monitor_copi, 
-    reg_xst_udp_monitor_cipo                   => reg_xst_udp_monitor_cipo, 
-    reg_ring_lane_info_xst_copi                => reg_ring_lane_info_xst_copi, 
-    reg_ring_lane_info_xst_cipo                => reg_ring_lane_info_xst_cipo, 
-    reg_bsn_monitor_v2_ring_rx_xst_copi        => reg_bsn_monitor_v2_ring_rx_xst_copi, 
-    reg_bsn_monitor_v2_ring_rx_xst_cipo        => reg_bsn_monitor_v2_ring_rx_xst_cipo, 
-    reg_bsn_monitor_v2_ring_tx_xst_copi        => reg_bsn_monitor_v2_ring_tx_xst_copi, 
-    reg_bsn_monitor_v2_ring_tx_xst_cipo        => reg_bsn_monitor_v2_ring_tx_xst_cipo, 
-    reg_dp_block_validate_err_xst_copi         => reg_dp_block_validate_err_xst_copi, 
-    reg_dp_block_validate_err_xst_cipo         => reg_dp_block_validate_err_xst_cipo, 
-    reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi, 
-    reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo, 
-    reg_tr_10GbE_mac_copi                      => reg_tr_10GbE_mac_copi, 
-    reg_tr_10GbE_mac_cipo                      => reg_tr_10GbE_mac_cipo, 
-    reg_tr_10GbE_eth10g_copi                   => reg_tr_10GbE_eth10g_copi, 
-    reg_tr_10GbE_eth10g_cipo                   => reg_tr_10GbE_eth10g_cipo, 
-    ram_st_xsq_mosi                            => ram_st_xsq_mosi, 
-    ram_st_xsq_miso                            => ram_st_xsq_miso 
+    jesd204b_mosi                                => jesd204b_mosi,
+    jesd204b_miso                                => jesd204b_miso,
+    jesd_ctrl_mosi                               => jesd_ctrl_mosi,
+    jesd_ctrl_miso                               => jesd_ctrl_miso,
+    reg_dp_shiftram_mosi                         => reg_dp_shiftram_mosi,
+    reg_dp_shiftram_miso                         => reg_dp_shiftram_miso,
+    reg_bsn_source_v2_mosi                       => reg_bsn_source_v2_mosi,
+    reg_bsn_source_v2_miso                       => reg_bsn_source_v2_miso,
+    reg_bsn_scheduler_mosi                       => reg_bsn_scheduler_wg_mosi,
+    reg_bsn_scheduler_miso                       => reg_bsn_scheduler_wg_miso,
+    reg_wg_mosi                                  => reg_wg_mosi,
+    reg_wg_miso                                  => reg_wg_miso,
+    ram_wg_mosi                                  => ram_wg_mosi,
+    ram_wg_miso                                  => ram_wg_miso,
+    reg_bsn_monitor_input_mosi                   => reg_bsn_monitor_input_mosi,
+    reg_bsn_monitor_input_miso                   => reg_bsn_monitor_input_miso,
+    ram_diag_data_buf_bsn_mosi                   => ram_diag_data_buf_bsn_mosi,
+    ram_diag_data_buf_bsn_miso                   => ram_diag_data_buf_bsn_miso,
+    reg_diag_data_buf_bsn_mosi                   => reg_diag_data_buf_bsn_mosi,
+    reg_diag_data_buf_bsn_miso                   => reg_diag_data_buf_bsn_miso,
+    ram_st_histogram_mosi                        => ram_st_histogram_mosi,
+    ram_st_histogram_miso                        => ram_st_histogram_miso,
+    reg_aduh_monitor_mosi                        => reg_aduh_monitor_mosi,
+    reg_aduh_monitor_miso                        => reg_aduh_monitor_miso,
+    ram_st_sst_mosi                              => ram_st_sst_mosi,   
+    ram_st_sst_miso                              => ram_st_sst_miso,   
+    ram_fil_coefs_mosi                           => ram_fil_coefs_mosi,   
+    ram_fil_coefs_miso                           => ram_fil_coefs_miso,   
+    reg_si_mosi                                  => reg_si_mosi,   
+    reg_si_miso                                  => reg_si_miso,
+    ram_equalizer_gains_mosi                     => ram_equalizer_gains_mosi,   
+    ram_equalizer_gains_miso                     => ram_equalizer_gains_miso,   
+    reg_dp_selector_mosi                         => reg_dp_selector_mosi,   
+    reg_dp_selector_miso                         => reg_dp_selector_miso,
+    reg_sdp_info_mosi                            => reg_sdp_info_mosi,          
+    reg_sdp_info_miso                            => reg_sdp_info_miso, 
+    reg_ring_info_copi                           => reg_ring_info_copi,
+    reg_ring_info_cipo                           => reg_ring_info_cipo,          
+    ram_ss_ss_wide_mosi                          => ram_ss_ss_wide_mosi,        
+    ram_ss_ss_wide_miso                          => ram_ss_ss_wide_miso,        
+    ram_bf_weights_mosi                          => ram_bf_weights_mosi,        
+    ram_bf_weights_miso                          => ram_bf_weights_miso,        
+    reg_bf_scale_mosi                            => reg_bf_scale_mosi,          
+    reg_bf_scale_miso                            => reg_bf_scale_miso,          
+    reg_hdr_dat_mosi                             => reg_hdr_dat_mosi,           
+    reg_hdr_dat_miso                             => reg_hdr_dat_miso,           
+    reg_dp_xonoff_mosi                           => reg_dp_xonoff_mosi,         
+    reg_dp_xonoff_miso                           => reg_dp_xonoff_miso,         
+    ram_st_bst_mosi                              => ram_st_bst_mosi,            
+    ram_st_bst_miso                              => ram_st_bst_miso,            
+    reg_nw_10GbE_mac_mosi                        => reg_nw_10GbE_mac_mosi,      
+    reg_nw_10GbE_mac_miso                        => reg_nw_10GbE_mac_miso,      
+    reg_nw_10GbE_eth10g_mosi                     => reg_nw_10GbE_eth10g_mosi,   
+    reg_nw_10GbE_eth10g_miso                     => reg_nw_10GbE_eth10g_miso,   
+    ram_scrap_mosi                               => ram_scrap_mosi,
+    ram_scrap_miso                               => ram_scrap_miso,
+    reg_stat_enable_sst_mosi                     => reg_stat_enable_sst_mosi,
+    reg_stat_enable_sst_miso                     => reg_stat_enable_sst_miso,
+    reg_stat_hdr_dat_sst_mosi                    => reg_stat_hdr_dat_sst_mosi,
+    reg_stat_hdr_dat_sst_miso                    => reg_stat_hdr_dat_sst_miso,
+    reg_stat_enable_xst_mosi                     => reg_stat_enable_xst_mosi,
+    reg_stat_enable_xst_miso                     => reg_stat_enable_xst_miso,
+    reg_stat_hdr_dat_xst_mosi                    => reg_stat_hdr_dat_xst_mosi,
+    reg_stat_hdr_dat_xst_miso                    => reg_stat_hdr_dat_xst_miso,
+    reg_stat_enable_bst_mosi                     => reg_stat_enable_bst_mosi,
+    reg_stat_enable_bst_miso                     => reg_stat_enable_bst_miso,
+    reg_stat_hdr_dat_bst_mosi                    => reg_stat_hdr_dat_bst_mosi,
+    reg_stat_hdr_dat_bst_miso                    => reg_stat_hdr_dat_bst_miso,
+    reg_crosslets_info_mosi                      => reg_crosslets_info_mosi, 
+    reg_crosslets_info_miso                      => reg_crosslets_info_miso,
+    reg_nof_crosslets_mosi                       => reg_nof_crosslets_mosi, 
+    reg_nof_crosslets_miso                       => reg_nof_crosslets_miso, 
+    reg_bsn_sync_scheduler_xsub_mosi             => reg_bsn_sync_scheduler_xsub_mosi, 
+    reg_bsn_sync_scheduler_xsub_miso             => reg_bsn_sync_scheduler_xsub_miso,
+    reg_bsn_align_v2_copi                        => reg_bsn_align_v2_copi, 
+    reg_bsn_align_v2_cipo                        => reg_bsn_align_v2_cipo, 
+    reg_bsn_monitor_v2_bsn_align_v2_input_copi   => reg_bsn_monitor_v2_bsn_align_input_copi, 
+    reg_bsn_monitor_v2_bsn_align_v2_input_cipo   => reg_bsn_monitor_v2_bsn_align_input_cipo, 
+    reg_bsn_monitor_v2_bsn_align_v2_output_copi  => reg_bsn_monitor_v2_bsn_align_output_copi, 
+    reg_bsn_monitor_v2_bsn_align_v2_output_cipo  => reg_bsn_monitor_v2_bsn_align_output_cipo, 
+    reg_bsn_monitor_v2_xst_offload_copi          => reg_bsn_monitor_v2_xst_offload_copi, 
+    reg_bsn_monitor_v2_xst_offload_cipo          => reg_bsn_monitor_v2_xst_offload_cipo, 
+    reg_ring_lane_info_xst_copi                  => reg_ring_lane_info_xst_copi, 
+    reg_ring_lane_info_xst_cipo                  => reg_ring_lane_info_xst_cipo, 
+    reg_bsn_monitor_v2_ring_rx_xst_copi          => reg_bsn_monitor_v2_ring_rx_xst_copi, 
+    reg_bsn_monitor_v2_ring_rx_xst_cipo          => reg_bsn_monitor_v2_ring_rx_xst_cipo, 
+    reg_bsn_monitor_v2_ring_tx_xst_copi          => reg_bsn_monitor_v2_ring_tx_xst_copi, 
+    reg_bsn_monitor_v2_ring_tx_xst_cipo          => reg_bsn_monitor_v2_ring_tx_xst_cipo, 
+    reg_dp_block_validate_err_xst_copi           => reg_dp_block_validate_err_xst_copi, 
+    reg_dp_block_validate_err_xst_cipo           => reg_dp_block_validate_err_xst_cipo, 
+    reg_dp_block_validate_bsn_at_sync_xst_copi   => reg_dp_block_validate_bsn_at_sync_xst_copi, 
+    reg_dp_block_validate_bsn_at_sync_xst_cipo   => reg_dp_block_validate_bsn_at_sync_xst_cipo, 
+    reg_tr_10GbE_mac_copi                        => reg_tr_10GbE_mac_copi, 
+    reg_tr_10GbE_mac_cipo                        => reg_tr_10GbE_mac_cipo, 
+    reg_tr_10GbE_eth10g_copi                     => reg_tr_10GbE_eth10g_copi, 
+    reg_tr_10GbE_eth10g_cipo                     => reg_tr_10GbE_eth10g_cipo, 
+    ram_st_xsq_mosi                              => ram_st_xsq_mosi, 
+    ram_st_xsq_miso                              => ram_st_xsq_miso 
   );
 
 
@@ -868,14 +868,14 @@ BEGIN
     reg_stat_hdr_dat_xst_mosi   => reg_stat_hdr_dat_xst_mosi, 
     reg_stat_hdr_dat_xst_miso   => reg_stat_hdr_dat_xst_miso, 
     
-    reg_bsn_align_copi                         => reg_bsn_align_copi, 
-    reg_bsn_align_cipo                         => reg_bsn_align_cipo, 
-    reg_bsn_monitor_v2_bsn_align_input_copi    => reg_bsn_monitor_v2_bsn_align_input_copi, 
-    reg_bsn_monitor_v2_bsn_align_input_cipo    => reg_bsn_monitor_v2_bsn_align_input_cipo, 
-    reg_bsn_monitor_v2_bsn_align_output_copi   => reg_bsn_monitor_v2_bsn_align_output_copi, 
-    reg_bsn_monitor_v2_bsn_align_output_cipo   => reg_bsn_monitor_v2_bsn_align_output_cipo, 
-    reg_xst_udp_monitor_copi                   => reg_xst_udp_monitor_copi, 
-    reg_xst_udp_monitor_cipo                   => reg_xst_udp_monitor_cipo, 
+    reg_bsn_align_copi                         => reg_bsn_align_v2_copi, 
+    reg_bsn_align_cipo                         => reg_bsn_align_v2_cipo, 
+    reg_bsn_monitor_v2_bsn_align_input_copi    => reg_bsn_monitor_v2_bsn_align_v2_input_copi, 
+    reg_bsn_monitor_v2_bsn_align_input_cipo    => reg_bsn_monitor_v2_bsn_align_v2_input_cipo, 
+    reg_bsn_monitor_v2_bsn_align_output_copi   => reg_bsn_monitor_v2_bsn_align_v2_output_copi, 
+    reg_bsn_monitor_v2_bsn_align_output_cipo   => reg_bsn_monitor_v2_bsn_align_v2_output_cipo, 
+    reg_xst_udp_monitor_copi                   => reg_bsn_monitor_v2_xst_offload_copi, 
+    reg_xst_udp_monitor_cipo                   => reg_bsn_monitor_v2_xst_offload_cipo, 
     reg_ring_lane_info_xst_copi                => reg_ring_lane_info_xst_copi, 
     reg_ring_lane_info_xst_cipo                => reg_ring_lane_info_xst_cipo, 
     reg_bsn_monitor_v2_ring_rx_xst_copi        => reg_bsn_monitor_v2_ring_rx_xst_copi, 
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index a19c6ce777..49693f03c1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -239,18 +239,18 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
    reg_nw_10GbE_eth10g_miso       : IN  t_mem_miso;
 
    -- XST bsn aligner_v2
-   reg_bsn_align_copi             : OUT t_mem_mosi;             
-   reg_bsn_align_cipo             : IN  t_mem_miso;             
+   reg_bsn_align_v2_copi          : OUT t_mem_mosi;             
+   reg_bsn_align_v2_cipo          : IN  t_mem_miso;             
    
    -- XST bsn aligner_v2 bsn monitors
-   reg_bsn_monitor_v2_bsn_align_input_copi         : OUT t_mem_mosi;             
-   reg_bsn_monitor_v2_bsn_align_input_cipo         : IN  t_mem_miso;             
-   reg_bsn_monitor_v2_bsn_align_output_copi        : OUT t_mem_mosi;             
-   reg_bsn_monitor_v2_bsn_align_output_cipo        : IN  t_mem_miso;             
+   reg_bsn_monitor_v2_bsn_align_v2_input_copi  : OUT t_mem_mosi;             
+   reg_bsn_monitor_v2_bsn_align_v2_input_cipo  : IN  t_mem_miso;             
+   reg_bsn_monitor_v2_bsn_align_v2_output_copi : OUT t_mem_mosi;             
+   reg_bsn_monitor_v2_bsn_align_v2_output_cipo : IN  t_mem_miso;             
 
    -- XST UDP offload bsn monitor
-   reg_xst_udp_monitor_copi       : OUT t_mem_mosi;             
-   reg_xst_udp_monitor_cipo       : IN  t_mem_miso;             
+   reg_bsn_monitor_v2_xst_offload_copi       : OUT t_mem_mosi;             
+   reg_bsn_monitor_v2_xst_offload_cipo       : IN  t_mem_miso;             
 
    -- XST ring lane info
    reg_ring_lane_info_xst_copi    : OUT t_mem_mosi;             
@@ -439,17 +439,17 @@ BEGIN
     u_mm_file_reg_nw_10GbE_eth10g     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
                                                PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
 
-    u_mm_file_reg_bsn_align           : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN")
-                                                PORT MAP(mm_rst, mm_clk, reg_bsn_align_copi, reg_bsn_align_cipo );
+    u_mm_file_reg_bsn_align_v2         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2")
+                                                PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_copi, reg_bsn_align_v2_cipo );
 
-    u_mm_file_reg_bsn_monitor_v2_bsn_align_input       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT")
-                                                PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_input_copi, reg_bsn_monitor_v2_bsn_align_input_cipo );
+    u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT")
+                                                           PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_input_copi, reg_bsn_monitor_v2_bsn_align_v2_input_cipo );
 
-    u_mm_file_reg_bsn_monitor_v2_bsn_align_output      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT")
-                                                PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_output_copi, reg_bsn_monitor_v2_bsn_align_output_cipo );
+    u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_output: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT")
+                                                           PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_output_copi, reg_bsn_monitor_v2_bsn_align_v2_output_cipo );
 
-    u_mm_file_reg_xst_udp_monitor     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_XST_UDP_MONITOR")
-                                                PORT MAP(mm_rst, mm_clk, reg_xst_udp_monitor_copi, reg_xst_udp_monitor_cipo );
+    u_mm_file_reg_bsn_monitor_v2_xst_offload     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
+                                                PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
 
     u_mm_file_reg_ring_lane_info_xst  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
                                                 PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
@@ -927,37 +927,37 @@ BEGIN
       reg_nw_10GbE_eth10g_read_export           => reg_nw_10GbE_eth10g_mosi.rd,
       reg_nw_10GbE_eth10g_readdata_export       => reg_nw_10GbE_eth10g_miso.rddata(c_word_w-1 DOWNTO 0),
 
-      reg_bsn_align_clk_export                  => OPEN,
-      reg_bsn_align_reset_export                => OPEN,
-      reg_bsn_align_address_export              => reg_bsn_align_copi.address(c_sdp_reg_bsn_align_addr_w-1 DOWNTO 0),
-      reg_bsn_align_write_export                => reg_bsn_align_copi.wr,
-      reg_bsn_align_writedata_export            => reg_bsn_align_copi.wrdata(c_word_w-1 DOWNTO 0), 
-      reg_bsn_align_read_export                 => reg_bsn_align_copi.rd,
-      reg_bsn_align_readdata_export             => reg_bsn_align_cipo.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_bsn_monitor_v2_bsn_align_input_clk_export        => OPEN,
-      reg_bsn_monitor_v2_bsn_align_input_reset_export      => OPEN,
-      reg_bsn_monitor_v2_bsn_align_input_address_export    => reg_bsn_monitor_v2_bsn_align_input_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_input_addr_w-1 DOWNTO 0),
-      reg_bsn_monitor_v2_bsn_align_input_write_export      => reg_bsn_monitor_v2_bsn_align_input_copi.wr,
-      reg_bsn_monitor_v2_bsn_align_input_writedata_export  => reg_bsn_monitor_v2_bsn_align_input_copi.wrdata(c_word_w-1 DOWNTO 0), 
-      reg_bsn_monitor_v2_bsn_align_input_read_export       => reg_bsn_monitor_v2_bsn_align_input_copi.rd,
-      reg_bsn_monitor_v2_bsn_align_input_readdata_export   => reg_bsn_monitor_v2_bsn_align_input_cipo.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_bsn_monitor_v2_bsn_align_output_clk_export       => OPEN,
-      reg_bsn_monitor_v2_bsn_align_output_reset_export     => OPEN,
-      reg_bsn_monitor_v2_bsn_align_output_address_export   => reg_bsn_monitor_v2_bsn_align_output_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_output_addr_w-1 DOWNTO 0),
-      reg_bsn_monitor_v2_bsn_align_output_write_export     => reg_bsn_monitor_v2_bsn_align_output_copi.wr,
-      reg_bsn_monitor_v2_bsn_align_output_writedata_export => reg_bsn_monitor_v2_bsn_align_output_copi.wrdata(c_word_w-1 DOWNTO 0), 
-      reg_bsn_monitor_v2_bsn_align_output_read_export      => reg_bsn_monitor_v2_bsn_align_output_copi.rd,
-      reg_bsn_monitor_v2_bsn_align_output_readdata_export  => reg_bsn_monitor_v2_bsn_align_output_cipo.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_xst_udp_monitor_clk_export            => OPEN,
-      reg_xst_udp_monitor_reset_export          => OPEN,
-      reg_xst_udp_monitor_address_export        => reg_xst_udp_monitor_copi.address(c_sdp_reg_xst_udp_monitor_addr_w-1 DOWNTO 0),
-      reg_xst_udp_monitor_write_export          => reg_xst_udp_monitor_copi.wr,
-      reg_xst_udp_monitor_writedata_export      => reg_xst_udp_monitor_copi.wrdata(c_word_w-1 DOWNTO 0), 
-      reg_xst_udp_monitor_read_export           => reg_xst_udp_monitor_copi.rd,
-      reg_xst_udp_monitor_readdata_export       => reg_xst_udp_monitor_cipo.rddata(c_word_w-1 DOWNTO 0),
+      reg_bsn_align_v2_clk_export               => OPEN,
+      reg_bsn_align_v2_reset_export             => OPEN,
+      reg_bsn_align_v2_address_export           => reg_bsn_align_v2_copi.address(c_sdp_reg_bsn_align_v2_addr_w-1 DOWNTO 0),
+      reg_bsn_align_v2_write_export             => reg_bsn_align_v2_copi.wr,
+      reg_bsn_align_v2_writedata_export         => reg_bsn_align_v2_copi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_bsn_align_v2_read_export              => reg_bsn_align_v2_copi.rd,
+      reg_bsn_align_v2_readdata_export          => reg_bsn_align_v2_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_bsn_monitor_v2_bsn_align_v2_input_clk_export       => OPEN,
+      reg_bsn_monitor_v2_bsn_align_v2_input_reset_export     => OPEN,
+      reg_bsn_monitor_v2_bsn_align_v2_input_address_export   => reg_bsn_monitor_v2_bsn_align_v2_input_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_v2_input_addr_w-1 DOWNTO 0),
+      reg_bsn_monitor_v2_bsn_align_v2_input_write_export     => reg_bsn_monitor_v2_bsn_align_v2_input_copi.wr,
+      reg_bsn_monitor_v2_bsn_align_v2_input_writedata_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_bsn_monitor_v2_bsn_align_v2_input_read_export      => reg_bsn_monitor_v2_bsn_align_v2_input_copi.rd,
+      reg_bsn_monitor_v2_bsn_align_v2_input_readdata_export  => reg_bsn_monitor_v2_bsn_align_v2_input_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_bsn_monitor_v2_bsn_align_v2_output_clk_export      => OPEN,
+      reg_bsn_monitor_v2_bsn_align_v2_output_reset_export    => OPEN,
+      reg_bsn_monitor_v2_bsn_align_v2_output_address_export  => reg_bsn_monitor_v2_bsn_align_v2_output_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_v2_output_addr_w-1 DOWNTO 0),
+      reg_bsn_monitor_v2_bsn_align_v2_output_write_export    => reg_bsn_monitor_v2_bsn_align_v2_output_copi.wr,
+      reg_bsn_monitor_v2_bsn_align_v2_output_writedata_export=> reg_bsn_monitor_v2_bsn_align_v2_output_copi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_bsn_monitor_v2_bsn_align_v2_output_read_export     => reg_bsn_monitor_v2_bsn_align_v2_output_copi.rd,
+      reg_bsn_monitor_v2_bsn_align_v2_output_readdata_export => reg_bsn_monitor_v2_bsn_align_v2_output_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_bsn_monitor_v2_xst_offload_clk_export            => OPEN,
+      reg_bsn_monitor_v2_xst_offload_reset_export          => OPEN,
+      reg_bsn_monitor_v2_xst_offload_address_export        => reg_bsn_monitor_v2_xst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w-1 DOWNTO 0),
+      reg_bsn_monitor_v2_xst_offload_write_export          => reg_bsn_monitor_v2_xst_offload_copi.wr,
+      reg_bsn_monitor_v2_xst_offload_writedata_export      => reg_bsn_monitor_v2_xst_offload_copi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_bsn_monitor_v2_xst_offload_read_export           => reg_bsn_monitor_v2_xst_offload_copi.rd,
+      reg_bsn_monitor_v2_xst_offload_readdata_export       => reg_bsn_monitor_v2_xst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
 
       reg_ring_lane_info_xst_clk_export         => OPEN,
       reg_ring_lane_info_xst_reset_export       => OPEN,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index f4ed10f552..e76a06d0b6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -168,13 +168,13 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
             reg_bf_scale_reset_export                              : out std_logic;                                        -- export
             reg_bf_scale_write_export                              : out std_logic;                                        -- export
             reg_bf_scale_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_align_address_export                           : out std_logic_vector(3 downto 0);                     -- export
-            reg_bsn_align_clk_export                               : out std_logic;                                        -- export
-            reg_bsn_align_read_export                              : out std_logic;                                        -- export
-            reg_bsn_align_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bsn_align_reset_export                             : out std_logic;                                        -- export
-            reg_bsn_align_write_export                             : out std_logic;                                        -- export
-            reg_bsn_align_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_align_v2_reset_export                          : out std_logic;                                        -- export
+            reg_bsn_align_v2_clk_export                            : out std_logic;                                        -- export
+            reg_bsn_align_v2_address_export                        : out std_logic_vector(5 downto 0);                     -- export
+            reg_bsn_align_v2_write_export                          : out std_logic;                                        -- export
+            reg_bsn_align_v2_writedata_export                      : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_align_v2_read_export                           : out std_logic;                                        -- export
+            reg_bsn_align_v2_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
             reg_bsn_monitor_input_address_export                   : out std_logic_vector(7 downto 0);                     -- export
             reg_bsn_monitor_input_clk_export                       : out std_logic;                                        -- export
             reg_bsn_monitor_input_read_export                      : out std_logic;                                        -- export
@@ -182,20 +182,20 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
             reg_bsn_monitor_input_reset_export                     : out std_logic;                                        -- export
             reg_bsn_monitor_input_write_export                     : out std_logic;                                        -- export
             reg_bsn_monitor_input_writedata_export                 : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_monitor_v2_bsn_align_input_address_export      : out std_logic_vector(6 downto 0);                     -- export
-            reg_bsn_monitor_v2_bsn_align_input_clk_export          : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_input_read_export         : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_input_readdata_export     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bsn_monitor_v2_bsn_align_input_reset_export        : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_input_write_export        : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_input_writedata_export    : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_monitor_v2_bsn_align_output_address_export     : out std_logic_vector(2 downto 0);                     -- export
-            reg_bsn_monitor_v2_bsn_align_output_clk_export         : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_output_read_export        : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_output_readdata_export    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bsn_monitor_v2_bsn_align_output_reset_export       : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_output_write_export       : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_output_writedata_export   : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_reset_export        : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_clk_export          : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_address_export      : out std_logic_vector(6 downto 0);                     -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_write_export        : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_writedata_export    : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_read_export         : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_readdata_export     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_reset_export       : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_clk_export         : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_address_export     : out std_logic_vector(2 downto 0);                     -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_write_export       : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_writedata_export   : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_read_export        : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_readdata_export    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
             reg_bsn_monitor_v2_ring_rx_xst_address_export          : out std_logic_vector(6 downto 0);                     -- export
             reg_bsn_monitor_v2_ring_rx_xst_clk_export              : out std_logic;                                        -- export
             reg_bsn_monitor_v2_ring_rx_xst_read_export             : out std_logic;                                        -- export
@@ -476,13 +476,13 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
             reg_wg_reset_export                                    : out std_logic;                                        -- export
             reg_wg_write_export                                    : out std_logic;                                        -- export
             reg_wg_writedata_export                                : out std_logic_vector(31 downto 0);                    -- export
-            reg_xst_udp_monitor_address_export                     : out std_logic_vector(2 downto 0);                     -- export
-            reg_xst_udp_monitor_clk_export                         : out std_logic;                                        -- export
-            reg_xst_udp_monitor_read_export                        : out std_logic;                                        -- export
-            reg_xst_udp_monitor_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_xst_udp_monitor_reset_export                       : out std_logic;                                        -- export
-            reg_xst_udp_monitor_write_export                       : out std_logic;                                        -- export
-            reg_xst_udp_monitor_writedata_export                   : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_xst_offload_reset_export            : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_xst_offload_clk_export              : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_xst_offload_address_export          : out std_logic_vector(2 downto 0);                     -- export
+            reg_bsn_monitor_v2_xst_offload_write_export            : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_xst_offload_writedata_export        : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_xst_offload_read_export             : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_xst_offload_readdata_export         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
             reset_reset_n                                          : in  std_logic                     := 'X';             -- reset_n
             rom_system_info_address_export                         : out std_logic_vector(12 downto 0);                    -- export
             rom_system_info_clk_export                             : out std_logic;                                        -- export
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
index a0a5c66397..0cd431c31c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
@@ -270,28 +270,28 @@ peripherals:
     parameter_overrides:
       - { name: g_nof_streams, value: c_P_sq }
     mm_port_names:
-      - REG_BSN_ALIGN
+      - REG_BSN_ALIGN_V2
   
   - peripheral_name: dp/dp_bsn_monitor_v2
     peripheral_group: bsn_align_input
     parameter_overrides:
       - { name: g_nof_streams, value: c_P_sq }
     mm_port_names:
-      - REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT
+      - REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT
   
   - peripheral_name: dp/dp_bsn_monitor_v2
     peripheral_group: bsn_align_output
     parameter_overrides:
       - { name: g_nof_streams, value: 1 }
     mm_port_names:
-      - REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT
+      - REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT
   
   - peripheral_name: dp/dp_bsn_monitor_v2
     peripheral_group: xst_udp
     parameter_overrides:
       - { name: g_nof_streams, value: 1 }
     mm_port_names:
-      - REG_XST_UDP_MONITOR
+      - REG_BSN_MONITOR_V2_XST_OFFLOAD
   
   - peripheral_name: ring/ring_lane_info
     peripheral_group: xsub
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
index e0b793d115..f91ded3ee6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
@@ -2302,7 +2302,7 @@
         <ipxact:parameter parameterId="dataSlaveMapParam" type="string">
           <ipxact:name>dataSlaveMapParam</ipxact:name>
           <ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
-          <ipxact:value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_input.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C400' end='0x10C440' datawidth='32' /&gt;&lt;slave name='reg_bsn_align.mem' start='0x10C440' end='0x10C480' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C540' end='0x10C580' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C580' end='0x10C5A0' datawidth='32' /&gt;&lt;slave name='reg_xst_udp_monitor.mem' start='0x10C5A0' end='0x10C5C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_output.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10C600' end='0x10C620' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10C620' end='0x10C640' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10C640' end='0x10C660' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10C660' end='0x10C670' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C670' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10C680' end='0x10C690' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10C690' end='0x10C6A0' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10C6C0' end='0x10C6C8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10C6C8' end='0x10C6D0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10C6D0' end='0x10C6D8' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10C6D8' end='0x10C6E0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C6E0' end='0x10C6E8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10C6E8' end='0x10C6F0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10C6F0' end='0x10C6F8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10C6F8' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10C700' end='0x10C708' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10C708' end='0x10C710' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10C710' end='0x10C718' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C720' end='0x10C728' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</ipxact:value>
+          <ipxact:value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_v2_input.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x10C400' end='0x10C480' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C540' end='0x10C580' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_v2_output.mem' start='0x10C600' end='0x10C620' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10C620' end='0x10C640' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10C640' end='0x10C660' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10C660' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10C680' end='0x10C6A0' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10C6C0' end='0x10C6D0' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10C6D0' end='0x10C6E0' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10C6E0' end='0x10C6F0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10C6F0' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10C700' end='0x10C708' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10C708' end='0x10C710' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10C710' end='0x10C718' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C720' end='0x10C728' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10C728' end='0x10C730' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10C730' end='0x10C738' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10C738' end='0x10C740' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10C740' end='0x10C748' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10C748' end='0x10C750' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10C750' end='0x10C758' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10C758' end='0x10C760' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C760' end='0x10C768' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
           <ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3589,7 +3589,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_v2_bsn_align_input.mem' start='0x200' end='0x400' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&amp;gt;&amp;lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&amp;gt;&amp;lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&amp;gt;&amp;lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&amp;gt;&amp;lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&amp;gt;&amp;lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C400' end='0x10C440' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_align.mem' start='0x10C440' end='0x10C480' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_crosslets_info.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_sdp_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C540' end='0x10C580' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C580' end='0x10C5A0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_xst_udp_monitor.mem' start='0x10C5A0' end='0x10C5C0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_v2_bsn_align_output.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_source_v2.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_fpga_temp_sens.mem' start='0x10C600' end='0x10C620' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_epcs.mem' start='0x10C620' end='0x10C640' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_remu.mem' start='0x10C640' end='0x10C660' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_ring_info.mem' start='0x10C660' end='0x10C670' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C670' end='0x10C680' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_enable_bst.mem' start='0x10C680' end='0x10C690' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_xonoff.mem' start='0x10C690' end='0x10C6A0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bf_scale.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_pps.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_nof_crosslets.mem' start='0x10C6C0' end='0x10C6C8' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_enable_xst.mem' start='0x10C6C8' end='0x10C6D0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_enable_sst.mem' start='0x10C6D0' end='0x10C6D8' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_jesd_ctrl.mem' start='0x10C6D8' end='0x10C6E0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C6E0' end='0x10C6E8' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_selector.mem' start='0x10C6E8' end='0x10C6F0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_scheduler.mem' start='0x10C6F0' end='0x10C6F8' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_si.mem' start='0x10C6F8' end='0x10C700' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_mmdp_data.mem' start='0x10C700' end='0x10C708' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_mmdp_ctrl.mem' start='0x10C708' end='0x10C710' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dpmm_data.mem' start='0x10C710' end='0x10C718' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dpmm_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /&amp;gt;&amp;lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C720' end='0x10C728' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_align_v2.mem' start='0x80' end='0x100' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_v2_bsn_align_v2_input.mem' start='0x200' end='0x400' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&amp;gt;&amp;lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&amp;gt;&amp;lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&amp;gt;&amp;lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&amp;gt;&amp;lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&amp;gt;&amp;lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_shiftram.mem' start='0x10C400' end='0x10C480' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_crosslets_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_sdp_info.mem' start='0x10C540' end='0x10C580' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_v2_bsn_align_v2_output.mem' start='0x10C600' end='0x10C620' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_source_v2.mem' start='0x10C620' end='0x10C640' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_fpga_temp_sens.mem' start='0x10C640' end='0x10C660' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_epcs.mem' start='0x10C660' end='0x10C680' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_remu.mem' start='0x10C680' end='0x10C6A0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_ring_info.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_enable_bst.mem' start='0x10C6C0' end='0x10C6D0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_xonoff.mem' start='0x10C6D0' end='0x10C6E0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bf_scale.mem' start='0x10C6E0' end='0x10C6F0' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_pps.mem' start='0x10C6F0' end='0x10C700' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_nof_crosslets.mem' start='0x10C700' end='0x10C708' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_enable_xst.mem' start='0x10C708' end='0x10C710' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_stat_enable_sst.mem' start='0x10C710' end='0x10C718' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_jesd_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C720' end='0x10C728' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_selector.mem' start='0x10C728' end='0x10C730' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_scheduler.mem' start='0x10C730' end='0x10C738' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_si.mem' start='0x10C738' end='0x10C740' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_mmdp_data.mem' start='0x10C740' end='0x10C748' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_mmdp_ctrl.mem' start='0x10C748' end='0x10C750' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dpmm_data.mem' start='0x10C750' end='0x10C758' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dpmm_ctrl.mem' start='0x10C758' end='0x10C760' datawidth='32' /&amp;gt;&amp;lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C760' end='0x10C768' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
rename to applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
index aace048703..a36f15b68a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
@@ -1,8 +1,8 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_align</ipxact:library>
-  <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_align</ipxact:name>
+  <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
     <ipxact:busInterface>
@@ -139,7 +139,7 @@
         <ipxact:parameter parameterId="addressSpan" type="string">
           <ipxact:name>addressSpan</ipxact:name>
           <ipxact:displayName>Address span</ipxact:displayName>
-          <ipxact:value>64</ipxact:value>
+          <ipxact:value>128</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="addressUnits" type="string">
           <ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>3</ipxact:right>
+              <ipxact:right>4</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>3</ipxact:right>
+              <ipxact:right>4</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -851,7 +851,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_align</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -860,7 +860,7 @@
         <ipxact:parameter parameterId="g_adr_w" type="int">
           <ipxact:name>g_adr_w</ipxact:name>
           <ipxact:displayName>g_adr_w</ipxact:displayName>
-          <ipxact:value>4</ipxact:value>
+          <ipxact:value>5</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="g_dat_w" type="int">
           <ipxact:name>g_dat_w</ipxact:name>
@@ -909,7 +909,7 @@
          type = "String";
       }
    }
-   element qsys_lofar2_unb2c_sdp_station_reg_bsn_align
+   element qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2
    {
    }
 }
@@ -997,7 +997,7 @@
                     &lt;name&gt;avs_mem_address&lt;/name&gt;
                     &lt;role&gt;address&lt;/role&gt;
                     &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;4&lt;/width&gt;
+                    &lt;width&gt;5&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1066,7 +1066,7 @@
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressSpan&lt;/key&gt;
-                        &lt;value&gt;64&lt;/value&gt;
+                        &lt;value&gt;128&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressUnits&lt;/key&gt;
@@ -1295,7 +1295,7 @@
                     &lt;name&gt;coe_address_export&lt;/name&gt;
                     &lt;role&gt;export&lt;/role&gt;
                     &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;4&lt;/width&gt;
+                    &lt;width&gt;5&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1462,11 +1462,11 @@
                 &lt;consumedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
-                        &lt;value&gt;6&lt;/value&gt;
+                        &lt;value&gt;7&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
@@ -1494,38 +1494,38 @@
       </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align.address" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.address" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align.clk" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.clk" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align.mem" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.mem" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align.read" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.read" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align.readdata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.readdata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align.reset" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.reset" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align.system" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.system" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align.system_reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.system_reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align.write" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.write" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align.writedata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.writedata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
rename to applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
index 7561ca7480..e9f5a18d77 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
@@ -1,8 +1,8 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input</ipxact:library>
-  <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input</ipxact:name>
+  <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
     <ipxact:busInterface>
@@ -851,7 +851,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -909,7 +909,7 @@
          type = "String";
       }
    }
-   element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input
+   element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input
    {
    }
 }
@@ -1494,38 +1494,38 @@
       </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.address" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.address" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.clk" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.clk" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.mem" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.mem" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.read" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.read" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.readdata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.readdata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.reset" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.reset" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.system" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.system" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.system_reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.system_reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.write" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.write" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.writedata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.writedata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
rename to applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
index c45820e24e..418509f913 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
@@ -1,8 +1,8 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output</ipxact:library>
-  <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output</ipxact:name>
+  <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
     <ipxact:busInterface>
@@ -851,7 +851,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -909,7 +909,7 @@
          type = "String";
       }
    }
-   element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output
+   element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output
    {
    }
 }
@@ -1494,38 +1494,38 @@
       </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.address" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.address" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.clk" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.clk" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.mem" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.mem" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.read" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.read" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.readdata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.readdata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.reset" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.reset" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.system" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.system" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.system_reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.system_reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.write" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.write" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.writedata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.writedata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.ip
rename to applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
index 4d9ca9f87a..5d07f8f5df 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
@@ -1,8 +1,8 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor</ipxact:library>
-  <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor</ipxact:name>
+  <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
     <ipxact:busInterface>
@@ -851,7 +851,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -909,7 +909,7 @@
          type = "String";
       }
    }
-   element qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor
+   element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload
    {
    }
 }
@@ -1494,38 +1494,38 @@
       </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.address" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.address" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.clk" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.clk" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.mem" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.mem" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.read" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.read" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.readdata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.readdata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.reset" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.reset" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.system" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.system" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.system_reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.system_reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.write" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.write" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.writedata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.writedata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
index 576264761a..81c0f091da 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
@@ -99,7 +99,7 @@
    {
       datum baseAddress
       {
-         value = "1099552";
+         value = "1099616";
          type = "String";
       }
    }
@@ -144,7 +144,7 @@
    {
       datum baseAddress
       {
-         value = "1099480";
+         value = "1099544";
          type = "String";
       }
    }
@@ -165,7 +165,7 @@
    {
       datum baseAddress
       {
-         value = "1099440";
+         value = "1099504";
          type = "String";
       }
    }
@@ -410,11 +410,11 @@
    {
       datum baseAddress
       {
-         value = "1099424";
+         value = "1099488";
          type = "String";
       }
    }
-   element reg_bsn_align
+   element reg_bsn_align_v2
    {
       datum _sortIndex
       {
@@ -422,11 +422,11 @@
          type = "int";
       }
    }
-   element reg_bsn_align.mem
+   element reg_bsn_align_v2.mem
    {
       datum baseAddress
       {
-         value = "1098816";
+         value = "128";
          type = "String";
       }
    }
@@ -446,7 +446,7 @@
          type = "String";
       }
    }
-   element reg_bsn_monitor_v2_bsn_align_input
+   element reg_bsn_monitor_v2_bsn_align_v2_input
    {
       datum _sortIndex
       {
@@ -454,7 +454,7 @@
          type = "int";
       }
    }
-   element reg_bsn_monitor_v2_bsn_align_input.mem
+   element reg_bsn_monitor_v2_bsn_align_v2_input.mem
    {
       datum baseAddress
       {
@@ -462,7 +462,7 @@
          type = "String";
       }
    }
-   element reg_bsn_monitor_v2_bsn_align_output
+   element reg_bsn_monitor_v2_bsn_align_v2_output
    {
       datum _sortIndex
       {
@@ -470,11 +470,11 @@
          type = "int";
       }
    }
-   element reg_bsn_monitor_v2_bsn_align_output.mem
+   element reg_bsn_monitor_v2_bsn_align_v2_output.mem
    {
       datum baseAddress
       {
-         value = "1099200";
+         value = "1099264";
          type = "String";
       }
    }
@@ -510,6 +510,22 @@
          type = "String";
       }
    }
+   element reg_bsn_monitor_v2_xst_offload
+   {
+      datum _sortIndex
+      {
+         value = "59";
+         type = "int";
+      }
+   }
+   element reg_bsn_monitor_v2_xst_offload.mem
+   {
+      datum baseAddress
+      {
+         value = "1099232";
+         type = "String";
+      }
+   }
    element reg_bsn_scheduler
    {
       datum _sortIndex
@@ -522,7 +538,7 @@
    {
       datum baseAddress
       {
-         value = "1099504";
+         value = "1099568";
          type = "String";
       }
    }
@@ -538,7 +554,7 @@
    {
       datum baseAddress
       {
-         value = "1099232";
+         value = "1099296";
          type = "String";
       }
    }
@@ -554,7 +570,7 @@
    {
       datum baseAddress
       {
-         value = "1098880";
+         value = "1098944";
          type = "String";
       }
    }
@@ -570,7 +586,7 @@
    {
       datum baseAddress
       {
-         value = "1098944";
+         value = "1099008";
          type = "String";
       }
    }
@@ -586,7 +602,7 @@
    {
       datum baseAddress
       {
-         value = "128";
+         value = "12416";
          type = "String";
       }
    }
@@ -602,7 +618,7 @@
    {
       datum baseAddress
       {
-         value = "1099376";
+         value = "1099440";
          type = "String";
       }
    }
@@ -618,7 +634,7 @@
    {
       datum baseAddress
       {
-         value = "1098752";
+         value = "1098880";
          type = "String";
       }
    }
@@ -634,7 +650,7 @@
    {
       datum baseAddress
       {
-         value = "1099496";
+         value = "1099560";
          type = "String";
       }
    }
@@ -650,7 +666,7 @@
    {
       datum baseAddress
       {
-         value = "12416";
+         value = "1098752";
          type = "String";
       }
    }
@@ -666,7 +682,7 @@
    {
       datum baseAddress
       {
-         value = "1099408";
+         value = "1099472";
          type = "String";
       }
    }
@@ -687,7 +703,7 @@
    {
       datum baseAddress
       {
-         value = "1099544";
+         value = "1099608";
          type = "String";
       }
    }
@@ -708,7 +724,7 @@
    {
       datum baseAddress
       {
-         value = "1099536";
+         value = "1099600";
          type = "String";
       }
    }
@@ -729,7 +745,7 @@
    {
       datum baseAddress
       {
-         value = "1099296";
+         value = "1099360";
          type = "String";
       }
    }
@@ -745,7 +761,7 @@
    {
       datum baseAddress
       {
-         value = "1099264";
+         value = "1099328";
          type = "String";
       }
    }
@@ -766,7 +782,7 @@
    {
       datum baseAddress
       {
-         value = "1099072";
+         value = "1099136";
          type = "String";
       }
    }
@@ -803,7 +819,7 @@
    {
       datum baseAddress
       {
-         value = "1099528";
+         value = "1099592";
          type = "String";
       }
    }
@@ -824,7 +840,7 @@
    {
       datum baseAddress
       {
-         value = "1099520";
+         value = "1099584";
          type = "String";
       }
    }
@@ -840,7 +856,7 @@
    {
       datum baseAddress
       {
-         value = "1099456";
+         value = "1099520";
          type = "String";
       }
    }
@@ -856,7 +872,7 @@
    {
       datum baseAddress
       {
-         value = "1099488";
+         value = "1099552";
          type = "String";
       }
    }
@@ -893,7 +909,7 @@
    {
       datum baseAddress
       {
-         value = "1099328";
+         value = "1099392";
          type = "String";
       }
    }
@@ -909,7 +925,7 @@
    {
       datum baseAddress
       {
-         value = "1099360";
+         value = "1099424";
          type = "String";
       }
    }
@@ -941,7 +957,7 @@
    {
       datum baseAddress
       {
-         value = "1099008";
+         value = "1099072";
          type = "String";
       }
    }
@@ -957,7 +973,7 @@
    {
       datum baseAddress
       {
-         value = "1099512";
+         value = "1099576";
          type = "String";
       }
    }
@@ -973,7 +989,7 @@
    {
       datum baseAddress
       {
-         value = "1099392";
+         value = "1099456";
          type = "String";
       }
    }
@@ -989,7 +1005,7 @@
    {
       datum baseAddress
       {
-         value = "1099472";
+         value = "1099536";
          type = "String";
       }
    }
@@ -1005,7 +1021,7 @@
    {
       datum baseAddress
       {
-         value = "1099464";
+         value = "1099528";
          type = "String";
       }
    }
@@ -1069,7 +1085,7 @@
    {
       datum baseAddress
       {
-         value = "1099136";
+         value = "1099200";
          type = "String";
       }
    }
@@ -1131,22 +1147,6 @@
          type = "String";
       }
    }
-   element reg_xst_udp_monitor
-   {
-      datum _sortIndex
-      {
-         value = "59";
-         type = "int";
-      }
-   }
-   element reg_xst_udp_monitor.mem
-   {
-      datum baseAddress
-      {
-         value = "1099168";
-         type = "String";
-      }
-   }
    element rom_system_info
    {
       datum _sortIndex
@@ -1893,38 +1893,38 @@
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_align_address"
-   internal="reg_bsn_align.address"
+   name="reg_bsn_align_v2_address"
+   internal="reg_bsn_align_v2.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_align_clk"
-   internal="reg_bsn_align.clk"
+   name="reg_bsn_align_v2_clk"
+   internal="reg_bsn_align_v2.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_align_read"
-   internal="reg_bsn_align.read"
+   name="reg_bsn_align_v2_read"
+   internal="reg_bsn_align_v2.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_align_readdata"
-   internal="reg_bsn_align.readdata"
+   name="reg_bsn_align_v2_readdata"
+   internal="reg_bsn_align_v2.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_align_reset"
-   internal="reg_bsn_align.reset"
+   name="reg_bsn_align_v2_reset"
+   internal="reg_bsn_align_v2.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_align_write"
-   internal="reg_bsn_align.write"
+   name="reg_bsn_align_v2_write"
+   internal="reg_bsn_align_v2.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_align_writedata"
-   internal="reg_bsn_align.writedata"
+   name="reg_bsn_align_v2_writedata"
+   internal="reg_bsn_align_v2.writedata"
    type="conduit"
    dir="end" />
  <interface
@@ -1963,73 +1963,73 @@
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_input_address"
-   internal="reg_bsn_monitor_v2_bsn_align_input.address"
+   name="reg_bsn_monitor_v2_bsn_align_v2_input_address"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_input.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_input_clk"
-   internal="reg_bsn_monitor_v2_bsn_align_input.clk"
+   name="reg_bsn_monitor_v2_bsn_align_v2_input_clk"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_input.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_input_read"
-   internal="reg_bsn_monitor_v2_bsn_align_input.read"
+   name="reg_bsn_monitor_v2_bsn_align_v2_input_read"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_input.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_input_readdata"
-   internal="reg_bsn_monitor_v2_bsn_align_input.readdata"
+   name="reg_bsn_monitor_v2_bsn_align_v2_input_readdata"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_input.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_input_reset"
-   internal="reg_bsn_monitor_v2_bsn_align_input.reset"
+   name="reg_bsn_monitor_v2_bsn_align_v2_input_reset"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_input.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_input_write"
-   internal="reg_bsn_monitor_v2_bsn_align_input.write"
+   name="reg_bsn_monitor_v2_bsn_align_v2_input_write"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_input.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_input_writedata"
-   internal="reg_bsn_monitor_v2_bsn_align_input.writedata"
+   name="reg_bsn_monitor_v2_bsn_align_v2_input_writedata"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_input.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_output_address"
-   internal="reg_bsn_monitor_v2_bsn_align_output.address"
+   name="reg_bsn_monitor_v2_bsn_align_v2_output_address"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_output.address"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_output_clk"
-   internal="reg_bsn_monitor_v2_bsn_align_output.clk"
+   name="reg_bsn_monitor_v2_bsn_align_v2_output_clk"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_output.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_output_read"
-   internal="reg_bsn_monitor_v2_bsn_align_output.read"
+   name="reg_bsn_monitor_v2_bsn_align_v2_output_read"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_output.read"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_output_readdata"
-   internal="reg_bsn_monitor_v2_bsn_align_output.readdata"
+   name="reg_bsn_monitor_v2_bsn_align_v2_output_readdata"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_output.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_output_reset"
-   internal="reg_bsn_monitor_v2_bsn_align_output.reset"
+   name="reg_bsn_monitor_v2_bsn_align_v2_output_reset"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_output.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_output_write"
-   internal="reg_bsn_monitor_v2_bsn_align_output.write"
+   name="reg_bsn_monitor_v2_bsn_align_v2_output_write"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_output.write"
    type="conduit"
    dir="end" />
  <interface
-   name="reg_bsn_monitor_v2_bsn_align_output_writedata"
-   internal="reg_bsn_monitor_v2_bsn_align_output.writedata"
+   name="reg_bsn_monitor_v2_bsn_align_v2_output_writedata"
+   internal="reg_bsn_monitor_v2_bsn_align_v2_output.writedata"
    type="conduit"
    dir="end" />
  <interface
@@ -2102,6 +2102,41 @@
    internal="reg_bsn_monitor_v2_ring_tx_xst.writedata"
    type="conduit"
    dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_xst_offload_address"
+   internal="reg_bsn_monitor_v2_xst_offload.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_xst_offload_clk"
+   internal="reg_bsn_monitor_v2_xst_offload.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_xst_offload_read"
+   internal="reg_bsn_monitor_v2_xst_offload.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_xst_offload_readdata"
+   internal="reg_bsn_monitor_v2_xst_offload.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_xst_offload_reset"
+   internal="reg_bsn_monitor_v2_xst_offload.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_xst_offload_write"
+   internal="reg_bsn_monitor_v2_xst_offload.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_xst_offload_writedata"
+   internal="reg_bsn_monitor_v2_xst_offload.writedata"
+   type="conduit"
+   dir="end" />
  <interface
    name="reg_bsn_scheduler_address"
    internal="reg_bsn_scheduler.address"
@@ -3314,41 +3349,6 @@
    internal="reg_wg.writedata"
    type="conduit"
    dir="end" />
- <interface
-   name="reg_xst_udp_monitor_address"
-   internal="reg_xst_udp_monitor.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_xst_udp_monitor_clk"
-   internal="reg_xst_udp_monitor.clk"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_xst_udp_monitor_read"
-   internal="reg_xst_udp_monitor.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_xst_udp_monitor_readdata"
-   internal="reg_xst_udp_monitor.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_xst_udp_monitor_reset"
-   internal="reg_xst_udp_monitor.reset"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_xst_udp_monitor_write"
-   internal="reg_xst_udp_monitor.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_xst_udp_monitor_writedata"
-   internal="reg_xst_udp_monitor.writedata"
-   type="conduit"
-   dir="end" />
  <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
  <interface
    name="rom_system_info_address"
@@ -7936,7 +7936,7 @@
                     <consumedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_input.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C400' end='0x10C440' datawidth='32' /&gt;&lt;slave name='reg_bsn_align.mem' start='0x10C440' end='0x10C480' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C540' end='0x10C580' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C580' end='0x10C5A0' datawidth='32' /&gt;&lt;slave name='reg_xst_udp_monitor.mem' start='0x10C5A0' end='0x10C5C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_output.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10C600' end='0x10C620' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10C620' end='0x10C640' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10C640' end='0x10C660' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10C660' end='0x10C670' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C670' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10C680' end='0x10C690' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10C690' end='0x10C6A0' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10C6C0' end='0x10C6C8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10C6C8' end='0x10C6D0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10C6D0' end='0x10C6D8' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10C6D8' end='0x10C6E0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C6E0' end='0x10C6E8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10C6E8' end='0x10C6F0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10C6F0' end='0x10C6F8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10C6F8' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10C700' end='0x10C708' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10C708' end='0x10C710' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10C710' end='0x10C718' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C720' end='0x10C728' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_v2_input.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x10C400' end='0x10C480' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C540' end='0x10C580' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_v2_output.mem' start='0x10C600' end='0x10C620' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10C620' end='0x10C640' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10C640' end='0x10C660' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10C660' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10C680' end='0x10C6A0' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10C6C0' end='0x10C6D0' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10C6D0' end='0x10C6E0' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10C6E0' end='0x10C6F0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10C6F0' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10C700' end='0x10C708' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10C708' end='0x10C710' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10C710' end='0x10C718' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C720' end='0x10C728' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10C728' end='0x10C730' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10C730' end='0x10C738' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10C738' end='0x10C740' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10C740' end='0x10C748' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10C748' end='0x10C750' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10C750' end='0x10C758' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10C758' end='0x10C760' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C760' end='0x10C768' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
@@ -31468,7 +31468,7 @@
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_bsn_align"
+   name="reg_bsn_align_v2"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -31547,7 +31547,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>4</width>
+                        <width>5</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -31616,7 +31616,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>64</value>
+                            <value>128</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -31845,7 +31845,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>4</width>
+                        <width>5</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -32023,11 +32023,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>6</value>
+                            <value>7</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32127,7 +32127,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>4</width>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -32196,7 +32196,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>64</value>
+                        <value>128</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -32425,7 +32425,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>4</width>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -32579,30 +32579,30 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
@@ -33750,7 +33750,7 @@
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_bsn_monitor_v2_bsn_align_input"
+   name="reg_bsn_monitor_v2_bsn_align_v2_input"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -34861,37 +34861,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">/home/walle/git-lofar/hdl/build/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_bsn_monitor_v2_bsn_align_output"
+   name="reg_bsn_monitor_v2_bsn_align_v2_output"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -36002,30 +36002,30 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">/home/walle/git-lofar/hdl/build/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
@@ -38314,7 +38314,7 @@
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_bsn_scheduler"
+   name="reg_bsn_monitor_v2_xst_offload"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -38322,17 +38322,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -38341,27 +38341,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -38374,13 +38375,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -38394,7 +38393,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -38463,7 +38462,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -38620,12 +38619,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -38652,17 +38651,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
+                        <direction>Output</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -38684,17 +38683,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>address</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -38716,14 +38715,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>write</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -38735,31 +38734,30 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>writedata</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -38769,22 +38767,24 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -38811,14 +38811,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
+                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -38869,11 +38869,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -38902,17 +38902,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>address</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -38921,27 +38921,28 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -38954,13 +38955,11 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -38974,7 +38973,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -39043,7 +39042,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>8</value>
+                        <value>32</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -39200,12 +39199,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -39232,17 +39231,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>clk</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_clk_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
+                    <direction>Output</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -39264,17 +39263,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>address</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -39296,14 +39295,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>write</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -39315,31 +39314,30 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>writedata</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -39349,22 +39347,24 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -39391,14 +39391,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
+                    <direction>Input</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -39425,37 +39425,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_bsn_source_v2"
+   name="reg_bsn_scheduler"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -39471,7 +39471,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -39535,7 +39535,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -39604,7 +39604,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -40010,11 +40010,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -40051,7 +40051,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>3</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -40115,7 +40115,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>3</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -40184,7 +40184,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>32</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -40566,37 +40566,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_bsn_sync_scheduler_xsub"
+   name="reg_bsn_source_v2"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -40604,17 +40604,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -40623,28 +40623,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -40657,11 +40656,13 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -40675,7 +40676,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>4</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -40744,7 +40745,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>64</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -40900,6 +40901,70 @@
                     </parameterValueMap>
                 </parameters>
             </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
             <interface>
                 <name>reset</name>
                 <type>conduit</type>
@@ -40933,14 +40998,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -40952,30 +41017,31 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>4</width>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -40985,13 +41051,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -41060,70 +41124,6 @@
                     </parameterValueMap>
                 </parameters>
             </interface>
-            <interface>
-                <name>read</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_read_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>readdata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_readdata_export</name>
-                        <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
         </interfaces>
     </boundary>
     <originalModuleInfo>
@@ -41151,11 +41151,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>6</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -41184,17 +41184,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -41203,28 +41203,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -41237,11 +41236,13 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -41255,7 +41256,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>4</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -41324,7 +41325,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>64</value>
+                        <value>32</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -41481,108 +41482,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_reset_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>clk</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>address</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>4</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>write</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -41609,14 +41514,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
+                    <direction>Input</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -41641,12 +41546,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -41673,14 +41578,109 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_write_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -41707,37 +41707,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_crosslets_info"
+   name="reg_bsn_sync_scheduler_xsub"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -41745,17 +41745,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>4</width>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -41764,27 +41764,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -41797,13 +41798,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -42043,12 +42042,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -42075,44 +42074,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_readdata_export</name>
-                        <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>reset</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -42139,80 +42106,49 @@
                 </parameters>
             </interface>
             <interface>
-                <name>system</name>
-                <type>clock</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>ptfSchematicName</key>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>system_reset</name>
-                <type>reset</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                            <value>system</value>
-                        </entry>
-                        <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>write</name>
+                <name>address</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -42265,6 +42201,70 @@
                     </parameterValueMap>
                 </parameters>
             </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
         </interfaces>
     </boundary>
     <originalModuleInfo>
@@ -42325,17 +42325,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>address</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>4</width>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -42344,27 +42344,28 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -42377,13 +42378,11 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -42622,70 +42621,6 @@
                 </parameterValueMap>
             </parameters>
         </interface>
-        <interface>
-            <name>read</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_read_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>readdata</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_readdata_export</name>
-                    <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
         <interface>
             <name>reset</name>
             <type>conduit</type>
@@ -42719,75 +42654,76 @@
             </parameters>
         </interface>
         <interface>
-            <name>system</name>
-            <type>clock</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>ptfSchematicName</key>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>system_reset</name>
-            <type>reset</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                        <value>system</value>
-                    </entry>
-                    <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>write</name>
+            <name>clk</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -42845,40 +42781,104 @@
                 </parameterValueMap>
             </parameters>
         </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_diag_data_buffer_bsn"
+   name="reg_crosslets_info"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -42894,7 +42894,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>5</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -42958,7 +42958,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>5</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -43027,7 +43027,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>128</value>
+                            <value>64</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -43433,11 +43433,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>7</value>
+                            <value>6</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -43474,7 +43474,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>5</width>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -43538,7 +43538,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>5</width>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -43607,7 +43607,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>128</value>
+                        <value>64</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -43989,37 +43989,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dp_block_validate_bsn_at_sync_xst"
+   name="reg_diag_data_buffer_bsn"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -44027,17 +44027,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>5</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -44046,28 +44046,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -44080,11 +44079,13 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -44098,7 +44099,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>2</width>
+                        <width>5</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -44167,7 +44168,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16</value>
+                            <value>128</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -44324,12 +44325,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -44356,12 +44357,44 @@
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>reset</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -44388,46 +44421,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>2</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>write</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -44439,30 +44440,31 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>32</width>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -44472,24 +44474,22 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>write</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_write_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -44516,14 +44516,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>writedata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_writedata_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
+                        <direction>Output</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -44574,11 +44574,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>4</value>
+                            <value>7</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -44607,17 +44607,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -44626,28 +44626,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -44660,11 +44659,13 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -44678,7 +44679,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>2</width>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -44747,7 +44748,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>16</value>
+                        <value>128</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -44903,6 +44904,70 @@
                 </parameterValueMap>
             </parameters>
         </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
         <interface>
             <name>reset</name>
             <type>conduit</type>
@@ -44936,76 +45001,75 @@
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>address</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>2</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>write</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_write_export</name>
+                    <name>coe_write_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -45063,104 +45127,40 @@
                 </parameterValueMap>
             </parameters>
         </interface>
-        <interface>
-            <name>read</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_read_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>readdata</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_readdata_export</name>
-                    <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dp_block_validate_err_xst"
+   name="reg_dp_block_validate_bsn_at_sync_xst"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -45239,7 +45239,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>4</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -45308,7 +45308,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>64</value>
+                            <value>16</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -45537,7 +45537,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>4</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -45715,11 +45715,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>6</value>
+                            <value>4</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -45819,7 +45819,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>4</width>
+                    <width>2</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -45888,7 +45888,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>64</value>
+                        <value>16</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -46117,7 +46117,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>4</width>
+                    <width>2</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -46271,37 +46271,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dp_selector"
+   name="reg_dp_block_validate_err_xst"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -46309,17 +46309,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -46328,27 +46328,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -46361,13 +46362,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -46381,7 +46380,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -46450,7 +46449,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>64</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -46607,12 +46606,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -46639,44 +46638,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_readdata_export</name>
-                        <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>reset</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -46703,17 +46670,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -46722,28 +46689,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>write</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -46756,22 +46722,56 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
+                <name>writedata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -46798,14 +46798,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
+                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -46856,11 +46856,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>6</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -46889,17 +46889,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>address</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -46908,27 +46908,28 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -46941,13 +46942,11 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -46961,7 +46960,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -47030,7 +47029,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>8</value>
+                        <value>64</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -47187,12 +47186,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -47219,17 +47218,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>clk</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_clk_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
+                    <direction>Output</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -47251,17 +47250,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>address</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -47283,14 +47282,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>write</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -47302,31 +47301,30 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>writedata</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -47336,22 +47334,24 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -47378,14 +47378,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
+                    <direction>Input</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -47412,37 +47412,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dp_shiftram"
+   name="reg_dp_selector"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -47458,7 +47458,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>5</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -47522,7 +47522,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>5</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -47591,7 +47591,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>128</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -47997,11 +47997,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>7</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -48038,7 +48038,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>5</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -48102,7 +48102,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>5</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -48171,7 +48171,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>128</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -48553,37 +48553,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dp_xonoff"
+   name="reg_dp_shiftram"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -48599,7 +48599,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>2</width>
+                        <width>5</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -48663,7 +48663,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>2</width>
+                        <width>5</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -48732,7 +48732,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16</value>
+                            <value>128</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -49138,11 +49138,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>4</value>
+                            <value>7</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -49179,7 +49179,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>2</width>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -49243,7 +49243,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>2</width>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -49312,7 +49312,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>16</value>
+                        <value>128</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -49694,37 +49694,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dpmm_ctrl"
+   name="reg_dp_xonoff"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -49740,7 +49740,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -49804,7 +49804,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -49873,7 +49873,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>16</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -50279,11 +50279,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>4</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -50320,7 +50320,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>2</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -50384,7 +50384,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>2</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -50453,7 +50453,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>8</value>
+                        <value>16</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -50835,37 +50835,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dpmm_data"
+   name="reg_dpmm_ctrl"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -51976,37 +51976,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_epcs"
+   name="reg_dpmm_data"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -52022,7 +52022,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -52086,7 +52086,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -52155,7 +52155,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -52561,11 +52561,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -52602,7 +52602,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>3</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -52666,7 +52666,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>3</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -52735,7 +52735,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>32</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -53117,37 +53117,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_epcs</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_fpga_temp_sens"
+   name="reg_epcs"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -54258,37 +54258,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_epcs</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_fpga_voltage_sens"
+   name="reg_fpga_temp_sens"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -54304,7 +54304,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>4</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -54368,7 +54368,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>4</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -54437,7 +54437,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>64</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -54843,11 +54843,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>6</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -54884,7 +54884,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>4</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -54948,7 +54948,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>4</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -55017,7 +55017,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>64</value>
+                        <value>32</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -55399,37 +55399,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_hdr_dat"
+   name="reg_fpga_voltage_sens"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -55445,7 +55445,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>7</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -55509,7 +55509,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>7</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -55578,7 +55578,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>512</value>
+                            <value>64</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -55984,11 +55984,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>9</value>
+                            <value>6</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -56025,7 +56025,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>7</width>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -56089,7 +56089,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>7</width>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -56158,7 +56158,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>512</value>
+                        <value>64</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -56540,37 +56540,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_mmdp_ctrl"
+   name="reg_hdr_dat"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -56586,7 +56586,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>7</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -56650,7 +56650,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>7</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -56719,7 +56719,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>512</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -57125,11 +57125,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>9</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -57166,7 +57166,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>7</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -57230,7 +57230,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>7</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -57299,7 +57299,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>8</value>
+                        <value>512</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -57681,37 +57681,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_mmdp_data"
+   name="reg_mmdp_ctrl"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -58822,37 +58822,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_nof_crosslets"
+   name="reg_mmdp_data"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -58860,17 +58860,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -58879,28 +58879,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -58913,11 +58912,13 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -59157,12 +59158,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -59189,17 +59190,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
+                        <direction>Input</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -59221,17 +59222,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>address</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -59253,14 +59254,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -59272,30 +59273,61 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_write_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>32</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -59317,46 +59349,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>writedata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_writedata_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>readdata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_readdata_export</name>
-                        <role>export</role>
-                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -59440,17 +59440,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -59459,28 +59459,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -59493,11 +59492,13 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -59737,12 +59738,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -59769,17 +59770,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
+                    <direction>Input</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -59801,17 +59802,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>address</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -59833,14 +59834,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -59852,30 +59853,31 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>32</width>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -59885,24 +59887,22 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>write</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_write_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -59929,14 +59929,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>writedata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_writedata_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
+                    <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -59963,37 +59963,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_nw_10gbe_eth10g"
+   name="reg_nof_crosslets"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -60001,17 +60001,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -60020,27 +60020,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -60053,13 +60054,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -60299,12 +60298,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -60331,15 +60330,47 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>address</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -60363,17 +60394,49 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_writedata_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -60395,75 +60458,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>system</name>
-                <type>clock</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>ptfSchematicName</key>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>system_reset</name>
-                <type>reset</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                            <value>system</value>
-                        </entry>
-                        <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>write</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -60490,14 +60490,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
+                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -60581,17 +60581,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>address</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -60600,27 +60600,28 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -60633,13 +60634,11 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -60879,12 +60878,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -60911,14 +60910,110 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>clk</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_clk_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -60943,141 +61038,46 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>system</name>
-            <type>clock</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
                     <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>ptfSchematicName</key>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>system_reset</name>
-            <type>reset</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                        <value>system</value>
-                    </entry>
-                    <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>write</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_write_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>writedata</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_writedata_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -61104,37 +61104,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_nw_10gbe_mac"
+   name="reg_nw_10gbe_eth10g"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -61150,7 +61150,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>13</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -61214,7 +61214,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>13</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -61283,7 +61283,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32768</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -61689,11 +61689,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>15</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -61730,7 +61730,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>13</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -61794,7 +61794,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>13</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -61863,7 +61863,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>32768</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -62245,37 +62245,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_remu"
+   name="reg_nw_10gbe_mac"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -62291,7 +62291,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>13</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -62355,7 +62355,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>13</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -62424,7 +62424,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>32768</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -62830,11 +62830,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>15</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -62871,7 +62871,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>3</width>
+                    <width>13</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -62935,7 +62935,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>3</width>
+                    <width>13</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -63004,7 +63004,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>32</value>
+                        <value>32768</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -63386,37 +63386,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_remu</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_ring_info"
+   name="reg_remu"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -63424,17 +63424,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -63443,28 +63443,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -63477,11 +63476,13 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -63495,7 +63496,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>2</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -63564,7 +63565,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -63721,12 +63722,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -63753,17 +63754,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
+                        <direction>Input</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -63785,17 +63786,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>address</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>2</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -63817,14 +63818,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -63836,30 +63837,31 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>32</width>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -63869,24 +63871,22 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>write</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_write_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -63913,14 +63913,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>writedata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_writedata_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
+                        <direction>Output</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -63971,11 +63971,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>4</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -64004,17 +64004,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -64023,28 +64023,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -64057,11 +64056,13 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -64075,7 +64076,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>2</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -64114,17 +64115,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -64140,7 +64145,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>16</value>
+                        <value>32</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -64164,6 +64169,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -64295,166 +64301,6 @@
                 </parameterValueMap>
             </parameters>
         </interface>
-        <interface>
-            <name>reset</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_reset_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>clk</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>address</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>2</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>write</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_write_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>writedata</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_writedata_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
         <interface>
             <name>read</name>
             <type>conduit</type>
@@ -64519,40 +64365,199 @@
                 </parameterValueMap>
             </parameters>
         </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_remu</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_ring_lane_info_xst"
+   name="reg_ring_info"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -64631,7 +64636,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -64700,7 +64705,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>16</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -64929,7 +64934,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -65107,11 +65112,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>4</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -65211,7 +65216,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>2</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -65280,7 +65285,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>8</value>
+                        <value>16</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -65509,7 +65514,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>2</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -65663,37 +65668,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_sdp_info"
+   name="reg_ring_lane_info_xst"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -65701,17 +65706,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>4</width>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -65720,27 +65725,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -65753,13 +65759,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -65773,7 +65777,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>4</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -65842,7 +65846,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>64</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -65999,12 +66003,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -66031,17 +66035,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
+                        <direction>Output</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -66063,17 +66067,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>address</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -66095,14 +66099,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>write</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -66114,31 +66118,30 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>writedata</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -66148,22 +66151,24 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -66190,14 +66195,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
+                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -66248,11 +66253,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>6</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -66281,17 +66286,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>address</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>4</width>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -66300,27 +66305,28 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -66333,13 +66339,11 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -66353,7 +66357,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>4</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -66422,7 +66426,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>64</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -66579,12 +66583,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -66611,17 +66615,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>clk</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_clk_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
+                    <direction>Output</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -66643,17 +66647,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>address</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -66675,14 +66679,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>write</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -66694,31 +66698,30 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>writedata</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -66728,22 +66731,24 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -66770,14 +66775,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
+                    <direction>Input</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -66804,37 +66809,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_si"
+   name="reg_sdp_info"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -66850,7 +66855,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -66914,7 +66919,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -66983,7 +66988,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>64</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -67389,11 +67394,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>6</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -67430,7 +67435,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -67494,7 +67499,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -67563,7 +67568,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>8</value>
+                        <value>64</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -67945,37 +67950,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_si</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_stat_enable_bst"
+   name="reg_si"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -67991,7 +67996,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>2</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -68055,7 +68060,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>2</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -68124,7 +68129,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -68530,11 +68535,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>4</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -68571,7 +68576,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>2</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -68635,7 +68640,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>2</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -68704,7 +68709,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>16</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -69086,37 +69091,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_si</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_stat_enable_sst"
+   name="reg_stat_enable_bst"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -69132,7 +69137,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -69196,7 +69201,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -69265,7 +69270,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>16</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -69671,11 +69676,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>4</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -69712,7 +69717,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>2</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -69776,7 +69781,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>2</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -69845,7 +69850,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>8</value>
+                        <value>16</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -70227,37 +70232,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_stat_enable_xst"
+   name="reg_stat_enable_sst"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -71368,37 +71373,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_stat_hdr_dat_bst"
+   name="reg_stat_enable_xst"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -71414,7 +71419,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>7</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -71478,7 +71483,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>7</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -71547,7 +71552,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>512</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -71953,11 +71958,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>9</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -71994,7 +71999,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>7</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -72058,7 +72063,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>7</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -72127,7 +72132,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>512</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -72509,37 +72514,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_stat_hdr_dat_sst"
+   name="reg_stat_hdr_dat_bst"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -72555,7 +72560,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>6</width>
+                        <width>7</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -72619,7 +72624,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>6</width>
+                        <width>7</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -72688,7 +72693,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>256</value>
+                            <value>512</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -73094,11 +73099,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>8</value>
+                            <value>9</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -73135,7 +73140,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>6</width>
+                    <width>7</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -73199,7 +73204,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>6</width>
+                    <width>7</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -73268,7 +73273,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>256</value>
+                        <value>512</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -73650,37 +73655,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_stat_hdr_dat_xst"
+   name="reg_stat_hdr_dat_sst"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -74791,37 +74796,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_tr_10gbe_eth10g"
+   name="reg_stat_hdr_dat_xst"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -74829,17 +74834,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -74848,28 +74853,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -74882,11 +74886,13 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -74900,7 +74906,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -74969,7 +74975,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>256</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -75126,12 +75132,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -75158,17 +75164,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
+                        <direction>Input</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -75190,17 +75196,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>address</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -75222,14 +75228,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -75241,30 +75247,61 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_write_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>32</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -75286,46 +75323,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>writedata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_writedata_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>readdata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_readdata_export</name>
-                        <role>export</role>
-                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -75376,11 +75381,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -75409,17 +75414,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -75428,28 +75433,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -75462,11 +75466,13 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -75480,7 +75486,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>3</width>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -75549,7 +75555,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>32</value>
+                        <value>256</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -75706,12 +75712,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -75738,17 +75744,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
+                    <direction>Input</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -75770,17 +75776,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>address</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>3</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -75802,14 +75808,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -75821,30 +75827,31 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>32</width>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -75854,24 +75861,22 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>write</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_write_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -75898,14 +75903,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>writedata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_writedata_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
+                    <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -75932,37 +75937,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_tr_10gbe_mac"
+   name="reg_tr_10gbe_eth10g"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -76041,7 +76046,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>15</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -76110,7 +76115,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>131072</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -76339,7 +76344,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>15</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -76517,11 +76522,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>17</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -76621,7 +76626,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>15</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -76690,7 +76695,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>131072</value>
+                        <value>32</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -76919,7 +76924,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>15</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -77073,37 +77078,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_wdi"
+   name="reg_tr_10gbe_mac"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -77111,17 +77116,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -77130,27 +77135,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -77163,13 +77169,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -77183,7 +77187,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>15</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -77252,7 +77256,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>131072</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -77409,12 +77413,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -77441,17 +77445,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
+                        <direction>Output</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -77473,17 +77477,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>address</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>15</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -77505,14 +77509,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>write</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -77524,31 +77528,30 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>writedata</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -77558,22 +77561,24 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -77600,14 +77605,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
+                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -77658,11 +77663,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>17</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -77691,17 +77696,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>address</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -77710,27 +77715,28 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -77743,13 +77749,11 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -77763,7 +77767,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>15</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -77832,7 +77836,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>8</value>
+                        <value>131072</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -77989,12 +77993,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -78021,17 +78025,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>clk</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_clk_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
+                    <direction>Output</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -78053,17 +78057,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>address</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>15</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -78085,14 +78089,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>write</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -78104,31 +78108,30 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>writedata</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -78138,22 +78141,24 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -78180,14 +78185,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
+                    <direction>Input</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -78214,37 +78219,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wdi</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_wg"
+   name="reg_wdi"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -78260,7 +78265,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>6</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -78324,7 +78329,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>6</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -78393,7 +78398,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>256</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -78799,11 +78804,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>8</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -78840,7 +78845,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>6</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -78904,7 +78909,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>6</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -78973,7 +78978,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>256</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -79355,37 +79360,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wg</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wdi</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_xst_udp_monitor"
+   name="reg_wg"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -79393,17 +79398,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -79412,28 +79417,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -79446,11 +79450,13 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -79464,7 +79470,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -79533,7 +79539,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>256</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -79690,12 +79696,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -79722,17 +79728,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
+                        <direction>Input</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -79754,17 +79760,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>address</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -79786,14 +79792,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -79805,30 +79811,31 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>32</width>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -79838,24 +79845,22 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>write</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_write_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -79882,14 +79887,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>writedata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_writedata_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
+                        <direction>Output</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -79940,11 +79945,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -79973,17 +79978,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -79992,28 +79997,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -80026,11 +80030,13 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -80044,7 +80050,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>3</width>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -80113,7 +80119,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>32</value>
+                        <value>256</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -80270,12 +80276,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -80302,17 +80308,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
+                    <direction>Input</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -80334,17 +80340,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>address</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>3</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -80366,14 +80372,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -80385,30 +80391,31 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>32</width>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -80418,24 +80425,22 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>write</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_write_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -80462,14 +80467,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>writedata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_writedata_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
+                    <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -80496,30 +80501,30 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wg</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
@@ -82976,7 +82981,7 @@
    start="cpu_0.data_master"
    end="jtag_uart_0.avalon_jtag_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c720" />
+  <parameter name="baseAddress" value="0x0010c760" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83056,7 +83061,7 @@
    start="cpu_0.data_master"
    end="pio_pps.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c6b0" />
+  <parameter name="baseAddress" value="0x0010c6f0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83096,7 +83101,7 @@
    start="cpu_0.data_master"
    end="reg_remu.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c640" />
+  <parameter name="baseAddress" value="0x0010c680" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83116,7 +83121,7 @@
    start="cpu_0.data_master"
    end="reg_epcs.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c620" />
+  <parameter name="baseAddress" value="0x0010c660" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83136,7 +83141,7 @@
    start="cpu_0.data_master"
    end="reg_dpmm_ctrl.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c718" />
+  <parameter name="baseAddress" value="0x0010c758" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83156,7 +83161,7 @@
    start="cpu_0.data_master"
    end="reg_dpmm_data.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c710" />
+  <parameter name="baseAddress" value="0x0010c750" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83176,7 +83181,7 @@
    start="cpu_0.data_master"
    end="reg_mmdp_ctrl.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c708" />
+  <parameter name="baseAddress" value="0x0010c748" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83196,7 +83201,7 @@
    start="cpu_0.data_master"
    end="reg_mmdp_data.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c700" />
+  <parameter name="baseAddress" value="0x0010c740" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83216,7 +83221,7 @@
    start="cpu_0.data_master"
    end="reg_fpga_temp_sens.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c600" />
+  <parameter name="baseAddress" value="0x0010c640" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83236,7 +83241,7 @@
    start="cpu_0.data_master"
    end="reg_fpga_voltage_sens.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c540" />
+  <parameter name="baseAddress" value="0x0010c580" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83276,7 +83281,7 @@
    start="cpu_0.data_master"
    end="reg_si.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c6f8" />
+  <parameter name="baseAddress" value="0x0010c738" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83376,7 +83381,7 @@
    start="cpu_0.data_master"
    end="reg_dp_shiftram.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3080" />
+  <parameter name="baseAddress" value="0x0010c400" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83396,7 +83401,7 @@
    start="cpu_0.data_master"
    end="reg_bsn_scheduler.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c6f0" />
+  <parameter name="baseAddress" value="0x0010c730" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83416,7 +83421,7 @@
    start="cpu_0.data_master"
    end="reg_bsn_source_v2.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c5e0" />
+  <parameter name="baseAddress" value="0x0010c620" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83496,7 +83501,7 @@
    start="cpu_0.data_master"
    end="reg_dp_selector.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c6e8" />
+  <parameter name="baseAddress" value="0x0010c728" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83576,7 +83581,7 @@
    start="cpu_0.data_master"
    end="reg_bf_scale.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c6a0" />
+  <parameter name="baseAddress" value="0x0010c6e0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83616,7 +83621,7 @@
    start="cpu_0.data_master"
    end="reg_dp_xonoff.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c690" />
+  <parameter name="baseAddress" value="0x0010c6d0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83656,7 +83661,7 @@
    start="cpu_0.data_master"
    end="reg_sdp_info.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c500" />
+  <parameter name="baseAddress" value="0x0010c540" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83676,7 +83681,7 @@
    start="cpu_0.data_master"
    end="reg_nw_10gbe_eth10g.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c6e0" />
+  <parameter name="baseAddress" value="0x0010c720" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83716,7 +83721,7 @@
    start="cpu_0.data_master"
    end="reg_diag_data_buffer_bsn.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0080" />
+  <parameter name="baseAddress" value="0x3080" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83756,7 +83761,7 @@
    start="cpu_0.data_master"
    end="pio_jesd_ctrl.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c6d8" />
+  <parameter name="baseAddress" value="0x0010c718" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83776,7 +83781,7 @@
    start="cpu_0.data_master"
    end="reg_stat_enable_sst.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c6d0" />
+  <parameter name="baseAddress" value="0x0010c710" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83816,7 +83821,7 @@
    start="cpu_0.data_master"
    end="reg_stat_enable_bst.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c680" />
+  <parameter name="baseAddress" value="0x0010c6c0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83856,7 +83861,7 @@
    start="cpu_0.data_master"
    end="reg_crosslets_info.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c4c0" />
+  <parameter name="baseAddress" value="0x0010c500" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83896,7 +83901,7 @@
    start="cpu_0.data_master"
    end="reg_stat_enable_xst.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c6c8" />
+  <parameter name="baseAddress" value="0x0010c708" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83936,7 +83941,7 @@
    start="cpu_0.data_master"
    end="reg_bsn_sync_scheduler_xsub.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c480" />
+  <parameter name="baseAddress" value="0x0010c4c0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83976,7 +83981,7 @@
    start="cpu_0.data_master"
    end="reg_nof_crosslets.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c6c0" />
+  <parameter name="baseAddress" value="0x0010c700" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83994,9 +83999,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="reg_bsn_align.mem">
+   end="reg_bsn_align_v2.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c440" />
+  <parameter name="baseAddress" value="0x0080" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84014,9 +84019,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="reg_bsn_monitor_v2_bsn_align_output.mem">
+   end="reg_bsn_monitor_v2_bsn_align_v2_output.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c5c0" />
+  <parameter name="baseAddress" value="0x0010c600" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84034,9 +84039,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="reg_xst_udp_monitor.mem">
+   end="reg_bsn_monitor_v2_xst_offload.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c5a0" />
+  <parameter name="baseAddress" value="0x0010c5e0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84116,7 +84121,7 @@
    start="cpu_0.data_master"
    end="reg_dp_block_validate_err_xst.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c400" />
+  <parameter name="baseAddress" value="0x0010c480" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84136,7 +84141,7 @@
    start="cpu_0.data_master"
    end="reg_dp_block_validate_bsn_at_sync_xst.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c670" />
+  <parameter name="baseAddress" value="0x0010c6b0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84156,7 +84161,7 @@
    start="cpu_0.data_master"
    end="reg_ring_info.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c660" />
+  <parameter name="baseAddress" value="0x0010c6a0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84176,7 +84181,7 @@
    start="cpu_0.data_master"
    end="reg_tr_10gbe_eth10g.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0010c580" />
+  <parameter name="baseAddress" value="0x0010c5c0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84214,7 +84219,7 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="reg_bsn_monitor_v2_bsn_align_input.mem">
+   end="reg_bsn_monitor_v2_bsn_align_v2_input.mem">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0200" />
   <parameter name="defaultConnection" value="false" />
@@ -84601,17 +84606,17 @@
    kind="clock"
    version="19.4"
    start="clk_0.clk"
-   end="reg_bsn_align.system" />
+   end="reg_bsn_align_v2.system" />
  <connection
    kind="clock"
    version="19.4"
    start="clk_0.clk"
-   end="reg_bsn_monitor_v2_bsn_align_output.system" />
+   end="reg_bsn_monitor_v2_bsn_align_v2_output.system" />
  <connection
    kind="clock"
    version="19.4"
    start="clk_0.clk"
-   end="reg_xst_udp_monitor.system" />
+   end="reg_bsn_monitor_v2_xst_offload.system" />
  <connection
    kind="clock"
    version="19.4"
@@ -84656,7 +84661,7 @@
    kind="clock"
    version="19.4"
    start="clk_0.clk"
-   end="reg_bsn_monitor_v2_bsn_align_input.system" />
+   end="reg_bsn_monitor_v2_bsn_align_v2_input.system" />
  <connection
    kind="interrupt"
    version="19.4"
@@ -84949,17 +84954,17 @@
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="reg_bsn_align.system_reset" />
+   end="reg_bsn_align_v2.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="reg_bsn_monitor_v2_bsn_align_output.system_reset" />
+   end="reg_bsn_monitor_v2_bsn_align_v2_output.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="reg_xst_udp_monitor.system_reset" />
+   end="reg_bsn_monitor_v2_xst_offload.system_reset" />
  <connection
    kind="reset"
    version="19.4"
@@ -85004,7 +85009,7 @@
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="reg_bsn_monitor_v2_bsn_align_input.system_reset" />
+   end="reg_bsn_monitor_v2_bsn_align_v2_input.system_reset" />
  <connection
    kind="reset"
    version="19.4"
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
index c7155b30c3..0e2e17e2c7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
@@ -65,12 +65,13 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
@@ -107,7 +108,6 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
index 83a37e5186..2dbc42a190 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
@@ -73,12 +73,13 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
@@ -115,7 +116,6 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
index 0870c853d9..484e94af1f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
@@ -72,12 +72,13 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
@@ -114,7 +115,6 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
index 303b2ff966..9d83b60200 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
@@ -69,12 +69,13 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
@@ -111,7 +112,6 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
index fa2e4069a3..f6fa5a6eac 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
@@ -72,12 +72,13 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
@@ -114,7 +115,6 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
index c0ad06a755..450d250eb3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
@@ -69,12 +69,13 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_input.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_output.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
@@ -111,7 +112,6 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
-    $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_xst_udp_monitor.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index d2e63d498c..45baadee02 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -346,18 +346,18 @@ ARCHITECTURE str OF lofar2_unb2c_sdp_station IS
   SIGNAL reg_stat_hdr_dat_xst_miso      : t_mem_miso;
 
   -- XST bsn aligner_v2
-  SIGNAL  reg_bsn_align_copi                          : t_mem_mosi;
-  SIGNAL  reg_bsn_align_cipo                          : t_mem_miso;
+  SIGNAL  reg_bsn_align_v2_copi                       : t_mem_mosi;
+  SIGNAL  reg_bsn_align_v2_cipo                       : t_mem_miso;
    
   -- XST bsn aligner_v2 bsn monitors
-  SIGNAL  reg_bsn_monitor_v2_bsn_align_input_copi                      : t_mem_mosi;
-  SIGNAL  reg_bsn_monitor_v2_bsn_align_input_cipo                      : t_mem_miso;
-  SIGNAL  reg_bsn_monitor_v2_bsn_align_output_copi                     : t_mem_mosi;
-  SIGNAL  reg_bsn_monitor_v2_bsn_align_output_cipo                     : t_mem_miso;
+  SIGNAL  reg_bsn_monitor_v2_bsn_align_v2_input_copi  : t_mem_mosi;
+  SIGNAL  reg_bsn_monitor_v2_bsn_align_v2_input_cipo  : t_mem_miso;
+  SIGNAL  reg_bsn_monitor_v2_bsn_align_v2_output_copi : t_mem_mosi;
+  SIGNAL  reg_bsn_monitor_v2_bsn_align_v2_output_cipo : t_mem_miso;
 
   -- XST UDP offload bsn monitor
-  SIGNAL  reg_xst_udp_monitor_copi                    : t_mem_mosi;
-  SIGNAL  reg_xst_udp_monitor_cipo                    : t_mem_miso;
+  SIGNAL  reg_bsn_monitor_v2_xst_offload_copi         : t_mem_mosi;
+  SIGNAL  reg_bsn_monitor_v2_xst_offload_cipo         : t_mem_miso;
 
   -- XST ring lane info
   SIGNAL  reg_ring_lane_info_xst_copi                 : t_mem_mosi;
@@ -605,104 +605,104 @@ BEGIN
 
     -- mm buses for signal flow blocks
     -- Jesd ip status/control
-    jesd204b_mosi                              => jesd204b_mosi,
-    jesd204b_miso                              => jesd204b_miso,
-    jesd_ctrl_mosi                             => jesd_ctrl_mosi,
-    jesd_ctrl_miso                             => jesd_ctrl_miso,
-    reg_dp_shiftram_mosi                       => reg_dp_shiftram_mosi,
-    reg_dp_shiftram_miso                       => reg_dp_shiftram_miso,
-    reg_bsn_source_v2_mosi                     => reg_bsn_source_v2_mosi,
-    reg_bsn_source_v2_miso                     => reg_bsn_source_v2_miso,
-    reg_bsn_scheduler_mosi                     => reg_bsn_scheduler_wg_mosi,
-    reg_bsn_scheduler_miso                     => reg_bsn_scheduler_wg_miso,
-    reg_wg_mosi                                => reg_wg_mosi,
-    reg_wg_miso                                => reg_wg_miso,
-    ram_wg_mosi                                => ram_wg_mosi,
-    ram_wg_miso                                => ram_wg_miso,
-    reg_bsn_monitor_input_mosi                 => reg_bsn_monitor_input_mosi,
-    reg_bsn_monitor_input_miso                 => reg_bsn_monitor_input_miso,
-    ram_diag_data_buf_bsn_mosi                 => ram_diag_data_buf_bsn_mosi,
-    ram_diag_data_buf_bsn_miso                 => ram_diag_data_buf_bsn_miso,
-    reg_diag_data_buf_bsn_mosi                 => reg_diag_data_buf_bsn_mosi,
-    reg_diag_data_buf_bsn_miso                 => reg_diag_data_buf_bsn_miso,
-    ram_st_histogram_mosi                      => ram_st_histogram_mosi,
-    ram_st_histogram_miso                      => ram_st_histogram_miso,
-    reg_aduh_monitor_mosi                      => reg_aduh_monitor_mosi,
-    reg_aduh_monitor_miso                      => reg_aduh_monitor_miso,
-    ram_st_sst_mosi                            => ram_st_sst_mosi,   
-    ram_st_sst_miso                            => ram_st_sst_miso,   
-    ram_fil_coefs_mosi                         => ram_fil_coefs_mosi,   
-    ram_fil_coefs_miso                         => ram_fil_coefs_miso,   
-    reg_si_mosi                                => reg_si_mosi,   
-    reg_si_miso                                => reg_si_miso,
-    ram_equalizer_gains_mosi                   => ram_equalizer_gains_mosi,   
-    ram_equalizer_gains_miso                   => ram_equalizer_gains_miso,   
-    reg_dp_selector_mosi                       => reg_dp_selector_mosi,   
-    reg_dp_selector_miso                       => reg_dp_selector_miso,
-    reg_sdp_info_mosi                          => reg_sdp_info_mosi,          
-    reg_sdp_info_miso                          => reg_sdp_info_miso, 
-    reg_ring_info_copi                         => reg_ring_info_copi,
-    reg_ring_info_cipo                         => reg_ring_info_cipo,          
-    ram_ss_ss_wide_mosi                        => ram_ss_ss_wide_mosi,        
-    ram_ss_ss_wide_miso                        => ram_ss_ss_wide_miso,        
-    ram_bf_weights_mosi                        => ram_bf_weights_mosi,        
-    ram_bf_weights_miso                        => ram_bf_weights_miso,        
-    reg_bf_scale_mosi                          => reg_bf_scale_mosi,          
-    reg_bf_scale_miso                          => reg_bf_scale_miso,          
-    reg_hdr_dat_mosi                           => reg_hdr_dat_mosi,           
-    reg_hdr_dat_miso                           => reg_hdr_dat_miso,           
-    reg_dp_xonoff_mosi                         => reg_dp_xonoff_mosi,         
-    reg_dp_xonoff_miso                         => reg_dp_xonoff_miso,         
-    ram_st_bst_mosi                            => ram_st_bst_mosi,            
-    ram_st_bst_miso                            => ram_st_bst_miso,            
-    reg_nw_10GbE_mac_mosi                      => reg_nw_10GbE_mac_mosi,      
-    reg_nw_10GbE_mac_miso                      => reg_nw_10GbE_mac_miso,      
-    reg_nw_10GbE_eth10g_mosi                   => reg_nw_10GbE_eth10g_mosi,   
-    reg_nw_10GbE_eth10g_miso                   => reg_nw_10GbE_eth10g_miso,   
-    ram_scrap_mosi                             => ram_scrap_mosi,
-    ram_scrap_miso                             => ram_scrap_miso,
-    reg_stat_enable_sst_mosi                   => reg_stat_enable_sst_mosi,
-    reg_stat_enable_sst_miso                   => reg_stat_enable_sst_miso,
-    reg_stat_hdr_dat_sst_mosi                  => reg_stat_hdr_dat_sst_mosi,
-    reg_stat_hdr_dat_sst_miso                  => reg_stat_hdr_dat_sst_miso,
-    reg_stat_enable_xst_mosi                   => reg_stat_enable_xst_mosi,
-    reg_stat_enable_xst_miso                   => reg_stat_enable_xst_miso,
-    reg_stat_hdr_dat_xst_mosi                  => reg_stat_hdr_dat_xst_mosi,
-    reg_stat_hdr_dat_xst_miso                  => reg_stat_hdr_dat_xst_miso,
-    reg_stat_enable_bst_mosi                   => reg_stat_enable_bst_mosi,
-    reg_stat_enable_bst_miso                   => reg_stat_enable_bst_miso,
-    reg_stat_hdr_dat_bst_mosi                  => reg_stat_hdr_dat_bst_mosi,
-    reg_stat_hdr_dat_bst_miso                  => reg_stat_hdr_dat_bst_miso,
-    reg_crosslets_info_mosi                    => reg_crosslets_info_mosi, 
-    reg_crosslets_info_miso                    => reg_crosslets_info_miso,
-    reg_nof_crosslets_mosi                     => reg_nof_crosslets_mosi, 
-    reg_nof_crosslets_miso                     => reg_nof_crosslets_miso, 
-    reg_bsn_sync_scheduler_xsub_mosi           => reg_bsn_sync_scheduler_xsub_mosi, 
-    reg_bsn_sync_scheduler_xsub_miso           => reg_bsn_sync_scheduler_xsub_miso,
-    reg_bsn_align_copi                         => reg_bsn_align_copi, 
-    reg_bsn_align_cipo                         => reg_bsn_align_cipo, 
-    reg_bsn_monitor_v2_bsn_align_input_copi    => reg_bsn_monitor_v2_bsn_align_input_copi, 
-    reg_bsn_monitor_v2_bsn_align_input_cipo    => reg_bsn_monitor_v2_bsn_align_input_cipo, 
-    reg_bsn_monitor_v2_bsn_align_output_copi   => reg_bsn_monitor_v2_bsn_align_output_copi, 
-    reg_bsn_monitor_v2_bsn_align_output_cipo   => reg_bsn_monitor_v2_bsn_align_output_cipo, 
-    reg_xst_udp_monitor_copi                   => reg_xst_udp_monitor_copi, 
-    reg_xst_udp_monitor_cipo                   => reg_xst_udp_monitor_cipo, 
-    reg_ring_lane_info_xst_copi                => reg_ring_lane_info_xst_copi, 
-    reg_ring_lane_info_xst_cipo                => reg_ring_lane_info_xst_cipo, 
-    reg_bsn_monitor_v2_ring_rx_xst_copi        => reg_bsn_monitor_v2_ring_rx_xst_copi, 
-    reg_bsn_monitor_v2_ring_rx_xst_cipo        => reg_bsn_monitor_v2_ring_rx_xst_cipo, 
-    reg_bsn_monitor_v2_ring_tx_xst_copi        => reg_bsn_monitor_v2_ring_tx_xst_copi, 
-    reg_bsn_monitor_v2_ring_tx_xst_cipo        => reg_bsn_monitor_v2_ring_tx_xst_cipo, 
-    reg_dp_block_validate_err_xst_copi         => reg_dp_block_validate_err_xst_copi, 
-    reg_dp_block_validate_err_xst_cipo         => reg_dp_block_validate_err_xst_cipo, 
-    reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi, 
-    reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo, 
-    reg_tr_10GbE_mac_copi                      => reg_tr_10GbE_mac_copi, 
-    reg_tr_10GbE_mac_cipo                      => reg_tr_10GbE_mac_cipo, 
-    reg_tr_10GbE_eth10g_copi                   => reg_tr_10GbE_eth10g_copi, 
-    reg_tr_10GbE_eth10g_cipo                   => reg_tr_10GbE_eth10g_cipo, 
-    ram_st_xsq_mosi                            => ram_st_xsq_mosi, 
-    ram_st_xsq_miso                            => ram_st_xsq_miso 
+    jesd204b_mosi                                => jesd204b_mosi,
+    jesd204b_miso                                => jesd204b_miso,
+    jesd_ctrl_mosi                               => jesd_ctrl_mosi,
+    jesd_ctrl_miso                               => jesd_ctrl_miso,
+    reg_dp_shiftram_mosi                         => reg_dp_shiftram_mosi,
+    reg_dp_shiftram_miso                         => reg_dp_shiftram_miso,
+    reg_bsn_source_v2_mosi                       => reg_bsn_source_v2_mosi,
+    reg_bsn_source_v2_miso                       => reg_bsn_source_v2_miso,
+    reg_bsn_scheduler_mosi                       => reg_bsn_scheduler_wg_mosi,
+    reg_bsn_scheduler_miso                       => reg_bsn_scheduler_wg_miso,
+    reg_wg_mosi                                  => reg_wg_mosi,
+    reg_wg_miso                                  => reg_wg_miso,
+    ram_wg_mosi                                  => ram_wg_mosi,
+    ram_wg_miso                                  => ram_wg_miso,
+    reg_bsn_monitor_input_mosi                   => reg_bsn_monitor_input_mosi,
+    reg_bsn_monitor_input_miso                   => reg_bsn_monitor_input_miso,
+    ram_diag_data_buf_bsn_mosi                   => ram_diag_data_buf_bsn_mosi,
+    ram_diag_data_buf_bsn_miso                   => ram_diag_data_buf_bsn_miso,
+    reg_diag_data_buf_bsn_mosi                   => reg_diag_data_buf_bsn_mosi,
+    reg_diag_data_buf_bsn_miso                   => reg_diag_data_buf_bsn_miso,
+    ram_st_histogram_mosi                        => ram_st_histogram_mosi,
+    ram_st_histogram_miso                        => ram_st_histogram_miso,
+    reg_aduh_monitor_mosi                        => reg_aduh_monitor_mosi,
+    reg_aduh_monitor_miso                        => reg_aduh_monitor_miso,
+    ram_st_sst_mosi                              => ram_st_sst_mosi,   
+    ram_st_sst_miso                              => ram_st_sst_miso,   
+    ram_fil_coefs_mosi                           => ram_fil_coefs_mosi,   
+    ram_fil_coefs_miso                           => ram_fil_coefs_miso,   
+    reg_si_mosi                                  => reg_si_mosi,   
+    reg_si_miso                                  => reg_si_miso,
+    ram_equalizer_gains_mosi                     => ram_equalizer_gains_mosi,   
+    ram_equalizer_gains_miso                     => ram_equalizer_gains_miso,   
+    reg_dp_selector_mosi                         => reg_dp_selector_mosi,   
+    reg_dp_selector_miso                         => reg_dp_selector_miso,
+    reg_sdp_info_mosi                            => reg_sdp_info_mosi,          
+    reg_sdp_info_miso                            => reg_sdp_info_miso, 
+    reg_ring_info_copi                           => reg_ring_info_copi,
+    reg_ring_info_cipo                           => reg_ring_info_cipo,          
+    ram_ss_ss_wide_mosi                          => ram_ss_ss_wide_mosi,        
+    ram_ss_ss_wide_miso                          => ram_ss_ss_wide_miso,        
+    ram_bf_weights_mosi                          => ram_bf_weights_mosi,        
+    ram_bf_weights_miso                          => ram_bf_weights_miso,        
+    reg_bf_scale_mosi                            => reg_bf_scale_mosi,          
+    reg_bf_scale_miso                            => reg_bf_scale_miso,          
+    reg_hdr_dat_mosi                             => reg_hdr_dat_mosi,           
+    reg_hdr_dat_miso                             => reg_hdr_dat_miso,           
+    reg_dp_xonoff_mosi                           => reg_dp_xonoff_mosi,         
+    reg_dp_xonoff_miso                           => reg_dp_xonoff_miso,         
+    ram_st_bst_mosi                              => ram_st_bst_mosi,            
+    ram_st_bst_miso                              => ram_st_bst_miso,            
+    reg_nw_10GbE_mac_mosi                        => reg_nw_10GbE_mac_mosi,      
+    reg_nw_10GbE_mac_miso                        => reg_nw_10GbE_mac_miso,      
+    reg_nw_10GbE_eth10g_mosi                     => reg_nw_10GbE_eth10g_mosi,   
+    reg_nw_10GbE_eth10g_miso                     => reg_nw_10GbE_eth10g_miso,   
+    ram_scrap_mosi                               => ram_scrap_mosi,
+    ram_scrap_miso                               => ram_scrap_miso,
+    reg_stat_enable_sst_mosi                     => reg_stat_enable_sst_mosi,
+    reg_stat_enable_sst_miso                     => reg_stat_enable_sst_miso,
+    reg_stat_hdr_dat_sst_mosi                    => reg_stat_hdr_dat_sst_mosi,
+    reg_stat_hdr_dat_sst_miso                    => reg_stat_hdr_dat_sst_miso,
+    reg_stat_enable_xst_mosi                     => reg_stat_enable_xst_mosi,
+    reg_stat_enable_xst_miso                     => reg_stat_enable_xst_miso,
+    reg_stat_hdr_dat_xst_mosi                    => reg_stat_hdr_dat_xst_mosi,
+    reg_stat_hdr_dat_xst_miso                    => reg_stat_hdr_dat_xst_miso,
+    reg_stat_enable_bst_mosi                     => reg_stat_enable_bst_mosi,
+    reg_stat_enable_bst_miso                     => reg_stat_enable_bst_miso,
+    reg_stat_hdr_dat_bst_mosi                    => reg_stat_hdr_dat_bst_mosi,
+    reg_stat_hdr_dat_bst_miso                    => reg_stat_hdr_dat_bst_miso,
+    reg_crosslets_info_mosi                      => reg_crosslets_info_mosi, 
+    reg_crosslets_info_miso                      => reg_crosslets_info_miso,
+    reg_nof_crosslets_mosi                       => reg_nof_crosslets_mosi, 
+    reg_nof_crosslets_miso                       => reg_nof_crosslets_miso, 
+    reg_bsn_sync_scheduler_xsub_mosi             => reg_bsn_sync_scheduler_xsub_mosi, 
+    reg_bsn_sync_scheduler_xsub_miso             => reg_bsn_sync_scheduler_xsub_miso,
+    reg_bsn_align_v2_copi                        => reg_bsn_align_v2_copi, 
+    reg_bsn_align_v2_cipo                        => reg_bsn_align_v2_cipo, 
+    reg_bsn_monitor_v2_bsn_align_v2_input_copi   => reg_bsn_monitor_v2_bsn_align_v2_input_copi, 
+    reg_bsn_monitor_v2_bsn_align_v2_input_cipo   => reg_bsn_monitor_v2_bsn_align_v2_input_cipo, 
+    reg_bsn_monitor_v2_bsn_align_v2_output_copi  => reg_bsn_monitor_v2_bsn_align_v2_output_copi, 
+    reg_bsn_monitor_v2_bsn_align_v2_output_cipo  => reg_bsn_monitor_v2_bsn_align_v2_output_cipo, 
+    reg_bsn_monitor_v2_xst_offload_copi          => reg_bsn_monitor_v2_xst_offload_copi, 
+    reg_bsn_monitor_v2_xst_offload_cipo          => reg_bsn_monitor_v2_xst_offload_cipo, 
+    reg_ring_lane_info_xst_copi                  => reg_ring_lane_info_xst_copi, 
+    reg_ring_lane_info_xst_cipo                  => reg_ring_lane_info_xst_cipo, 
+    reg_bsn_monitor_v2_ring_rx_xst_copi          => reg_bsn_monitor_v2_ring_rx_xst_copi, 
+    reg_bsn_monitor_v2_ring_rx_xst_cipo          => reg_bsn_monitor_v2_ring_rx_xst_cipo, 
+    reg_bsn_monitor_v2_ring_tx_xst_copi          => reg_bsn_monitor_v2_ring_tx_xst_copi, 
+    reg_bsn_monitor_v2_ring_tx_xst_cipo          => reg_bsn_monitor_v2_ring_tx_xst_cipo, 
+    reg_dp_block_validate_err_xst_copi           => reg_dp_block_validate_err_xst_copi, 
+    reg_dp_block_validate_err_xst_cipo           => reg_dp_block_validate_err_xst_cipo, 
+    reg_dp_block_validate_bsn_at_sync_xst_copi   => reg_dp_block_validate_bsn_at_sync_xst_copi, 
+    reg_dp_block_validate_bsn_at_sync_xst_cipo   => reg_dp_block_validate_bsn_at_sync_xst_cipo, 
+    reg_tr_10GbE_mac_copi                        => reg_tr_10GbE_mac_copi, 
+    reg_tr_10GbE_mac_cipo                        => reg_tr_10GbE_mac_cipo, 
+    reg_tr_10GbE_eth10g_copi                     => reg_tr_10GbE_eth10g_copi, 
+    reg_tr_10GbE_eth10g_cipo                     => reg_tr_10GbE_eth10g_cipo, 
+    ram_st_xsq_mosi                              => ram_st_xsq_mosi, 
+    ram_st_xsq_miso                              => ram_st_xsq_miso 
   );
 
 
@@ -836,14 +836,14 @@ BEGIN
     reg_stat_hdr_dat_xst_mosi   => reg_stat_hdr_dat_xst_mosi, 
     reg_stat_hdr_dat_xst_miso   => reg_stat_hdr_dat_xst_miso, 
       
-    reg_bsn_align_copi                         => reg_bsn_align_copi, 
-    reg_bsn_align_cipo                         => reg_bsn_align_cipo, 
-    reg_bsn_monitor_v2_bsn_align_input_copi    => reg_bsn_monitor_v2_bsn_align_input_copi, 
-    reg_bsn_monitor_v2_bsn_align_input_cipo    => reg_bsn_monitor_v2_bsn_align_input_cipo, 
-    reg_bsn_monitor_v2_bsn_align_output_copi   => reg_bsn_monitor_v2_bsn_align_output_copi, 
-    reg_bsn_monitor_v2_bsn_align_output_cipo   => reg_bsn_monitor_v2_bsn_align_output_cipo, 
-    reg_xst_udp_monitor_copi                   => reg_xst_udp_monitor_copi, 
-    reg_xst_udp_monitor_cipo                   => reg_xst_udp_monitor_cipo, 
+    reg_bsn_align_copi                         => reg_bsn_align_v2_copi, 
+    reg_bsn_align_cipo                         => reg_bsn_align_v2_cipo, 
+    reg_bsn_monitor_v2_bsn_align_input_copi    => reg_bsn_monitor_v2_bsn_align_v2_input_copi, 
+    reg_bsn_monitor_v2_bsn_align_input_cipo    => reg_bsn_monitor_v2_bsn_align_v2_input_cipo, 
+    reg_bsn_monitor_v2_bsn_align_output_copi   => reg_bsn_monitor_v2_bsn_align_v2_output_copi, 
+    reg_bsn_monitor_v2_bsn_align_output_cipo   => reg_bsn_monitor_v2_bsn_align_v2_output_cipo, 
+    reg_xst_udp_monitor_copi                   => reg_bsn_monitor_v2_xst_offload_copi, 
+    reg_xst_udp_monitor_cipo                   => reg_bsn_monitor_v2_xst_offload_cipo, 
     reg_ring_lane_info_xst_copi                => reg_ring_lane_info_xst_copi, 
     reg_ring_lane_info_xst_cipo                => reg_ring_lane_info_xst_cipo, 
     reg_bsn_monitor_v2_ring_rx_xst_copi        => reg_bsn_monitor_v2_ring_rx_xst_copi, 
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index 9aa2848102..891f1d9e14 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -233,18 +233,18 @@ ENTITY mmm_lofar2_unb2c_sdp_station IS
    reg_nw_10GbE_eth10g_miso       : IN  t_mem_miso;
 
    -- XST bsn aligner_v2
-   reg_bsn_align_copi             : OUT t_mem_mosi;             
-   reg_bsn_align_cipo             : IN  t_mem_miso;             
+   reg_bsn_align_v2_copi          : OUT t_mem_mosi;             
+   reg_bsn_align_v2_cipo          : IN  t_mem_miso;             
    
    -- XST bsn aligner_v2 bsn monitors
-   reg_bsn_monitor_v2_bsn_align_input_copi         : OUT t_mem_mosi;             
-   reg_bsn_monitor_v2_bsn_align_input_cipo         : IN  t_mem_miso;             
-   reg_bsn_monitor_v2_bsn_align_output_copi        : OUT t_mem_mosi;             
-   reg_bsn_monitor_v2_bsn_align_output_cipo        : IN  t_mem_miso;             
+   reg_bsn_monitor_v2_bsn_align_v2_input_copi  : OUT t_mem_mosi;             
+   reg_bsn_monitor_v2_bsn_align_v2_input_cipo  : IN  t_mem_miso;             
+   reg_bsn_monitor_v2_bsn_align_v2_output_copi : OUT t_mem_mosi;             
+   reg_bsn_monitor_v2_bsn_align_v2_output_cipo : IN  t_mem_miso;             
 
    -- XST UDP offload bsn monitor
-   reg_xst_udp_monitor_copi       : OUT t_mem_mosi;             
-   reg_xst_udp_monitor_cipo       : IN  t_mem_miso;             
+   reg_bsn_monitor_v2_xst_offload_copi       : OUT t_mem_mosi;             
+   reg_bsn_monitor_v2_xst_offload_cipo       : IN  t_mem_miso;             
 
    -- XST ring lane info
    reg_ring_lane_info_xst_copi    : OUT t_mem_mosi;             
@@ -427,17 +427,17 @@ BEGIN
     u_mm_file_reg_nw_10GbE_eth10g     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
                                                PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
 
-    u_mm_file_reg_bsn_align           : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN")
-                                                PORT MAP(mm_rst, mm_clk, reg_bsn_align_copi, reg_bsn_align_cipo );
+    u_mm_file_reg_bsn_align_v2         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2")
+                                                PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_copi, reg_bsn_align_v2_cipo );
 
-    u_mm_file_reg_bsn_monitor_v2_bsn_align_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT")
-                                                           PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_input_copi, reg_bsn_monitor_v2_bsn_align_input_cipo );
+    u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT")
+                                                           PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_input_copi, reg_bsn_monitor_v2_bsn_align_v2_input_cipo );
 
-    u_mm_file_reg_bsn_monitor_v2_bsn_align_output: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT")
-                                                           PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_output_copi, reg_bsn_monitor_v2_bsn_align_output_cipo );
+    u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_output: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT")
+                                                           PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_output_copi, reg_bsn_monitor_v2_bsn_align_v2_output_cipo );
 
-    u_mm_file_reg_xst_udp_monitor     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_XST_UDP_MONITOR")
-                                                PORT MAP(mm_rst, mm_clk, reg_xst_udp_monitor_copi, reg_xst_udp_monitor_cipo );
+    u_mm_file_reg_bsn_monitor_v2_xst_offload     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
+                                                PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
 
     u_mm_file_reg_ring_lane_info_xst  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
                                                 PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
@@ -899,37 +899,37 @@ BEGIN
       reg_nw_10GbE_eth10g_read_export           => reg_nw_10GbE_eth10g_mosi.rd,
       reg_nw_10GbE_eth10g_readdata_export       => reg_nw_10GbE_eth10g_miso.rddata(c_word_w-1 DOWNTO 0),
 
-      reg_bsn_align_clk_export                  => OPEN,
-      reg_bsn_align_reset_export                => OPEN,
-      reg_bsn_align_address_export              => reg_bsn_align_copi.address(c_sdp_reg_bsn_align_addr_w-1 DOWNTO 0),
-      reg_bsn_align_write_export                => reg_bsn_align_copi.wr,
-      reg_bsn_align_writedata_export            => reg_bsn_align_copi.wrdata(c_word_w-1 DOWNTO 0), 
-      reg_bsn_align_read_export                 => reg_bsn_align_copi.rd,
-      reg_bsn_align_readdata_export             => reg_bsn_align_cipo.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_bsn_monitor_v2_bsn_align_input_clk_export       => OPEN,
-      reg_bsn_monitor_v2_bsn_align_input_reset_export     => OPEN,
-      reg_bsn_monitor_v2_bsn_align_input_address_export   => reg_bsn_monitor_v2_bsn_align_input_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_input_addr_w-1 DOWNTO 0),
-      reg_bsn_monitor_v2_bsn_align_input_write_export     => reg_bsn_monitor_v2_bsn_align_input_copi.wr,
-      reg_bsn_monitor_v2_bsn_align_input_writedata_export => reg_bsn_monitor_v2_bsn_align_input_copi.wrdata(c_word_w-1 DOWNTO 0), 
-      reg_bsn_monitor_v2_bsn_align_input_read_export      => reg_bsn_monitor_v2_bsn_align_input_copi.rd,
-      reg_bsn_monitor_v2_bsn_align_input_readdata_export  => reg_bsn_monitor_v2_bsn_align_input_cipo.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_bsn_monitor_v2_bsn_align_output_clk_export      => OPEN,
-      reg_bsn_monitor_v2_bsn_align_output_reset_export    => OPEN,
-      reg_bsn_monitor_v2_bsn_align_output_address_export  => reg_bsn_monitor_v2_bsn_align_output_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_output_addr_w-1 DOWNTO 0),
-      reg_bsn_monitor_v2_bsn_align_output_write_export    => reg_bsn_monitor_v2_bsn_align_output_copi.wr,
-      reg_bsn_monitor_v2_bsn_align_output_writedata_export=> reg_bsn_monitor_v2_bsn_align_output_copi.wrdata(c_word_w-1 DOWNTO 0), 
-      reg_bsn_monitor_v2_bsn_align_output_read_export     => reg_bsn_monitor_v2_bsn_align_output_copi.rd,
-      reg_bsn_monitor_v2_bsn_align_output_readdata_export => reg_bsn_monitor_v2_bsn_align_output_cipo.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_xst_udp_monitor_clk_export            => OPEN,
-      reg_xst_udp_monitor_reset_export          => OPEN,
-      reg_xst_udp_monitor_address_export        => reg_xst_udp_monitor_copi.address(c_sdp_reg_xst_udp_monitor_addr_w-1 DOWNTO 0),
-      reg_xst_udp_monitor_write_export          => reg_xst_udp_monitor_copi.wr,
-      reg_xst_udp_monitor_writedata_export      => reg_xst_udp_monitor_copi.wrdata(c_word_w-1 DOWNTO 0), 
-      reg_xst_udp_monitor_read_export           => reg_xst_udp_monitor_copi.rd,
-      reg_xst_udp_monitor_readdata_export       => reg_xst_udp_monitor_cipo.rddata(c_word_w-1 DOWNTO 0),
+      reg_bsn_align_v2_clk_export               => OPEN,
+      reg_bsn_align_v2_reset_export             => OPEN,
+      reg_bsn_align_v2_address_export           => reg_bsn_align_v2_copi.address(c_sdp_reg_bsn_align_v2_addr_w-1 DOWNTO 0),
+      reg_bsn_align_v2_write_export             => reg_bsn_align_v2_copi.wr,
+      reg_bsn_align_v2_writedata_export         => reg_bsn_align_v2_copi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_bsn_align_v2_read_export              => reg_bsn_align_v2_copi.rd,
+      reg_bsn_align_v2_readdata_export          => reg_bsn_align_v2_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_bsn_monitor_v2_bsn_align_v2_input_clk_export       => OPEN,
+      reg_bsn_monitor_v2_bsn_align_v2_input_reset_export     => OPEN,
+      reg_bsn_monitor_v2_bsn_align_v2_input_address_export   => reg_bsn_monitor_v2_bsn_align_v2_input_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_v2_input_addr_w-1 DOWNTO 0),
+      reg_bsn_monitor_v2_bsn_align_v2_input_write_export     => reg_bsn_monitor_v2_bsn_align_v2_input_copi.wr,
+      reg_bsn_monitor_v2_bsn_align_v2_input_writedata_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_bsn_monitor_v2_bsn_align_v2_input_read_export      => reg_bsn_monitor_v2_bsn_align_v2_input_copi.rd,
+      reg_bsn_monitor_v2_bsn_align_v2_input_readdata_export  => reg_bsn_monitor_v2_bsn_align_v2_input_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_bsn_monitor_v2_bsn_align_v2_output_clk_export      => OPEN,
+      reg_bsn_monitor_v2_bsn_align_v2_output_reset_export    => OPEN,
+      reg_bsn_monitor_v2_bsn_align_v2_output_address_export  => reg_bsn_monitor_v2_bsn_align_v2_output_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_v2_output_addr_w-1 DOWNTO 0),
+      reg_bsn_monitor_v2_bsn_align_v2_output_write_export    => reg_bsn_monitor_v2_bsn_align_v2_output_copi.wr,
+      reg_bsn_monitor_v2_bsn_align_v2_output_writedata_export=> reg_bsn_monitor_v2_bsn_align_v2_output_copi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_bsn_monitor_v2_bsn_align_v2_output_read_export     => reg_bsn_monitor_v2_bsn_align_v2_output_copi.rd,
+      reg_bsn_monitor_v2_bsn_align_v2_output_readdata_export => reg_bsn_monitor_v2_bsn_align_v2_output_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_bsn_monitor_v2_xst_offload_clk_export            => OPEN,
+      reg_bsn_monitor_v2_xst_offload_reset_export          => OPEN,
+      reg_bsn_monitor_v2_xst_offload_address_export        => reg_bsn_monitor_v2_xst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w-1 DOWNTO 0),
+      reg_bsn_monitor_v2_xst_offload_write_export          => reg_bsn_monitor_v2_xst_offload_copi.wr,
+      reg_bsn_monitor_v2_xst_offload_writedata_export      => reg_bsn_monitor_v2_xst_offload_copi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_bsn_monitor_v2_xst_offload_read_export           => reg_bsn_monitor_v2_xst_offload_copi.rd,
+      reg_bsn_monitor_v2_xst_offload_readdata_export       => reg_bsn_monitor_v2_xst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
 
       reg_ring_lane_info_xst_clk_export         => OPEN,
       reg_ring_lane_info_xst_reset_export       => OPEN,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index e98fce91c7..ccfb20e569 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -28,455 +28,455 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
   -----------------------------------------------------------------------------
     component qsys_lofar2_unb2c_sdp_station is
         port (
-            avs_eth_0_clk_export                                   : out std_logic;                                        -- export
-            avs_eth_0_irq_export                                   : in  std_logic                     := 'X';             -- export
-            avs_eth_0_ram_address_export                           : out std_logic_vector(9 downto 0);                     -- export
-            avs_eth_0_ram_read_export                              : out std_logic;                                        -- export
-            avs_eth_0_ram_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            avs_eth_0_ram_write_export                             : out std_logic;                                        -- export
-            avs_eth_0_ram_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            avs_eth_0_reg_address_export                           : out std_logic_vector(3 downto 0);                     -- export
-            avs_eth_0_reg_read_export                              : out std_logic;                                        -- export
-            avs_eth_0_reg_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            avs_eth_0_reg_write_export                             : out std_logic;                                        -- export
-            avs_eth_0_reg_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            avs_eth_0_reset_export                                 : out std_logic;                                        -- export
-            avs_eth_0_tse_address_export                           : out std_logic_vector(9 downto 0);                     -- export
-            avs_eth_0_tse_read_export                              : out std_logic;                                        -- export
-            avs_eth_0_tse_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            avs_eth_0_tse_waitrequest_export                       : in  std_logic                     := 'X';             -- export
-            avs_eth_0_tse_write_export                             : out std_logic;                                        -- export
-            avs_eth_0_tse_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            clk_clk                                                : in  std_logic                     := 'X';             -- clk
-            reset_reset_n                                          : in  std_logic                     := 'X';             -- reset_n
-            jesd204b_address_export                                : out std_logic_vector(11 downto 0);                    -- export
-            jesd204b_clk_export                                    : out std_logic;                                        -- export
-            jesd204b_read_export                                   : out std_logic;                                        -- export
-            jesd204b_readdata_export                               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            jesd204b_reset_export                                  : out std_logic;                                        -- export
-            jesd204b_write_export                                  : out std_logic;                                        -- export
-            jesd204b_writedata_export                              : out std_logic_vector(31 downto 0);                    -- export
-            pio_jesd_ctrl_address_export                           : out std_logic_vector(0 downto 0);                     -- export
-            pio_jesd_ctrl_clk_export                               : out std_logic;                                        -- export
-            pio_jesd_ctrl_read_export                              : out std_logic;                                        -- export
-            pio_jesd_ctrl_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            pio_jesd_ctrl_reset_export                             : out std_logic;                                        -- export
-            pio_jesd_ctrl_write_export                             : out std_logic;                                        -- export
-            pio_jesd_ctrl_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            pio_pps_address_export                                 : out std_logic_vector(1 downto 0);                     -- export
-            pio_pps_clk_export                                     : out std_logic;                                        -- export
-            pio_pps_read_export                                    : out std_logic;                                        -- export
-            pio_pps_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            pio_pps_reset_export                                   : out std_logic;                                        -- export
-            pio_pps_write_export                                   : out std_logic;                                        -- export
-            pio_pps_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
-            pio_system_info_address_export                         : out std_logic_vector(4 downto 0);                     -- export
-            pio_system_info_clk_export                             : out std_logic;                                        -- export
-            pio_system_info_read_export                            : out std_logic;                                        -- export
-            pio_system_info_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            pio_system_info_reset_export                           : out std_logic;                                        -- export
-            pio_system_info_write_export                           : out std_logic;                                        -- export
-            pio_system_info_writedata_export                       : out std_logic_vector(31 downto 0);                    -- export
-            pio_wdi_external_connection_export                     : out std_logic;                                        -- export
-            ram_bf_weights_address_export                          : out std_logic_vector(14 downto 0);                    -- export
-            ram_bf_weights_clk_export                              : out std_logic;                                        -- export
-            ram_bf_weights_read_export                             : out std_logic;                                        -- export
-            ram_bf_weights_readdata_export                         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_bf_weights_reset_export                            : out std_logic;                                        -- export
-            ram_bf_weights_write_export                            : out std_logic;                                        -- export
-            ram_bf_weights_writedata_export                        : out std_logic_vector(31 downto 0);                    -- export
-            ram_diag_data_buffer_bsn_address_export                : out std_logic_vector(20 downto 0);                    -- export
-            ram_diag_data_buffer_bsn_clk_export                    : out std_logic;                                        -- export
-            ram_diag_data_buffer_bsn_read_export                   : out std_logic;                                        -- export
-            ram_diag_data_buffer_bsn_readdata_export               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_diag_data_buffer_bsn_reset_export                  : out std_logic;                                        -- export
-            ram_diag_data_buffer_bsn_write_export                  : out std_logic;                                        -- export
-            ram_diag_data_buffer_bsn_writedata_export              : out std_logic_vector(31 downto 0);                    -- export
-            ram_equalizer_gains_address_export                     : out std_logic_vector(12 downto 0);                    -- export
-            ram_equalizer_gains_clk_export                         : out std_logic;                                        -- export
-            ram_equalizer_gains_read_export                        : out std_logic;                                        -- export
-            ram_equalizer_gains_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_equalizer_gains_reset_export                       : out std_logic;                                        -- export
-            ram_equalizer_gains_write_export                       : out std_logic;                                        -- export
-            ram_equalizer_gains_writedata_export                   : out std_logic_vector(31 downto 0);                    -- export
-            ram_fil_coefs_address_export                           : out std_logic_vector(13 downto 0);                    -- export
-            ram_fil_coefs_clk_export                               : out std_logic;                                        -- export
-            ram_fil_coefs_read_export                              : out std_logic;                                        -- export
-            ram_fil_coefs_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_fil_coefs_reset_export                             : out std_logic;                                        -- export
-            ram_fil_coefs_write_export                             : out std_logic;                                        -- export
-            ram_fil_coefs_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            ram_scrap_address_export                               : out std_logic_vector(8 downto 0);                     -- export
-            ram_scrap_clk_export                                   : out std_logic;                                        -- export
-            ram_scrap_read_export                                  : out std_logic;                                        -- export
-            ram_scrap_readdata_export                              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_scrap_reset_export                                 : out std_logic;                                        -- export
-            ram_scrap_write_export                                 : out std_logic;                                        -- export
-            ram_scrap_writedata_export                             : out std_logic_vector(31 downto 0);                    -- export
-            ram_ss_ss_wide_address_export                          : out std_logic_vector(13 downto 0);                    -- export
-            ram_ss_ss_wide_clk_export                              : out std_logic;                                        -- export
-            ram_ss_ss_wide_read_export                             : out std_logic;                                        -- export
-            ram_ss_ss_wide_readdata_export                         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_ss_ss_wide_reset_export                            : out std_logic;                                        -- export
-            ram_ss_ss_wide_write_export                            : out std_logic;                                        -- export
-            ram_ss_ss_wide_writedata_export                        : out std_logic_vector(31 downto 0);                    -- export
-            ram_st_bst_address_export                              : out std_logic_vector(11 downto 0);                    -- export
-            ram_st_bst_clk_export                                  : out std_logic;                                        -- export
-            ram_st_bst_read_export                                 : out std_logic;                                        -- export
-            ram_st_bst_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_st_bst_reset_export                                : out std_logic;                                        -- export
-            ram_st_bst_write_export                                : out std_logic;                                        -- export
-            ram_st_bst_writedata_export                            : out std_logic_vector(31 downto 0);                    -- export
-            ram_st_histogram_reset_export                          : out std_logic;                                        -- export
-            ram_st_histogram_clk_export                            : out std_logic;                                        -- export
-            ram_st_histogram_address_export                        : out std_logic_vector(12 downto 0);                    -- export
-            ram_st_histogram_write_export                          : out std_logic;                                        -- export
-            ram_st_histogram_writedata_export                      : out std_logic_vector(31 downto 0);                    -- export
-            ram_st_histogram_read_export                           : out std_logic;                                        -- export
-            ram_st_histogram_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_st_sst_address_export                              : out std_logic_vector(13 downto 0);                    -- export
-            ram_st_sst_clk_export                                  : out std_logic;                                        -- export
-            ram_st_sst_read_export                                 : out std_logic;                                        -- export
-            ram_st_sst_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_st_sst_reset_export                                : out std_logic;                                        -- export
-            ram_st_sst_write_export                                : out std_logic;                                        -- export
-            ram_st_sst_writedata_export                            : out std_logic_vector(31 downto 0);                    -- export
-            ram_st_xsq_address_export                              : out std_logic_vector(15 downto 0);                    -- export
-            ram_st_xsq_clk_export                                  : out std_logic;                                        -- export
-            ram_st_xsq_read_export                                 : out std_logic;                                        -- export
-            ram_st_xsq_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_st_xsq_reset_export                                : out std_logic;                                        -- export
-            ram_st_xsq_write_export                                : out std_logic;                                        -- export
-            ram_st_xsq_writedata_export                            : out std_logic_vector(31 downto 0);                    -- export
-            ram_wg_address_export                                  : out std_logic_vector(13 downto 0);                    -- export
-            ram_wg_clk_export                                      : out std_logic;                                        -- export
-            ram_wg_read_export                                     : out std_logic;                                        -- export
-            ram_wg_readdata_export                                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_wg_reset_export                                    : out std_logic;                                        -- export
-            ram_wg_write_export                                    : out std_logic;                                        -- export
-            ram_wg_writedata_export                                : out std_logic_vector(31 downto 0);                    -- export
-            reg_aduh_monitor_address_export                        : out std_logic_vector(5 downto 0);                     -- export
-            reg_aduh_monitor_clk_export                            : out std_logic;                                        -- export
-            reg_aduh_monitor_read_export                           : out std_logic;                                        -- export
-            reg_aduh_monitor_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_aduh_monitor_reset_export                          : out std_logic;                                        -- export
-            reg_aduh_monitor_write_export                          : out std_logic;                                        -- export
-            reg_aduh_monitor_writedata_export                      : out std_logic_vector(31 downto 0);                    -- export
-            reg_bf_scale_address_export                            : out std_logic_vector(1 downto 0);                     -- export
-            reg_bf_scale_clk_export                                : out std_logic;                                        -- export
-            reg_bf_scale_read_export                               : out std_logic;                                        -- export
-            reg_bf_scale_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bf_scale_reset_export                              : out std_logic;                                        -- export
-            reg_bf_scale_write_export                              : out std_logic;                                        -- export
-            reg_bf_scale_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_align_reset_export                             : out std_logic;                                        -- export
-            reg_bsn_align_clk_export                               : out std_logic;                                        -- export
-            reg_bsn_align_address_export                           : out std_logic_vector(3 downto 0);                     -- export
-            reg_bsn_align_write_export                             : out std_logic;                                        -- export
-            reg_bsn_align_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_align_read_export                              : out std_logic;                                        -- export
-            reg_bsn_align_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bsn_monitor_input_address_export                   : out std_logic_vector(7 downto 0);                     -- export
-            reg_bsn_monitor_input_clk_export                       : out std_logic;                                        -- export
-            reg_bsn_monitor_input_read_export                      : out std_logic;                                        -- export
-            reg_bsn_monitor_input_readdata_export                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bsn_monitor_input_reset_export                     : out std_logic;                                        -- export
-            reg_bsn_monitor_input_write_export                     : out std_logic;                                        -- export
-            reg_bsn_monitor_input_writedata_export                 : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_monitor_v2_bsn_align_input_reset_export        : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_input_clk_export          : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_input_address_export      : out std_logic_vector(6 downto 0);                     -- export
-            reg_bsn_monitor_v2_bsn_align_input_write_export        : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_input_writedata_export    : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_monitor_v2_bsn_align_input_read_export         : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_input_readdata_export     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bsn_monitor_v2_bsn_align_output_reset_export       : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_output_clk_export         : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_output_address_export     : out std_logic_vector(2 downto 0);                     -- export
-            reg_bsn_monitor_v2_bsn_align_output_write_export       : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_output_writedata_export   : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_monitor_v2_bsn_align_output_read_export        : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_bsn_align_output_readdata_export    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bsn_monitor_v2_ring_rx_xst_reset_export            : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_ring_rx_xst_clk_export              : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_ring_rx_xst_address_export          : out std_logic_vector(6 downto 0);                     -- export
-            reg_bsn_monitor_v2_ring_rx_xst_write_export            : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_ring_rx_xst_writedata_export        : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_monitor_v2_ring_rx_xst_read_export             : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_ring_rx_xst_readdata_export         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bsn_monitor_v2_ring_tx_xst_reset_export            : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_ring_tx_xst_clk_export              : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_ring_tx_xst_address_export          : out std_logic_vector(6 downto 0);                     -- export
-            reg_bsn_monitor_v2_ring_tx_xst_write_export            : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_ring_tx_xst_writedata_export        : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_monitor_v2_ring_tx_xst_read_export             : out std_logic;                                        -- export
-            reg_bsn_monitor_v2_ring_tx_xst_readdata_export         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bsn_scheduler_address_export                       : out std_logic_vector(0 downto 0);                     -- export
-            reg_bsn_scheduler_clk_export                           : out std_logic;                                        -- export
-            reg_bsn_scheduler_read_export                          : out std_logic;                                        -- export
-            reg_bsn_scheduler_readdata_export                      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bsn_scheduler_reset_export                         : out std_logic;                                        -- export
-            reg_bsn_scheduler_write_export                         : out std_logic;                                        -- export
-            reg_bsn_scheduler_writedata_export                     : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_source_v2_address_export                       : out std_logic_vector(2 downto 0);                     -- export
-            reg_bsn_source_v2_clk_export                           : out std_logic;                                        -- export
-            reg_bsn_source_v2_read_export                          : out std_logic;                                        -- export
-            reg_bsn_source_v2_readdata_export                      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_bsn_source_v2_reset_export                         : out std_logic;                                        -- export
-            reg_bsn_source_v2_write_export                         : out std_logic;                                        -- export
-            reg_bsn_source_v2_writedata_export                     : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_sync_scheduler_xsub_reset_export               : out std_logic;                                        -- export
-            reg_bsn_sync_scheduler_xsub_clk_export                 : out std_logic;                                        -- export
-            reg_bsn_sync_scheduler_xsub_address_export             : out std_logic_vector(3 downto 0);                     -- export
-            reg_bsn_sync_scheduler_xsub_write_export               : out std_logic;                                        -- export
-            reg_bsn_sync_scheduler_xsub_writedata_export           : out std_logic_vector(31 downto 0);                    -- export
-            reg_bsn_sync_scheduler_xsub_read_export                : out std_logic;                                        -- export
-            reg_bsn_sync_scheduler_xsub_readdata_export            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_crosslets_info_address_export                      : out std_logic_vector(3 downto 0);                     -- export
-            reg_crosslets_info_clk_export                          : out std_logic;                                        -- export
-            reg_crosslets_info_read_export                         : out std_logic;                                        -- export
-            reg_crosslets_info_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_crosslets_info_reset_export                        : out std_logic;                                        -- export
-            reg_crosslets_info_write_export                        : out std_logic;                                        -- export
-            reg_crosslets_info_writedata_export                    : out std_logic_vector(31 downto 0);                    -- export
-            reg_diag_data_buffer_bsn_address_export                : out std_logic_vector(4 downto 0);                     -- export
-            reg_diag_data_buffer_bsn_clk_export                    : out std_logic;                                        -- export
-            reg_diag_data_buffer_bsn_read_export                   : out std_logic;                                        -- export
-            reg_diag_data_buffer_bsn_readdata_export               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_diag_data_buffer_bsn_reset_export                  : out std_logic;                                        -- export
-            reg_diag_data_buffer_bsn_write_export                  : out std_logic;                                        -- export
-            reg_diag_data_buffer_bsn_writedata_export              : out std_logic_vector(31 downto 0);                    -- export
-            reg_dp_block_validate_bsn_at_sync_xst_reset_export     : out std_logic;                                        -- export
-            reg_dp_block_validate_bsn_at_sync_xst_clk_export       : out std_logic;                                        -- export
-            reg_dp_block_validate_bsn_at_sync_xst_address_export   : out std_logic_vector(1 downto 0);                     -- export
-            reg_dp_block_validate_bsn_at_sync_xst_write_export     : out std_logic;                                        -- export
-            reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0);                    -- export
-            reg_dp_block_validate_bsn_at_sync_xst_read_export      : out std_logic;                                        -- export
-            reg_dp_block_validate_bsn_at_sync_xst_readdata_export  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_dp_block_validate_err_xst_reset_export             : out std_logic;                                        -- export
-            reg_dp_block_validate_err_xst_clk_export               : out std_logic;                                        -- export
-            reg_dp_block_validate_err_xst_address_export           : out std_logic_vector(3 downto 0);                     -- export
-            reg_dp_block_validate_err_xst_write_export             : out std_logic;                                        -- export
-            reg_dp_block_validate_err_xst_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
-            reg_dp_block_validate_err_xst_read_export              : out std_logic;                                        -- export
-            reg_dp_block_validate_err_xst_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_dp_selector_address_export                         : out std_logic_vector(0 downto 0);                     -- export
-            reg_dp_selector_clk_export                             : out std_logic;                                        -- export
-            reg_dp_selector_read_export                            : out std_logic;                                        -- export
-            reg_dp_selector_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_dp_selector_reset_export                           : out std_logic;                                        -- export
-            reg_dp_selector_write_export                           : out std_logic;                                        -- export
-            reg_dp_selector_writedata_export                       : out std_logic_vector(31 downto 0);                    -- export
-            reg_dp_shiftram_address_export                         : out std_logic_vector(4 downto 0);                     -- export
-            reg_dp_shiftram_clk_export                             : out std_logic;                                        -- export
-            reg_dp_shiftram_read_export                            : out std_logic;                                        -- export
-            reg_dp_shiftram_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_dp_shiftram_reset_export                           : out std_logic;                                        -- export
-            reg_dp_shiftram_write_export                           : out std_logic;                                        -- export
-            reg_dp_shiftram_writedata_export                       : out std_logic_vector(31 downto 0);                    -- export
-            reg_dp_xonoff_address_export                           : out std_logic_vector(1 downto 0);                     -- export
-            reg_dp_xonoff_clk_export                               : out std_logic;                                        -- export
-            reg_dp_xonoff_read_export                              : out std_logic;                                        -- export
-            reg_dp_xonoff_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_dp_xonoff_reset_export                             : out std_logic;                                        -- export
-            reg_dp_xonoff_write_export                             : out std_logic;                                        -- export
-            reg_dp_xonoff_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            reg_dpmm_ctrl_address_export                           : out std_logic_vector(0 downto 0);                     -- export
-            reg_dpmm_ctrl_clk_export                               : out std_logic;                                        -- export
-            reg_dpmm_ctrl_read_export                              : out std_logic;                                        -- export
-            reg_dpmm_ctrl_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_dpmm_ctrl_reset_export                             : out std_logic;                                        -- export
-            reg_dpmm_ctrl_write_export                             : out std_logic;                                        -- export
-            reg_dpmm_ctrl_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            reg_dpmm_data_address_export                           : out std_logic_vector(0 downto 0);                     -- export
-            reg_dpmm_data_clk_export                               : out std_logic;                                        -- export
-            reg_dpmm_data_read_export                              : out std_logic;                                        -- export
-            reg_dpmm_data_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_dpmm_data_reset_export                             : out std_logic;                                        -- export
-            reg_dpmm_data_write_export                             : out std_logic;                                        -- export
-            reg_dpmm_data_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            reg_epcs_address_export                                : out std_logic_vector(2 downto 0);                     -- export
-            reg_epcs_clk_export                                    : out std_logic;                                        -- export
-            reg_epcs_read_export                                   : out std_logic;                                        -- export
-            reg_epcs_readdata_export                               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_epcs_reset_export                                  : out std_logic;                                        -- export
-            reg_epcs_write_export                                  : out std_logic;                                        -- export
-            reg_epcs_writedata_export                              : out std_logic_vector(31 downto 0);                    -- export
-            reg_fpga_temp_sens_address_export                      : out std_logic_vector(2 downto 0);                     -- export
-            reg_fpga_temp_sens_clk_export                          : out std_logic;                                        -- export
-            reg_fpga_temp_sens_read_export                         : out std_logic;                                        -- export
-            reg_fpga_temp_sens_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_fpga_temp_sens_reset_export                        : out std_logic;                                        -- export
-            reg_fpga_temp_sens_write_export                        : out std_logic;                                        -- export
-            reg_fpga_temp_sens_writedata_export                    : out std_logic_vector(31 downto 0);                    -- export
-            reg_fpga_voltage_sens_address_export                   : out std_logic_vector(3 downto 0);                     -- export
-            reg_fpga_voltage_sens_clk_export                       : out std_logic;                                        -- export
-            reg_fpga_voltage_sens_read_export                      : out std_logic;                                        -- export
-            reg_fpga_voltage_sens_readdata_export                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_fpga_voltage_sens_reset_export                     : out std_logic;                                        -- export
-            reg_fpga_voltage_sens_write_export                     : out std_logic;                                        -- export
-            reg_fpga_voltage_sens_writedata_export                 : out std_logic_vector(31 downto 0);                    -- export
-            reg_hdr_dat_address_export                             : out std_logic_vector(6 downto 0);                     -- export
-            reg_hdr_dat_clk_export                                 : out std_logic;                                        -- export
-            reg_hdr_dat_read_export                                : out std_logic;                                        -- export
-            reg_hdr_dat_readdata_export                            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_hdr_dat_reset_export                               : out std_logic;                                        -- export
-            reg_hdr_dat_write_export                               : out std_logic;                                        -- export
-            reg_hdr_dat_writedata_export                           : out std_logic_vector(31 downto 0);                    -- export
-            reg_mmdp_ctrl_address_export                           : out std_logic_vector(0 downto 0);                     -- export
-            reg_mmdp_ctrl_clk_export                               : out std_logic;                                        -- export
-            reg_mmdp_ctrl_read_export                              : out std_logic;                                        -- export
-            reg_mmdp_ctrl_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_mmdp_ctrl_reset_export                             : out std_logic;                                        -- export
-            reg_mmdp_ctrl_write_export                             : out std_logic;                                        -- export
-            reg_mmdp_ctrl_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            reg_mmdp_data_address_export                           : out std_logic_vector(0 downto 0);                     -- export
-            reg_mmdp_data_clk_export                               : out std_logic;                                        -- export
-            reg_mmdp_data_read_export                              : out std_logic;                                        -- export
-            reg_mmdp_data_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_mmdp_data_reset_export                             : out std_logic;                                        -- export
-            reg_mmdp_data_write_export                             : out std_logic;                                        -- export
-            reg_mmdp_data_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            reg_nof_crosslets_reset_export                         : out std_logic;                                        -- export
-            reg_nof_crosslets_clk_export                           : out std_logic;                                        -- export
-            reg_nof_crosslets_address_export                       : out std_logic_vector(0 downto 0);                     -- export
-            reg_nof_crosslets_write_export                         : out std_logic;                                        -- export
-            reg_nof_crosslets_writedata_export                     : out std_logic_vector(31 downto 0);                    -- export
-            reg_nof_crosslets_read_export                          : out std_logic;                                        -- export
-            reg_nof_crosslets_readdata_export                      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_nw_10gbe_eth10g_address_export                     : out std_logic_vector(0 downto 0);                     -- export
-            reg_nw_10gbe_eth10g_clk_export                         : out std_logic;                                        -- export
-            reg_nw_10gbe_eth10g_read_export                        : out std_logic;                                        -- export
-            reg_nw_10gbe_eth10g_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_nw_10gbe_eth10g_reset_export                       : out std_logic;                                        -- export
-            reg_nw_10gbe_eth10g_write_export                       : out std_logic;                                        -- export
-            reg_nw_10gbe_eth10g_writedata_export                   : out std_logic_vector(31 downto 0);                    -- export
-            reg_nw_10gbe_mac_address_export                        : out std_logic_vector(12 downto 0);                    -- export
-            reg_nw_10gbe_mac_clk_export                            : out std_logic;                                        -- export
-            reg_nw_10gbe_mac_read_export                           : out std_logic;                                        -- export
-            reg_nw_10gbe_mac_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_nw_10gbe_mac_reset_export                          : out std_logic;                                        -- export
-            reg_nw_10gbe_mac_write_export                          : out std_logic;                                        -- export
-            reg_nw_10gbe_mac_writedata_export                      : out std_logic_vector(31 downto 0);                    -- export
-            reg_remu_address_export                                : out std_logic_vector(2 downto 0);                     -- export
-            reg_remu_clk_export                                    : out std_logic;                                        -- export
-            reg_remu_read_export                                   : out std_logic;                                        -- export
-            reg_remu_readdata_export                               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_remu_reset_export                                  : out std_logic;                                        -- export
-            reg_remu_write_export                                  : out std_logic;                                        -- export
-            reg_remu_writedata_export                              : out std_logic_vector(31 downto 0);                    -- export
-            reg_ring_info_reset_export                             : out std_logic;                                        -- export
-            reg_ring_info_clk_export                               : out std_logic;                                        -- export
-            reg_ring_info_address_export                           : out std_logic_vector(1 downto 0);                     -- export
-            reg_ring_info_write_export                             : out std_logic;                                        -- export
-            reg_ring_info_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
-            reg_ring_info_read_export                              : out std_logic;                                        -- export
-            reg_ring_info_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_ring_lane_info_xst_reset_export                    : out std_logic;                                        -- export
-            reg_ring_lane_info_xst_clk_export                      : out std_logic;                                        -- export
-            reg_ring_lane_info_xst_address_export                  : out std_logic_vector(0 downto 0);                     -- export
-            reg_ring_lane_info_xst_write_export                    : out std_logic;                                        -- export
-            reg_ring_lane_info_xst_writedata_export                : out std_logic_vector(31 downto 0);                    -- export
-            reg_ring_lane_info_xst_read_export                     : out std_logic;                                        -- export
-            reg_ring_lane_info_xst_readdata_export                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_sdp_info_address_export                            : out std_logic_vector(3 downto 0);                     -- export
-            reg_sdp_info_clk_export                                : out std_logic;                                        -- export
-            reg_sdp_info_read_export                               : out std_logic;                                        -- export
-            reg_sdp_info_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_sdp_info_reset_export                              : out std_logic;                                        -- export
-            reg_sdp_info_write_export                              : out std_logic;                                        -- export
-            reg_sdp_info_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
-            reg_si_address_export                                  : out std_logic_vector(0 downto 0);                     -- export
-            reg_si_clk_export                                      : out std_logic;                                        -- export
-            reg_si_read_export                                     : out std_logic;                                        -- export
-            reg_si_readdata_export                                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_si_reset_export                                    : out std_logic;                                        -- export
-            reg_si_write_export                                    : out std_logic;                                        -- export
-            reg_si_writedata_export                                : out std_logic_vector(31 downto 0);                    -- export
-            reg_stat_enable_bst_address_export                     : out std_logic_vector(1 downto 0);                     -- export
-            reg_stat_enable_bst_clk_export                         : out std_logic;                                        -- export
-            reg_stat_enable_bst_read_export                        : out std_logic;                                        -- export
-            reg_stat_enable_bst_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_stat_enable_bst_reset_export                       : out std_logic;                                        -- export
-            reg_stat_enable_bst_write_export                       : out std_logic;                                        -- export
-            reg_stat_enable_bst_writedata_export                   : out std_logic_vector(31 downto 0);                    -- export
-            reg_stat_enable_sst_address_export                     : out std_logic_vector(0 downto 0);                     -- export
-            reg_stat_enable_sst_clk_export                         : out std_logic;                                        -- export
-            reg_stat_enable_sst_read_export                        : out std_logic;                                        -- export
-            reg_stat_enable_sst_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_stat_enable_sst_reset_export                       : out std_logic;                                        -- export
-            reg_stat_enable_sst_write_export                       : out std_logic;                                        -- export
-            reg_stat_enable_sst_writedata_export                   : out std_logic_vector(31 downto 0);                    -- export
-            reg_stat_enable_xst_address_export                     : out std_logic_vector(0 downto 0);                     -- export
-            reg_stat_enable_xst_clk_export                         : out std_logic;                                        -- export
-            reg_stat_enable_xst_read_export                        : out std_logic;                                        -- export
-            reg_stat_enable_xst_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_stat_enable_xst_reset_export                       : out std_logic;                                        -- export
-            reg_stat_enable_xst_write_export                       : out std_logic;                                        -- export
-            reg_stat_enable_xst_writedata_export                   : out std_logic_vector(31 downto 0);                    -- export
-            reg_stat_hdr_dat_bst_address_export                    : out std_logic_vector(6 downto 0);                     -- export
-            reg_stat_hdr_dat_bst_clk_export                        : out std_logic;                                        -- export
-            reg_stat_hdr_dat_bst_read_export                       : out std_logic;                                        -- export
-            reg_stat_hdr_dat_bst_readdata_export                   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_stat_hdr_dat_bst_reset_export                      : out std_logic;                                        -- export
-            reg_stat_hdr_dat_bst_write_export                      : out std_logic;                                        -- export
-            reg_stat_hdr_dat_bst_writedata_export                  : out std_logic_vector(31 downto 0);                    -- export
-            reg_stat_hdr_dat_sst_address_export                    : out std_logic_vector(5 downto 0);                     -- export
-            reg_stat_hdr_dat_sst_clk_export                        : out std_logic;                                        -- export
-            reg_stat_hdr_dat_sst_read_export                       : out std_logic;                                        -- export
-            reg_stat_hdr_dat_sst_readdata_export                   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_stat_hdr_dat_sst_reset_export                      : out std_logic;                                        -- export
-            reg_stat_hdr_dat_sst_write_export                      : out std_logic;                                        -- export
-            reg_stat_hdr_dat_sst_writedata_export                  : out std_logic_vector(31 downto 0);                    -- export
-            reg_stat_hdr_dat_xst_address_export                    : out std_logic_vector(5 downto 0);                     -- export
-            reg_stat_hdr_dat_xst_clk_export                        : out std_logic;                                        -- export
-            reg_stat_hdr_dat_xst_read_export                       : out std_logic;                                        -- export
-            reg_stat_hdr_dat_xst_readdata_export                   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_stat_hdr_dat_xst_reset_export                      : out std_logic;                                        -- export
-            reg_stat_hdr_dat_xst_write_export                      : out std_logic;                                        -- export
-            reg_stat_hdr_dat_xst_writedata_export                  : out std_logic_vector(31 downto 0);                    -- export
-            reg_tr_10gbe_eth10g_reset_export                       : out std_logic;                                        -- export
-            reg_tr_10gbe_eth10g_clk_export                         : out std_logic;                                        -- export
-            reg_tr_10gbe_eth10g_address_export                     : out std_logic_vector(2 downto 0);                     -- export
-            reg_tr_10gbe_eth10g_write_export                       : out std_logic;                                        -- export
-            reg_tr_10gbe_eth10g_writedata_export                   : out std_logic_vector(31 downto 0);                    -- export
-            reg_tr_10gbe_eth10g_read_export                        : out std_logic;                                        -- export
-            reg_tr_10gbe_eth10g_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_tr_10gbe_mac_reset_export                          : out std_logic;                                        -- export
-            reg_tr_10gbe_mac_clk_export                            : out std_logic;                                        -- export
-            reg_tr_10gbe_mac_address_export                        : out std_logic_vector(14 downto 0);                    -- export
-            reg_tr_10gbe_mac_write_export                          : out std_logic;                                        -- export
-            reg_tr_10gbe_mac_writedata_export                      : out std_logic_vector(31 downto 0);                    -- export
-            reg_tr_10gbe_mac_read_export                           : out std_logic;                                        -- export
-            reg_tr_10gbe_mac_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_wdi_address_export                                 : out std_logic_vector(0 downto 0);                     -- export
-            reg_wdi_clk_export                                     : out std_logic;                                        -- export
-            reg_wdi_read_export                                    : out std_logic;                                        -- export
-            reg_wdi_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_wdi_reset_export                                   : out std_logic;                                        -- export
-            reg_wdi_write_export                                   : out std_logic;                                        -- export
-            reg_wdi_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
-            reg_wg_address_export                                  : out std_logic_vector(5 downto 0);                     -- export
-            reg_wg_clk_export                                      : out std_logic;                                        -- export
-            reg_wg_read_export                                     : out std_logic;                                        -- export
-            reg_wg_readdata_export                                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_wg_reset_export                                    : out std_logic;                                        -- export
-            reg_wg_write_export                                    : out std_logic;                                        -- export
-            reg_wg_writedata_export                                : out std_logic_vector(31 downto 0);                    -- export
-            reg_xst_udp_monitor_reset_export                       : out std_logic;                                        -- export
-            reg_xst_udp_monitor_clk_export                         : out std_logic;                                        -- export
-            reg_xst_udp_monitor_address_export                     : out std_logic_vector(2 downto 0);                     -- export
-            reg_xst_udp_monitor_write_export                       : out std_logic;                                        -- export
-            reg_xst_udp_monitor_writedata_export                   : out std_logic_vector(31 downto 0);                    -- export
-            reg_xst_udp_monitor_read_export                        : out std_logic;                                        -- export
-            reg_xst_udp_monitor_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            rom_system_info_address_export                         : out std_logic_vector(12 downto 0);                    -- export
-            rom_system_info_clk_export                             : out std_logic;                                        -- export
-            rom_system_info_read_export                            : out std_logic;                                        -- export
-            rom_system_info_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            rom_system_info_reset_export                           : out std_logic;                                        -- export
-            rom_system_info_write_export                           : out std_logic;                                        -- export
-            rom_system_info_writedata_export                       : out std_logic_vector(31 downto 0)                     -- export
+            avs_eth_0_clk_export                                    : out std_logic;                                        -- export
+            avs_eth_0_irq_export                                    : in  std_logic                     := 'X';             -- export
+            avs_eth_0_ram_address_export                            : out std_logic_vector(9 downto 0);                     -- export
+            avs_eth_0_ram_read_export                               : out std_logic;                                        -- export
+            avs_eth_0_ram_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_ram_write_export                              : out std_logic;                                        -- export
+            avs_eth_0_ram_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_reg_address_export                            : out std_logic_vector(3 downto 0);                     -- export
+            avs_eth_0_reg_read_export                               : out std_logic;                                        -- export
+            avs_eth_0_reg_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_reg_write_export                              : out std_logic;                                        -- export
+            avs_eth_0_reg_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_reset_export                                  : out std_logic;                                        -- export
+            avs_eth_0_tse_address_export                            : out std_logic_vector(9 downto 0);                     -- export
+            avs_eth_0_tse_read_export                               : out std_logic;                                        -- export
+            avs_eth_0_tse_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_tse_waitrequest_export                        : in  std_logic                     := 'X';             -- export
+            avs_eth_0_tse_write_export                              : out std_logic;                                        -- export
+            avs_eth_0_tse_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            clk_clk                                                 : in  std_logic                     := 'X';             -- clk
+            reset_reset_n                                           : in  std_logic                     := 'X';             -- reset_n
+            jesd204b_address_export                                 : out std_logic_vector(11 downto 0);                    -- export
+            jesd204b_clk_export                                     : out std_logic;                                        -- export
+            jesd204b_read_export                                    : out std_logic;                                        -- export
+            jesd204b_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            jesd204b_reset_export                                   : out std_logic;                                        -- export
+            jesd204b_write_export                                   : out std_logic;                                        -- export
+            jesd204b_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
+            pio_jesd_ctrl_address_export                            : out std_logic_vector(0 downto 0);                     -- export
+            pio_jesd_ctrl_clk_export                                : out std_logic;                                        -- export
+            pio_jesd_ctrl_read_export                               : out std_logic;                                        -- export
+            pio_jesd_ctrl_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            pio_jesd_ctrl_reset_export                              : out std_logic;                                        -- export
+            pio_jesd_ctrl_write_export                              : out std_logic;                                        -- export
+            pio_jesd_ctrl_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            pio_pps_address_export                                  : out std_logic_vector(1 downto 0);                     -- export
+            pio_pps_clk_export                                      : out std_logic;                                        -- export
+            pio_pps_read_export                                     : out std_logic;                                        -- export
+            pio_pps_readdata_export                                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            pio_pps_reset_export                                    : out std_logic;                                        -- export
+            pio_pps_write_export                                    : out std_logic;                                        -- export
+            pio_pps_writedata_export                                : out std_logic_vector(31 downto 0);                    -- export
+            pio_system_info_address_export                          : out std_logic_vector(4 downto 0);                     -- export
+            pio_system_info_clk_export                              : out std_logic;                                        -- export
+            pio_system_info_read_export                             : out std_logic;                                        -- export
+            pio_system_info_readdata_export                         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            pio_system_info_reset_export                            : out std_logic;                                        -- export
+            pio_system_info_write_export                            : out std_logic;                                        -- export
+            pio_system_info_writedata_export                        : out std_logic_vector(31 downto 0);                    -- export
+            pio_wdi_external_connection_export                      : out std_logic;                                        -- export
+            ram_bf_weights_address_export                           : out std_logic_vector(14 downto 0);                    -- export
+            ram_bf_weights_clk_export                               : out std_logic;                                        -- export
+            ram_bf_weights_read_export                              : out std_logic;                                        -- export
+            ram_bf_weights_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_bf_weights_reset_export                             : out std_logic;                                        -- export
+            ram_bf_weights_write_export                             : out std_logic;                                        -- export
+            ram_bf_weights_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
+            ram_diag_data_buffer_bsn_address_export                 : out std_logic_vector(20 downto 0);                    -- export
+            ram_diag_data_buffer_bsn_clk_export                     : out std_logic;                                        -- export
+            ram_diag_data_buffer_bsn_read_export                    : out std_logic;                                        -- export
+            ram_diag_data_buffer_bsn_readdata_export                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_diag_data_buffer_bsn_reset_export                   : out std_logic;                                        -- export
+            ram_diag_data_buffer_bsn_write_export                   : out std_logic;                                        -- export
+            ram_diag_data_buffer_bsn_writedata_export               : out std_logic_vector(31 downto 0);                    -- export
+            ram_equalizer_gains_address_export                      : out std_logic_vector(12 downto 0);                    -- export
+            ram_equalizer_gains_clk_export                          : out std_logic;                                        -- export
+            ram_equalizer_gains_read_export                         : out std_logic;                                        -- export
+            ram_equalizer_gains_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_equalizer_gains_reset_export                        : out std_logic;                                        -- export
+            ram_equalizer_gains_write_export                        : out std_logic;                                        -- export
+            ram_equalizer_gains_writedata_export                    : out std_logic_vector(31 downto 0);                    -- export
+            ram_fil_coefs_address_export                            : out std_logic_vector(13 downto 0);                    -- export
+            ram_fil_coefs_clk_export                                : out std_logic;                                        -- export
+            ram_fil_coefs_read_export                               : out std_logic;                                        -- export
+            ram_fil_coefs_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_fil_coefs_reset_export                              : out std_logic;                                        -- export
+            ram_fil_coefs_write_export                              : out std_logic;                                        -- export
+            ram_fil_coefs_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            ram_scrap_address_export                                : out std_logic_vector(8 downto 0);                     -- export
+            ram_scrap_clk_export                                    : out std_logic;                                        -- export
+            ram_scrap_read_export                                   : out std_logic;                                        -- export
+            ram_scrap_readdata_export                               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_scrap_reset_export                                  : out std_logic;                                        -- export
+            ram_scrap_write_export                                  : out std_logic;                                        -- export
+            ram_scrap_writedata_export                              : out std_logic_vector(31 downto 0);                    -- export
+            ram_ss_ss_wide_address_export                           : out std_logic_vector(13 downto 0);                    -- export
+            ram_ss_ss_wide_clk_export                               : out std_logic;                                        -- export
+            ram_ss_ss_wide_read_export                              : out std_logic;                                        -- export
+            ram_ss_ss_wide_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_ss_ss_wide_reset_export                             : out std_logic;                                        -- export
+            ram_ss_ss_wide_write_export                             : out std_logic;                                        -- export
+            ram_ss_ss_wide_writedata_export                         : out std_logic_vector(31 downto 0);                    -- export
+            ram_st_bst_address_export                               : out std_logic_vector(11 downto 0);                    -- export
+            ram_st_bst_clk_export                                   : out std_logic;                                        -- export
+            ram_st_bst_read_export                                  : out std_logic;                                        -- export
+            ram_st_bst_readdata_export                              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_st_bst_reset_export                                 : out std_logic;                                        -- export
+            ram_st_bst_write_export                                 : out std_logic;                                        -- export
+            ram_st_bst_writedata_export                             : out std_logic_vector(31 downto 0);                    -- export
+            ram_st_histogram_reset_export                           : out std_logic;                                        -- export
+            ram_st_histogram_clk_export                             : out std_logic;                                        -- export
+            ram_st_histogram_address_export                         : out std_logic_vector(12 downto 0);                    -- export
+            ram_st_histogram_write_export                           : out std_logic;                                        -- export
+            ram_st_histogram_writedata_export                       : out std_logic_vector(31 downto 0);                    -- export
+            ram_st_histogram_read_export                            : out std_logic;                                        -- export
+            ram_st_histogram_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_st_sst_address_export                               : out std_logic_vector(13 downto 0);                    -- export
+            ram_st_sst_clk_export                                   : out std_logic;                                        -- export
+            ram_st_sst_read_export                                  : out std_logic;                                        -- export
+            ram_st_sst_readdata_export                              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_st_sst_reset_export                                 : out std_logic;                                        -- export
+            ram_st_sst_write_export                                 : out std_logic;                                        -- export
+            ram_st_sst_writedata_export                             : out std_logic_vector(31 downto 0);                    -- export
+            ram_st_xsq_address_export                               : out std_logic_vector(15 downto 0);                    -- export
+            ram_st_xsq_clk_export                                   : out std_logic;                                        -- export
+            ram_st_xsq_read_export                                  : out std_logic;                                        -- export
+            ram_st_xsq_readdata_export                              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_st_xsq_reset_export                                 : out std_logic;                                        -- export
+            ram_st_xsq_write_export                                 : out std_logic;                                        -- export
+            ram_st_xsq_writedata_export                             : out std_logic_vector(31 downto 0);                    -- export
+            ram_wg_address_export                                   : out std_logic_vector(13 downto 0);                    -- export
+            ram_wg_clk_export                                       : out std_logic;                                        -- export
+            ram_wg_read_export                                      : out std_logic;                                        -- export
+            ram_wg_readdata_export                                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_wg_reset_export                                     : out std_logic;                                        -- export
+            ram_wg_write_export                                     : out std_logic;                                        -- export
+            ram_wg_writedata_export                                 : out std_logic_vector(31 downto 0);                    -- export
+            reg_aduh_monitor_address_export                         : out std_logic_vector(5 downto 0);                     -- export
+            reg_aduh_monitor_clk_export                             : out std_logic;                                        -- export
+            reg_aduh_monitor_read_export                            : out std_logic;                                        -- export
+            reg_aduh_monitor_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_aduh_monitor_reset_export                           : out std_logic;                                        -- export
+            reg_aduh_monitor_write_export                           : out std_logic;                                        -- export
+            reg_aduh_monitor_writedata_export                       : out std_logic_vector(31 downto 0);                    -- export
+            reg_bf_scale_address_export                             : out std_logic_vector(1 downto 0);                     -- export
+            reg_bf_scale_clk_export                                 : out std_logic;                                        -- export
+            reg_bf_scale_read_export                                : out std_logic;                                        -- export
+            reg_bf_scale_readdata_export                            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bf_scale_reset_export                               : out std_logic;                                        -- export
+            reg_bf_scale_write_export                               : out std_logic;                                        -- export
+            reg_bf_scale_writedata_export                           : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_align_v2_reset_export                           : out std_logic;                                        -- export
+            reg_bsn_align_v2_clk_export                             : out std_logic;                                        -- export
+            reg_bsn_align_v2_address_export                         : out std_logic_vector(4 downto 0);                     -- export
+            reg_bsn_align_v2_write_export                           : out std_logic;                                        -- export
+            reg_bsn_align_v2_writedata_export                       : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_align_v2_read_export                            : out std_logic;                                        -- export
+            reg_bsn_align_v2_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bsn_monitor_input_address_export                    : out std_logic_vector(7 downto 0);                     -- export
+            reg_bsn_monitor_input_clk_export                        : out std_logic;                                        -- export
+            reg_bsn_monitor_input_read_export                       : out std_logic;                                        -- export
+            reg_bsn_monitor_input_readdata_export                   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bsn_monitor_input_reset_export                      : out std_logic;                                        -- export
+            reg_bsn_monitor_input_write_export                      : out std_logic;                                        -- export
+            reg_bsn_monitor_input_writedata_export                  : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_reset_export      : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_clk_export        : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_address_export    : out std_logic_vector(6 downto 0);                     -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_write_export      : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_writedata_export  : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_read_export       : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_input_readdata_export   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_reset_export     : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_clk_export       : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_address_export   : out std_logic_vector(2 downto 0);                     -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_write_export     : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_writedata_export : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_read_export      : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_bsn_align_v2_output_readdata_export  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bsn_monitor_v2_ring_rx_xst_reset_export             : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_ring_rx_xst_clk_export               : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_ring_rx_xst_address_export           : out std_logic_vector(6 downto 0);                     -- export
+            reg_bsn_monitor_v2_ring_rx_xst_write_export             : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_ring_rx_xst_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_ring_rx_xst_read_export              : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_ring_rx_xst_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bsn_monitor_v2_ring_tx_xst_reset_export             : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_ring_tx_xst_clk_export               : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_ring_tx_xst_address_export           : out std_logic_vector(6 downto 0);                     -- export
+            reg_bsn_monitor_v2_ring_tx_xst_write_export             : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_ring_tx_xst_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_ring_tx_xst_read_export              : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_ring_tx_xst_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bsn_monitor_v2_xst_offload_reset_export             : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_xst_offload_clk_export               : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_xst_offload_address_export           : out std_logic_vector(2 downto 0);                     -- export
+            reg_bsn_monitor_v2_xst_offload_write_export             : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_xst_offload_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_xst_offload_read_export              : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_xst_offload_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bsn_scheduler_address_export                        : out std_logic_vector(0 downto 0);                     -- export
+            reg_bsn_scheduler_clk_export                            : out std_logic;                                        -- export
+            reg_bsn_scheduler_read_export                           : out std_logic;                                        -- export
+            reg_bsn_scheduler_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bsn_scheduler_reset_export                          : out std_logic;                                        -- export
+            reg_bsn_scheduler_write_export                          : out std_logic;                                        -- export
+            reg_bsn_scheduler_writedata_export                      : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_source_v2_address_export                        : out std_logic_vector(2 downto 0);                     -- export
+            reg_bsn_source_v2_clk_export                            : out std_logic;                                        -- export
+            reg_bsn_source_v2_read_export                           : out std_logic;                                        -- export
+            reg_bsn_source_v2_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bsn_source_v2_reset_export                          : out std_logic;                                        -- export
+            reg_bsn_source_v2_write_export                          : out std_logic;                                        -- export
+            reg_bsn_source_v2_writedata_export                      : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_sync_scheduler_xsub_reset_export                : out std_logic;                                        -- export
+            reg_bsn_sync_scheduler_xsub_clk_export                  : out std_logic;                                        -- export
+            reg_bsn_sync_scheduler_xsub_address_export              : out std_logic_vector(3 downto 0);                     -- export
+            reg_bsn_sync_scheduler_xsub_write_export                : out std_logic;                                        -- export
+            reg_bsn_sync_scheduler_xsub_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_sync_scheduler_xsub_read_export                 : out std_logic;                                        -- export
+            reg_bsn_sync_scheduler_xsub_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_crosslets_info_address_export                       : out std_logic_vector(3 downto 0);                     -- export
+            reg_crosslets_info_clk_export                           : out std_logic;                                        -- export
+            reg_crosslets_info_read_export                          : out std_logic;                                        -- export
+            reg_crosslets_info_readdata_export                      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_crosslets_info_reset_export                         : out std_logic;                                        -- export
+            reg_crosslets_info_write_export                         : out std_logic;                                        -- export
+            reg_crosslets_info_writedata_export                     : out std_logic_vector(31 downto 0);                    -- export
+            reg_diag_data_buffer_bsn_address_export                 : out std_logic_vector(4 downto 0);                     -- export
+            reg_diag_data_buffer_bsn_clk_export                     : out std_logic;                                        -- export
+            reg_diag_data_buffer_bsn_read_export                    : out std_logic;                                        -- export
+            reg_diag_data_buffer_bsn_readdata_export                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_diag_data_buffer_bsn_reset_export                   : out std_logic;                                        -- export
+            reg_diag_data_buffer_bsn_write_export                   : out std_logic;                                        -- export
+            reg_diag_data_buffer_bsn_writedata_export               : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_block_validate_bsn_at_sync_xst_reset_export      : out std_logic;                                        -- export
+            reg_dp_block_validate_bsn_at_sync_xst_clk_export        : out std_logic;                                        -- export
+            reg_dp_block_validate_bsn_at_sync_xst_address_export    : out std_logic_vector(1 downto 0);                     -- export
+            reg_dp_block_validate_bsn_at_sync_xst_write_export      : out std_logic;                                        -- export
+            reg_dp_block_validate_bsn_at_sync_xst_writedata_export  : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_block_validate_bsn_at_sync_xst_read_export       : out std_logic;                                        -- export
+            reg_dp_block_validate_bsn_at_sync_xst_readdata_export   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_block_validate_err_xst_reset_export              : out std_logic;                                        -- export
+            reg_dp_block_validate_err_xst_clk_export                : out std_logic;                                        -- export
+            reg_dp_block_validate_err_xst_address_export            : out std_logic_vector(3 downto 0);                     -- export
+            reg_dp_block_validate_err_xst_write_export              : out std_logic;                                        -- export
+            reg_dp_block_validate_err_xst_writedata_export          : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_block_validate_err_xst_read_export               : out std_logic;                                        -- export
+            reg_dp_block_validate_err_xst_readdata_export           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_selector_address_export                          : out std_logic_vector(0 downto 0);                     -- export
+            reg_dp_selector_clk_export                              : out std_logic;                                        -- export
+            reg_dp_selector_read_export                             : out std_logic;                                        -- export
+            reg_dp_selector_readdata_export                         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_selector_reset_export                            : out std_logic;                                        -- export
+            reg_dp_selector_write_export                            : out std_logic;                                        -- export
+            reg_dp_selector_writedata_export                        : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_shiftram_address_export                          : out std_logic_vector(4 downto 0);                     -- export
+            reg_dp_shiftram_clk_export                              : out std_logic;                                        -- export
+            reg_dp_shiftram_read_export                             : out std_logic;                                        -- export
+            reg_dp_shiftram_readdata_export                         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_shiftram_reset_export                            : out std_logic;                                        -- export
+            reg_dp_shiftram_write_export                            : out std_logic;                                        -- export
+            reg_dp_shiftram_writedata_export                        : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_xonoff_address_export                            : out std_logic_vector(1 downto 0);                     -- export
+            reg_dp_xonoff_clk_export                                : out std_logic;                                        -- export
+            reg_dp_xonoff_read_export                               : out std_logic;                                        -- export
+            reg_dp_xonoff_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_xonoff_reset_export                              : out std_logic;                                        -- export
+            reg_dp_xonoff_write_export                              : out std_logic;                                        -- export
+            reg_dp_xonoff_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            reg_dpmm_ctrl_address_export                            : out std_logic_vector(0 downto 0);                     -- export
+            reg_dpmm_ctrl_clk_export                                : out std_logic;                                        -- export
+            reg_dpmm_ctrl_read_export                               : out std_logic;                                        -- export
+            reg_dpmm_ctrl_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dpmm_ctrl_reset_export                              : out std_logic;                                        -- export
+            reg_dpmm_ctrl_write_export                              : out std_logic;                                        -- export
+            reg_dpmm_ctrl_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            reg_dpmm_data_address_export                            : out std_logic_vector(0 downto 0);                     -- export
+            reg_dpmm_data_clk_export                                : out std_logic;                                        -- export
+            reg_dpmm_data_read_export                               : out std_logic;                                        -- export
+            reg_dpmm_data_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dpmm_data_reset_export                              : out std_logic;                                        -- export
+            reg_dpmm_data_write_export                              : out std_logic;                                        -- export
+            reg_dpmm_data_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            reg_epcs_address_export                                 : out std_logic_vector(2 downto 0);                     -- export
+            reg_epcs_clk_export                                     : out std_logic;                                        -- export
+            reg_epcs_read_export                                    : out std_logic;                                        -- export
+            reg_epcs_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_epcs_reset_export                                   : out std_logic;                                        -- export
+            reg_epcs_write_export                                   : out std_logic;                                        -- export
+            reg_epcs_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
+            reg_fpga_temp_sens_address_export                       : out std_logic_vector(2 downto 0);                     -- export
+            reg_fpga_temp_sens_clk_export                           : out std_logic;                                        -- export
+            reg_fpga_temp_sens_read_export                          : out std_logic;                                        -- export
+            reg_fpga_temp_sens_readdata_export                      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_fpga_temp_sens_reset_export                         : out std_logic;                                        -- export
+            reg_fpga_temp_sens_write_export                         : out std_logic;                                        -- export
+            reg_fpga_temp_sens_writedata_export                     : out std_logic_vector(31 downto 0);                    -- export
+            reg_fpga_voltage_sens_address_export                    : out std_logic_vector(3 downto 0);                     -- export
+            reg_fpga_voltage_sens_clk_export                        : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_read_export                       : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_readdata_export                   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_fpga_voltage_sens_reset_export                      : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_write_export                      : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_writedata_export                  : out std_logic_vector(31 downto 0);                    -- export
+            reg_hdr_dat_address_export                              : out std_logic_vector(6 downto 0);                     -- export
+            reg_hdr_dat_clk_export                                  : out std_logic;                                        -- export
+            reg_hdr_dat_read_export                                 : out std_logic;                                        -- export
+            reg_hdr_dat_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_hdr_dat_reset_export                                : out std_logic;                                        -- export
+            reg_hdr_dat_write_export                                : out std_logic;                                        -- export
+            reg_hdr_dat_writedata_export                            : out std_logic_vector(31 downto 0);                    -- export
+            reg_mmdp_ctrl_address_export                            : out std_logic_vector(0 downto 0);                     -- export
+            reg_mmdp_ctrl_clk_export                                : out std_logic;                                        -- export
+            reg_mmdp_ctrl_read_export                               : out std_logic;                                        -- export
+            reg_mmdp_ctrl_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_mmdp_ctrl_reset_export                              : out std_logic;                                        -- export
+            reg_mmdp_ctrl_write_export                              : out std_logic;                                        -- export
+            reg_mmdp_ctrl_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            reg_mmdp_data_address_export                            : out std_logic_vector(0 downto 0);                     -- export
+            reg_mmdp_data_clk_export                                : out std_logic;                                        -- export
+            reg_mmdp_data_read_export                               : out std_logic;                                        -- export
+            reg_mmdp_data_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_mmdp_data_reset_export                              : out std_logic;                                        -- export
+            reg_mmdp_data_write_export                              : out std_logic;                                        -- export
+            reg_mmdp_data_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            reg_nof_crosslets_reset_export                          : out std_logic;                                        -- export
+            reg_nof_crosslets_clk_export                            : out std_logic;                                        -- export
+            reg_nof_crosslets_address_export                        : out std_logic_vector(0 downto 0);                     -- export
+            reg_nof_crosslets_write_export                          : out std_logic;                                        -- export
+            reg_nof_crosslets_writedata_export                      : out std_logic_vector(31 downto 0);                    -- export
+            reg_nof_crosslets_read_export                           : out std_logic;                                        -- export
+            reg_nof_crosslets_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_nw_10gbe_eth10g_address_export                      : out std_logic_vector(0 downto 0);                     -- export
+            reg_nw_10gbe_eth10g_clk_export                          : out std_logic;                                        -- export
+            reg_nw_10gbe_eth10g_read_export                         : out std_logic;                                        -- export
+            reg_nw_10gbe_eth10g_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_nw_10gbe_eth10g_reset_export                        : out std_logic;                                        -- export
+            reg_nw_10gbe_eth10g_write_export                        : out std_logic;                                        -- export
+            reg_nw_10gbe_eth10g_writedata_export                    : out std_logic_vector(31 downto 0);                    -- export
+            reg_nw_10gbe_mac_address_export                         : out std_logic_vector(12 downto 0);                    -- export
+            reg_nw_10gbe_mac_clk_export                             : out std_logic;                                        -- export
+            reg_nw_10gbe_mac_read_export                            : out std_logic;                                        -- export
+            reg_nw_10gbe_mac_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_nw_10gbe_mac_reset_export                           : out std_logic;                                        -- export
+            reg_nw_10gbe_mac_write_export                           : out std_logic;                                        -- export
+            reg_nw_10gbe_mac_writedata_export                       : out std_logic_vector(31 downto 0);                    -- export
+            reg_remu_address_export                                 : out std_logic_vector(2 downto 0);                     -- export
+            reg_remu_clk_export                                     : out std_logic;                                        -- export
+            reg_remu_read_export                                    : out std_logic;                                        -- export
+            reg_remu_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_remu_reset_export                                   : out std_logic;                                        -- export
+            reg_remu_write_export                                   : out std_logic;                                        -- export
+            reg_remu_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
+            reg_ring_info_reset_export                              : out std_logic;                                        -- export
+            reg_ring_info_clk_export                                : out std_logic;                                        -- export
+            reg_ring_info_address_export                            : out std_logic_vector(1 downto 0);                     -- export
+            reg_ring_info_write_export                              : out std_logic;                                        -- export
+            reg_ring_info_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            reg_ring_info_read_export                               : out std_logic;                                        -- export
+            reg_ring_info_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_ring_lane_info_xst_reset_export                     : out std_logic;                                        -- export
+            reg_ring_lane_info_xst_clk_export                       : out std_logic;                                        -- export
+            reg_ring_lane_info_xst_address_export                   : out std_logic_vector(0 downto 0);                     -- export
+            reg_ring_lane_info_xst_write_export                     : out std_logic;                                        -- export
+            reg_ring_lane_info_xst_writedata_export                 : out std_logic_vector(31 downto 0);                    -- export
+            reg_ring_lane_info_xst_read_export                      : out std_logic;                                        -- export
+            reg_ring_lane_info_xst_readdata_export                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_sdp_info_address_export                             : out std_logic_vector(3 downto 0);                     -- export
+            reg_sdp_info_clk_export                                 : out std_logic;                                        -- export
+            reg_sdp_info_read_export                                : out std_logic;                                        -- export
+            reg_sdp_info_readdata_export                            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_sdp_info_reset_export                               : out std_logic;                                        -- export
+            reg_sdp_info_write_export                               : out std_logic;                                        -- export
+            reg_sdp_info_writedata_export                           : out std_logic_vector(31 downto 0);                    -- export
+            reg_si_address_export                                   : out std_logic_vector(0 downto 0);                     -- export
+            reg_si_clk_export                                       : out std_logic;                                        -- export
+            reg_si_read_export                                      : out std_logic;                                        -- export
+            reg_si_readdata_export                                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_si_reset_export                                     : out std_logic;                                        -- export
+            reg_si_write_export                                     : out std_logic;                                        -- export
+            reg_si_writedata_export                                 : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_enable_bst_address_export                      : out std_logic_vector(1 downto 0);                     -- export
+            reg_stat_enable_bst_clk_export                          : out std_logic;                                        -- export
+            reg_stat_enable_bst_read_export                         : out std_logic;                                        -- export
+            reg_stat_enable_bst_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_enable_bst_reset_export                        : out std_logic;                                        -- export
+            reg_stat_enable_bst_write_export                        : out std_logic;                                        -- export
+            reg_stat_enable_bst_writedata_export                    : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_enable_sst_address_export                      : out std_logic_vector(0 downto 0);                     -- export
+            reg_stat_enable_sst_clk_export                          : out std_logic;                                        -- export
+            reg_stat_enable_sst_read_export                         : out std_logic;                                        -- export
+            reg_stat_enable_sst_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_enable_sst_reset_export                        : out std_logic;                                        -- export
+            reg_stat_enable_sst_write_export                        : out std_logic;                                        -- export
+            reg_stat_enable_sst_writedata_export                    : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_enable_xst_address_export                      : out std_logic_vector(0 downto 0);                     -- export
+            reg_stat_enable_xst_clk_export                          : out std_logic;                                        -- export
+            reg_stat_enable_xst_read_export                         : out std_logic;                                        -- export
+            reg_stat_enable_xst_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_enable_xst_reset_export                        : out std_logic;                                        -- export
+            reg_stat_enable_xst_write_export                        : out std_logic;                                        -- export
+            reg_stat_enable_xst_writedata_export                    : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_hdr_dat_bst_address_export                     : out std_logic_vector(6 downto 0);                     -- export
+            reg_stat_hdr_dat_bst_clk_export                         : out std_logic;                                        -- export
+            reg_stat_hdr_dat_bst_read_export                        : out std_logic;                                        -- export
+            reg_stat_hdr_dat_bst_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_hdr_dat_bst_reset_export                       : out std_logic;                                        -- export
+            reg_stat_hdr_dat_bst_write_export                       : out std_logic;                                        -- export
+            reg_stat_hdr_dat_bst_writedata_export                   : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_hdr_dat_sst_address_export                     : out std_logic_vector(5 downto 0);                     -- export
+            reg_stat_hdr_dat_sst_clk_export                         : out std_logic;                                        -- export
+            reg_stat_hdr_dat_sst_read_export                        : out std_logic;                                        -- export
+            reg_stat_hdr_dat_sst_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_hdr_dat_sst_reset_export                       : out std_logic;                                        -- export
+            reg_stat_hdr_dat_sst_write_export                       : out std_logic;                                        -- export
+            reg_stat_hdr_dat_sst_writedata_export                   : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_hdr_dat_xst_address_export                     : out std_logic_vector(5 downto 0);                     -- export
+            reg_stat_hdr_dat_xst_clk_export                         : out std_logic;                                        -- export
+            reg_stat_hdr_dat_xst_read_export                        : out std_logic;                                        -- export
+            reg_stat_hdr_dat_xst_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_hdr_dat_xst_reset_export                       : out std_logic;                                        -- export
+            reg_stat_hdr_dat_xst_write_export                       : out std_logic;                                        -- export
+            reg_stat_hdr_dat_xst_writedata_export                   : out std_logic_vector(31 downto 0);                    -- export
+            reg_tr_10gbe_eth10g_reset_export                        : out std_logic;                                        -- export
+            reg_tr_10gbe_eth10g_clk_export                          : out std_logic;                                        -- export
+            reg_tr_10gbe_eth10g_address_export                      : out std_logic_vector(2 downto 0);                     -- export
+            reg_tr_10gbe_eth10g_write_export                        : out std_logic;                                        -- export
+            reg_tr_10gbe_eth10g_writedata_export                    : out std_logic_vector(31 downto 0);                    -- export
+            reg_tr_10gbe_eth10g_read_export                         : out std_logic;                                        -- export
+            reg_tr_10gbe_eth10g_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_tr_10gbe_mac_reset_export                           : out std_logic;                                        -- export
+            reg_tr_10gbe_mac_clk_export                             : out std_logic;                                        -- export
+            reg_tr_10gbe_mac_address_export                         : out std_logic_vector(14 downto 0);                    -- export
+            reg_tr_10gbe_mac_write_export                           : out std_logic;                                        -- export
+            reg_tr_10gbe_mac_writedata_export                       : out std_logic_vector(31 downto 0);                    -- export
+            reg_tr_10gbe_mac_read_export                            : out std_logic;                                        -- export
+            reg_tr_10gbe_mac_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_wdi_address_export                                  : out std_logic_vector(0 downto 0);                     -- export
+            reg_wdi_clk_export                                      : out std_logic;                                        -- export
+            reg_wdi_read_export                                     : out std_logic;                                        -- export
+            reg_wdi_readdata_export                                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_wdi_reset_export                                    : out std_logic;                                        -- export
+            reg_wdi_write_export                                    : out std_logic;                                        -- export
+            reg_wdi_writedata_export                                : out std_logic_vector(31 downto 0);                    -- export
+            reg_wg_address_export                                   : out std_logic_vector(5 downto 0);                     -- export
+            reg_wg_clk_export                                       : out std_logic;                                        -- export
+            reg_wg_read_export                                      : out std_logic;                                        -- export
+            reg_wg_readdata_export                                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_wg_reset_export                                     : out std_logic;                                        -- export
+            reg_wg_write_export                                     : out std_logic;                                        -- export
+            reg_wg_writedata_export                                 : out std_logic_vector(31 downto 0);                    -- export
+            rom_system_info_address_export                          : out std_logic_vector(12 downto 0);                    -- export
+            rom_system_info_clk_export                              : out std_logic;                                        -- export
+            rom_system_info_read_export                             : out std_logic;                                        -- export
+            rom_system_info_readdata_export                         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            rom_system_info_reset_export                            : out std_logic;                                        -- export
+            rom_system_info_write_export                            : out std_logic;                                        -- export
+            rom_system_info_writedata_export                        : out std_logic_vector(31 downto 0)                     -- export
         );
     end component qsys_lofar2_unb2c_sdp_station;
 END qsys_lofar2_unb2c_sdp_station_pkg;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index a97a3e1d94..1cedc89fbc 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -475,10 +475,10 @@ PACKAGE sdp_pkg is
   CONSTANT c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : NATURAL := 4; 
   CONSTANT c_sdp_ram_st_xsq_addr_w                  : NATURAL := ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * c_sdp_W_statistic_sz);
   CONSTANT c_sdp_ram_st_xsq_arr_addr_w              : NATURAL := ceil_log2(c_sdp_P_sq) + c_sdp_ram_st_xsq_addr_w;
-  CONSTANT c_sdp_reg_bsn_align_addr_w                         : NATURAL := ceil_log2(c_sdp_P_sq); 
-  CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_input_addr_w    : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_Log2(7);
-  CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_output_addr_w   : NATURAL := ceil_Log2(7);
-  CONSTANT c_sdp_reg_xst_udp_monitor_addr_w                   : NATURAL := ceil_Log2(7);
+  CONSTANT c_sdp_reg_bsn_align_v2_addr_w                         : NATURAL := ceil_log2(2*c_sdp_P_sq); 
+  CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_v2_input_addr_w    : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_Log2(7);
+  CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_v2_output_addr_w   : NATURAL := ceil_Log2(7);
+  CONSTANT c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w           : NATURAL := ceil_Log2(7);
   CONSTANT c_sdp_reg_ring_lane_info_xst_addr_w                : NATURAL := 1;
   CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w        : NATURAL := ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
   CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_xst_addr_w        : NATURAL := ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
index 745a4113ab..2b6912dc42 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
@@ -202,8 +202,8 @@ BEGIN
           exp_sosi.eop <= '1';
         END IF;
 
-        exp_sosi.re <= TO_DP_DSP_DATA(   (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
-        exp_sosi.im <= TO_DP_DSP_DATA(1+ (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
+        exp_sosi.re <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA(   (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5)(c_sdp_W_crosslet-1 DOWNTO 0));
+        exp_sosi.im <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA(1+ (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5)(c_sdp_W_crosslet-1 DOWNTO 0));
         proc_common_wait_some_cycles(clk, 1);
 
       END LOOP;
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index bb68ec6542..a86b46f925 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -115,15 +115,19 @@ peripherals:
       # MM port for dp_bsn_align_v2.vhd
       - mm_port_name: REG_DP_BSN_ALIGN_V2
         mm_port_type: REG
-        mm_port_span: 1 * MM_BUS_SIZE
+        mm_port_span: 2 * MM_BUS_SIZE
         mm_port_description: ""
         number_of_mm_ports: g_nof_streams
         fields:
           - - field_name: enable
               field_description: "Stream enable per stream via bits g_nof_streams-1 : 0. Bit value 0 disables the stream, 1 enables the stream. Disabled streams are not aligned."
-              address_offset: 0x0
+              address_offset: 0 * MM_BUS_SIZE
               mm_width: 1
               access_mode: RW
+          - - field_name: replaced_pkt_cnt
+              field_description: "Count of packets that contain replacement data per sync interval."
+              address_offset: 1 * MM_BUS_SIZE
+              access_mode: R0
 
 
   - peripheral_name: dp_bsn_source    # pi_dp_bsn_source.py
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
index 42e3ae8e6b..b23469ce50 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
@@ -76,7 +76,8 @@ ENTITY dp_bsn_align_v2 IS
     node_index     : IN  NATURAL RANGE 0 TO g_nof_aligners_max-1 := 0;  -- only used when g_nof_aligners_max > 1
 
     -- MM control
-    stream_en_arr  : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'1');
+    stream_en_arr            : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'1');
+    stream_replaced_cnt_arr  : OUT t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
 
     -- Streaming input
     in_sosi_arr    : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
@@ -140,6 +141,7 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
     fill_cipo_arr        : t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0);  -- used combinatorial to contain rd_cipo_arr from buffer or replacement data
     out_bsn              : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);  -- hold BSN until next sop, for easy view in Wave window
     out_channel_arr      : t_channel_arr(g_nof_streams-1 DOWNTO 0);  -- hold channel until next sop per stream, for easy view in Wave window
+    replace_cnt_en       : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
   END RECORD;
 
   -- Wires and auxiliary variables in p_comb
@@ -168,7 +170,8 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
                                   c_mem_copi_rst,
                                   (OTHERS=>c_mem_cipo_rst),
                                   (OTHERS=>'0'),
-                                  (OTHERS=>(OTHERS=>'0')));
+                                  (OTHERS=>(OTHERS=>'0')),
+                                  (OTHERS=>'0'));
 
   CONSTANT c_comb_rst  : t_comb := (c_dp_sosi_rst,
                                    (OTHERS=>'0'),
@@ -197,6 +200,12 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
   SIGNAL rd_copi           : t_mem_copi;
   SIGNAL comb_out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
 
+  -- Counter signals
+
+  SIGNAL replace_cnt                 : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL nxt_stream_replaced_cnt_arr : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL i_stream_replaced_cnt_arr   : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
+
   -- Debug signals
   SIGNAL dbg_nof_streams            : NATURAL := g_nof_streams;
   SIGNAL dbg_bsn_latency_max        : NATURAL := g_bsn_latency_max;
@@ -233,6 +242,7 @@ BEGIN
     v := r;  -- state signals
     v.mm_sosi := func_dp_stream_reset_control(r.mm_sosi);
     v.wr_copi_arr := RESET_MEM_COPI_CTRL(r.wr_copi_arr);
+    v.replace_cnt_en := (OTHERS => '0');
 
     ----------------------------------------------------------------------------
     -- p_write_arr
@@ -297,11 +307,13 @@ BEGIN
         v.mm_sosi.channel := (OTHERS=>'0');
         FOR I IN 0 TO g_nof_streams-1 LOOP
           w.lost_data_flags_arr(I) := NOT v.filled_arr(I)(v.rd_blk_pointer);
+          v.replace_cnt_en(I) := w.lost_data_flags_arr(I);
           IF stream_en_arr(I) = '1' THEN  -- use MM bit at sop
             v.use_replacement_data(I) := w.lost_data_flags_arr(I);  -- enabled stream, so replace the data if the data was lost
             v.mm_sosi.channel(I) := w.lost_data_flags_arr(I);  -- enabled stream, so flag the data if the data was lost
           ELSE
             v.use_replacement_data(I) := '1';  -- disabled stream, so replace the data, but do not flag the data as lost
+            v.replace_cnt_en(I) := '1';
           END IF;
         END LOOP;
       END IF;
@@ -452,7 +464,35 @@ BEGIN
     dp_done <= dp_done_arr(0);   -- for viewing only
   END GENERATE;
 
+  ------------------------------------------------------------------------------
+  -- Replaced packets Counter
+  ------------------------------------------------------------------------------
+  gen_cnt_replace : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    u_cnt_replace : ENTITY common_lib.common_counter
+    GENERIC MAP (
+      g_width => c_word_w
+    )
+    PORT MAP (
+      rst     => dp_rst,
+      clk     => dp_clk,
+      cnt_clr => in_sosi_arr_p(0).sync,
+      cnt_en  => r.replace_cnt_en(I),
+      count   => replace_cnt(I)
+    );
+  END GENERATE;
+
+  nxt_stream_replaced_cnt_arr <= replace_cnt WHEN in_sosi_arr_p(0).sync = '1' ELSE i_stream_replaced_cnt_arr; 
 
+  p_cnt_replace : PROCESS(dp_rst, dp_clk)
+  BEGIN
+    IF dp_rst = '1' THEN
+      i_stream_replaced_cnt_arr <= (OTHERS => (OTHERS => '0'));
+    ELSIF rising_edge(dp_clk) THEN
+      i_stream_replaced_cnt_arr <= nxt_stream_replaced_cnt_arr;
+    END IF;
+  END PROCESS;
+  stream_replaced_cnt_arr <= i_stream_replaced_cnt_arr;
+  
   ------------------------------------------------------------------------------
   -- Pipelining
   ------------------------------------------------------------------------------
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 124fdb1e14..e85e606017 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -122,9 +122,12 @@ ARCHITECTURE rtl OF dp_fifo_fill_eop IS
   SIGNAL reg_rd_eop_cnt   : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); 
   SIGNAL wr_eop_done      : STD_LOGIC; 
   SIGNAL wr_eop_new       : STD_LOGIC; 
+  SIGNAL nxt_wr_eop_new   : STD_LOGIC; 
   SIGNAL rd_eop_new       : STD_LOGIC; 
   SIGNAL wr_eop_busy      : STD_LOGIC;
+  SIGNAL nxt_wr_eop_busy  : STD_LOGIC;
   SIGNAL wr_eop_cnt       : NATURAL := 0;
+  SIGNAL nxt_wr_eop_cnt   : NATURAL := 0;
   SIGNAL rd_eop_cnt       : NATURAL := 0;
 
   -- EOP count can be negative when a packet is sent out without having received the eop. This can be the case when g_fifo_fill has been reached.
@@ -215,52 +218,63 @@ BEGIN
   -- statements where g_use_dual_clock = FALSE / TRUE will never be active simultaneously as a GENERATE statement cannot have an ELSE statement.
   rd_eop_cnt <= TO_UINT(reg_rd_eop_cnt) WHEN g_use_dual_clock ELSE wr_eop_cnt;
 
-  p_eop_cnt: PROCESS(wr_clk, wr_rst)
+  p_eop_cnt_comb: PROCESS(wr_eop_cnt, wr_eop_new, wr_eop_busy, wr_eop_done, snk_in)
     VARIABLE v_wr_eop_cnt: NATURAL;
+    VARIABLE v_wr_eop_new: STD_LOGIC;
+    VARIABLE v_wr_eop_busy: STD_LOGIC;
   BEGIN
-    IF wr_rst='1' THEN
-      wr_eop_busy <= '0';
-      wr_eop_cnt <= 0;
-      wr_eop_new <= '0'; 
-    ELSIF rising_edge(wr_clk) THEN
-      -- We need to control in_new signal for common_reg_cross_domain. We can simply pulse in_new after in_done = '1'.
-      -- After we have send the wr_eop_cnt accross the clock domain by seting wr_eop_new, the wr_eop_cnt is reset to 0.
-      -- It is not possible to set in_new = snk_in.eop as there can be more snk_in.eop during the clock cross time necessary by common_reg_cross_domain.
-      IF g_use_dual_clock THEN 
-        v_wr_eop_cnt := wr_eop_cnt; 
-        
-        -- When done = 1, busy can be set to 0.
-        IF wr_eop_done = '1' THEN 
-          wr_eop_busy <= '0';
-        END IF;
-        -- If common_reg_cross_domain is not busy transfering the register we can initiate a new transfer by setting wr_eop_new.
-        IF wr_eop_busy = '0' THEN
-          wr_eop_busy <= '1';
-          wr_eop_new <= '1'; 
-        END IF; 
+    -- We need to control in_new signal for common_reg_cross_domain. We can simply pulse in_new after in_done = '1'.
+    -- After we have send the wr_eop_cnt accross the clock domain by seting wr_eop_new, the wr_eop_cnt is reset to 0.
+    -- It is not possible to set in_new = snk_in.eop as there can be more snk_in.eop during the clock cross time necessary by common_reg_cross_domain.
+    v_wr_eop_new := wr_eop_new;
+    v_wr_eop_busy := wr_eop_busy;
+    IF g_use_dual_clock THEN 
+      v_wr_eop_cnt := wr_eop_cnt; 
+      
+      -- When done = 1, busy can be set to 0.
+      IF wr_eop_done = '1' THEN 
+        v_wr_eop_busy := '0';
+      END IF;
+      -- If common_reg_cross_domain is not busy transfering the register we can initiate a new transfer by setting wr_eop_new.
+      IF wr_eop_busy = '0' THEN
+        v_wr_eop_busy := '1';
+        v_wr_eop_new := '1'; 
+      END IF; 
   
-        -- After we transfered wr_eop_cnt, we can reset it to 0.
-        IF wr_eop_new = '1' THEN
-          wr_eop_new <= '0';
-          v_wr_eop_cnt := 0;
-        END IF;
+      -- After we transfered wr_eop_cnt, we can reset it to 0.
+      IF wr_eop_new = '1' THEN
+        v_wr_eop_new := '0';
+        v_wr_eop_cnt := 0;
+      END IF;
   
-        -- Count incoming snk_in.eop
-        IF snk_in.eop = '1' THEN 
-          v_wr_eop_cnt := v_wr_eop_cnt + 1;
-        END IF;
-        wr_eop_cnt <= v_wr_eop_cnt;
-
-      -- No need to transfer eop counter across clock domains for single clock
-      ELSE 
-        wr_eop_busy <= '0'; -- Not used here, fix value to prevent inferred latch.
-        wr_eop_new  <= '0'; -- Not used here, fix value to prevent inferred latch.
-        IF snk_in.eop = '1' THEN
-          wr_eop_cnt <= 1; -- wr_eop_cnt can simply be set to 1 instead of counting as it is immidiatly processed due to having a single clock.
-        ELSE
-          wr_eop_cnt <= 0;
-        END IF; 
+      -- Count incoming snk_in.eop
+      IF snk_in.eop = '1' THEN 
+        v_wr_eop_cnt := v_wr_eop_cnt + 1;
       END IF;
+      nxt_wr_eop_cnt <= v_wr_eop_cnt;
+
+    -- No need to transfer eop counter across clock domains for single clock
+    ELSE 
+      IF snk_in.eop = '1' THEN
+        nxt_wr_eop_cnt <= 1; -- wr_eop_cnt can simply be set to 1 instead of counting as it is immidiatly processed due to having a single clock.
+      ELSE
+        nxt_wr_eop_cnt <= 0;
+      END IF; 
+    END IF;
+    nxt_wr_eop_new <= v_wr_eop_new;
+    nxt_wr_eop_busy <= v_wr_eop_busy;
+  END PROCESS; 
+
+  p_eop_cnt_clk: PROCESS(wr_clk, wr_rst)
+  BEGIN
+    IF wr_rst='1' THEN
+      wr_eop_cnt  <= 0;
+      wr_eop_busy <= '0';
+      wr_eop_new  <= '0'; 
+    ELSIF rising_edge(wr_clk) THEN
+      wr_eop_cnt  <= nxt_wr_eop_cnt;     
+      wr_eop_busy <= nxt_wr_eop_busy;     
+      wr_eop_new  <= nxt_wr_eop_new;     
     END IF;
   END PROCESS; 
 
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
index ba9a27ffd4..77d8f531a1 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
@@ -26,7 +26,8 @@
 --   * Define MM reg for input enable/disable control for input i:
 --
 --      wi    Bits  Access     Type   Name
---       i     [0]      RW  boolean   input_enable
+--     2*i     [0]      RW  boolean   input_enable
+--   2*i+1  [31:0]      RO  integer   replaced_pkt_cnt
 --
 --      where i = 0:g_nof_streams-1 and input_enable '1' is on, '0' is off
 --
@@ -104,10 +105,12 @@ ARCHITECTURE str OF mmp_dp_bsn_align_v2 IS
   --   dat_w     : NATURAL;
   --   nof_dat   : NATURAL;    -- optional, nof dat words <= 2**adr_w
   --   init_sl   : STD_LOGIC;  -- optional, init all dat words to std_logic '0', '1' or 'X'
-  CONSTANT c_mm_reg       : t_c_mem := (1, ceil_log2(g_nof_streams), 1, g_nof_streams, '0');
+  CONSTANT c_mm_reg       : t_c_mem := (1, ceil_log2(2*g_nof_streams), c_word_w, 2*g_nof_streams, '0');
 
-  SIGNAL reg_wr           : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS => '1');
-  SIGNAL stream_en_arr    : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+  SIGNAL reg_wr                  : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS => '1');
+  SIGNAL reg_rd                  : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL stream_en_arr           : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+  SIGNAL stream_replaced_cnt_arr : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);
 
   SIGNAL ref_sync         : STD_LOGIC;
   SIGNAL mon_out_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0);
@@ -139,10 +142,15 @@ BEGIN
     reg_wr_arr     => OPEN,
     reg_rd_arr     => OPEN,
     out_reg        => reg_wr,   -- readback via ST clock domain
-    in_reg         => reg_wr
+    in_reg         => reg_rd
   );
 
-  stream_en_arr <= reg_wr;
+  gen_reg : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    stream_en_arr(I)                             <= sl(reg_wr(2*I * c_word_w DOWNTO 2*I * c_word_w));
+    reg_rd(2*I * c_word_w DOWNTO 2*I * c_word_w) <=    reg_wr(2*I * c_word_w DOWNTO 2*I * c_word_w);
+    reg_rd((2*I + 2) * c_word_w -1 DOWNTO (2*I + 1) * c_word_w) <= stream_replaced_cnt_arr(I);
+  END GENERATE;
+
 
   -- Use local sync as reference sync input for the BSN monitors
   ref_sync <= in_sosi_arr(0).sync;
@@ -229,19 +237,20 @@ BEGIN
     g_rd_latency                 => g_rd_latency
   )
   PORT MAP (
-    dp_rst         => dp_rst,
-    dp_clk         => dp_clk,
-    node_index     => node_index,
+    dp_rst                  => dp_rst,
+    dp_clk                  => dp_clk,
+    node_index              => node_index,
     -- MM control
-    stream_en_arr  => stream_en_arr,
+    stream_en_arr           => stream_en_arr,
+    stream_replaced_cnt_arr => stream_replaced_cnt_arr,
     -- Streaming input
-    in_sosi_arr    => in_sosi_arr,
+    in_sosi_arr             => in_sosi_arr,
     -- Output via local MM in dp_clk domain
-    mm_sosi        => i_mm_sosi,
-    mm_copi        => mm_copi,
-    mm_cipo_arr    => mm_cipo_arr,
+    mm_sosi                 => i_mm_sosi,
+    mm_copi                 => mm_copi,
+    mm_cipo_arr             => mm_cipo_arr,
     -- Output via streaming DP interface, when g_use_mm_output = TRUE.
-    out_sosi_arr   => i_out_sosi_arr
+    out_sosi_arr            => i_out_sosi_arr
   );
 
 END str;
-- 
GitLab