diff --git a/applications/apertif/designs/apertif_unb1_fn_bf_emu/src/vhdl/apertif_unb1_fn_bf_emu.vhd b/applications/apertif/designs/apertif_unb1_fn_bf_emu/src/vhdl/apertif_unb1_fn_bf_emu.vhd index 8208a9e7dae5f7ae5282233a094c4d425e9beeec..ecaaa9d30c402506417432320fc50d7f2ff28b64 100644 --- a/applications/apertif/designs/apertif_unb1_fn_bf_emu/src/vhdl/apertif_unb1_fn_bf_emu.vhd +++ b/applications/apertif/designs/apertif_unb1_fn_bf_emu/src/vhdl/apertif_unb1_fn_bf_emu.vhd @@ -118,8 +118,6 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS SIGNAL dp_pps : STD_LOGIC; SIGNAL ddr_ref_rst : STD_LOGIC; SIGNAL sa_rst : STD_LOGIC; - SIGNAL ctrl_dp_rst : STD_LOGIC; - SIGNAL ctrl_dp_clk : STD_LOGIC; SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0); -- [2:0], so range 0-3 for FN and range 4-7 BN @@ -132,7 +130,7 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS CONSTANT c_bg_gapsize : NATURAL := 0; CONSTANT c_bg_blocks_per_sync : NATURAL := 781250; CONSTANT c_bg_ctrl : t_diag_block_gen := (sel_a_b(g_sim, '1', '0'), -- enable: On by default in simulation; MM enable required on hardware. - '0', -- enable_sync + sel_a_b(g_sim, '1', '0'), -- enable_sync TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w), TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w), TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w), @@ -447,8 +445,8 @@ BEGIN mm_locked => mm_locked, mm_rst => mm_rst, - dp_rst => ctrl_dp_rst, - dp_clk => ctrl_dp_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, dp_pps => dp_pps, dp_rst_in => dp_rst, dp_clk_in => dp_clk,