diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd index 30edfe8dc9e4010bca8fa7c5190940b7266eaaac..b0d8e97ffabb25bf26f6f12596f688048f94ca6f 100644 --- a/libraries/base/common/src/vhdl/common_pkg.vhd +++ b/libraries/base/common/src/vhdl/common_pkg.vhd @@ -99,7 +99,8 @@ PACKAGE common_pkg IS -- DSP CONSTANT c_dsp_mult_w : NATURAL := 18; -- Width of the embedded multipliers in Stratix IV (and Arria 10 for 2 multipliers per DSP block) - CONSTANT c_dsp_mult_arria10_w : NATURAL := 27; -- Width of the embedded multipliers in Arria 10 + CONSTANT c_dsp_mult_18_w : NATURAL := 18; -- Width of the embedded multipliers in Stratix IV (and Arria 10 for 2 multipliers per DSP block) + CONSTANT c_dsp_mult_27_w : NATURAL := 27; -- Width of the embedded multipliers in Arria 10 -- TYPE DECLARATIONS -------------------------------------------------------- TYPE t_boolean_arr IS ARRAY (INTEGER RANGE <>) OF BOOLEAN; -- INTEGER left index starts default at -2**31 diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd index ab08dfeb93f79b36b15f944a828ccdf4555224a9..ead344fece9b262abc3641dabb2795592cf2041c 100644 --- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd +++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd @@ -70,7 +70,7 @@ architecture str of rTwoWMul is constant c_mult_extra_lat : natural := sel_a_b(c_lat>3, c_lat-3, 0); -- remaining extra pipelining in logic constant c_mult_output_lat : natural := sel_a_b(c_lat>0, 1, 0) + c_mult_extra_lat; -- first priority use DSP pipeline output constant c_mult_lat : natural := c_mult_input_lat + c_mult_product_lat + c_mult_adder_lat + c_mult_output_lat; - constant c_max_dsp_mult_w : natural := sel_a_b(g_technology = c_tech_stratixiv, c_dsp_mult_w, c_dsp_mult_arria10_w); + constant c_max_dsp_mult_w : natural := sel_a_b(g_technology = c_tech_stratixiv, c_dsp_mult_18_w, c_dsp_mult_27_w); -- Total input to output latency constant c_total_lat : natural := c_mult_lat + c_round_lat;