diff --git a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
index bf0ff81186028658073e7f1dec473202a5112d77..2f5450486e5aebc985d5f10945a912fa885e284c 100644
--- a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
+++ b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
@@ -125,7 +125,7 @@ BEGIN
     GENERIC MAP (
       g_technology     => g_technology,
       g_ram            => c_common_ram_crw_crw_ram,
---      g_init_file      => g_weights_file & "_" & NATURAL'IMAGE(i) & ".hex",    
+      g_init_file      => g_weights_file & "_" & NATURAL'IMAGE(i) & ".hex",    
       g_true_dual_port => FALSE --NOT(g_weights_write_only)
     )
     PORT MAP (
@@ -149,8 +149,8 @@ BEGIN
     );  
 
     -- RAM output rewired to SOSI array
-    common_ram_crw_crw_src_out_arr(i).re(g_weights_w-1 DOWNTO 0) <= common_ram_crw_crw_rd_dat_b_arr(i)(  g_weights_w-1 DOWNTO 0);
-    common_ram_crw_crw_src_out_arr(i).im(g_weights_w-1 DOWNTO 0) <= common_ram_crw_crw_rd_dat_b_arr(i)(2*g_weights_w-1 DOWNTO g_weights_w);
+    common_ram_crw_crw_src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_ram_crw_crw_rd_dat_b_arr(i)(  g_weights_w-1 DOWNTO 0));
+    common_ram_crw_crw_src_out_arr(i).im <= RESIZE_DP_DSP_DATA(common_ram_crw_crw_rd_dat_b_arr(i)(2*g_weights_w-1 DOWNTO g_weights_w));
     common_ram_crw_crw_src_out_arr(i).valid <= common_ram_crw_crw_rd_val_b_arr(i);
 
   END GENERATE; 
@@ -180,7 +180,7 @@ BEGIN
     rst          => dp_rst,
     clk          => dp_clk,
 
-    snk_in_arr   => common_ram_crw_crw_src_out_arr, 
+    snk_in_arr   => snk_in_arr, 
 
     src_out_arr  => dp_pipeline_arr_src_out_arr
   );