From 8a27e9aa329592ac63fac91340f87032218b5240 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 8 Feb 2024 15:32:51 +0100
Subject: [PATCH] Correct jesd_ctrl_mosi interface connection.
---
.../sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd | 11 ++---------
.../sdp/src/vhdl/sdp_adc_input_and_timing.vhd | 4 ----
2 files changed, 2 insertions(+), 13 deletions(-)
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 313614906f..16b7b5fedf 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -110,7 +110,8 @@ entity node_sdp_adc_input_and_timing is
end node_sdp_adc_input_and_timing;
architecture str of node_sdp_adc_input_and_timing is
- -- Use jesd v1 with tech_jesd204b and FIFO in ait or v2 with FIFO in tech_jesd204b_v2
+ -- Use tech_jesd204b with tech_jesd204b and FIFO in ait, or
+ -- use tech_jesd204b_v2 with FIFO in tech_jesd204b_v2
constant c_use_tech_jesd204b_v2 : boolean := false;
-- Waveform Generator
@@ -340,10 +341,6 @@ begin
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- -- JESD control
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
-- Streaming data output
out_sosi_arr => st_sosi_arr,
rx_bsn_source_restart => rx_bsn_source_restart,
@@ -463,10 +460,6 @@ begin
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- -- JESD control
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
-- Streaming data output
out_sosi_arr => out_sosi_arr,
rx_bsn_source_restart => dp_bsn_source_restart,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
index 8eaf5365b9..bc44dc392c 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
@@ -92,10 +92,6 @@ entity sdp_adc_input_and_timing is
reg_aduh_monitor_mosi : in t_mem_mosi;
reg_aduh_monitor_miso : out t_mem_miso;
- -- JESD control
- jesd_ctrl_mosi : in t_mem_mosi;
- jesd_ctrl_miso : out t_mem_miso;
-
-- Streaming data output
out_sosi_arr : out t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0);
rx_bsn_source_restart : out std_logic; -- for dp_sync_recover in WPFB
--
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