diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index 1a4692cfdacc5e2884df06c099ee673a4e635503..70a865f655e323c16564b00183f60a6f03cbad75 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -52,6 +52,7 @@ ENTITY ctrl_unb2_board IS
     g_base_ip        : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
     g_mm_clk_freq    : NATURAL := c_unb2_board_mm_clk_freq_125M;
     g_eth_clk_freq   : NATURAL := c_unb2_board_eth_clk_freq_125M;
+    g_tse_clk_buf    : BOOLEAN := FALSE;
     
     ----------------------------------------------------------------------------
     -- External CLK
@@ -671,16 +672,23 @@ BEGIN
   -- Ethernet 1GbE
   ------------------------------------------------------------------------------
 
-  -- Separate clkbuf for the 1GbE tse_clk:
-  u_tse_clk_buf : ENTITY tech_clkbuf_lib.tech_clkbuf
-  GENERIC MAP (
-    g_technology   => g_technology,
-    g_clock_net    => "GLOBAL"
-  )
-  PORT MAP (
-    inclk  => i_xo_ethclk,
-    outclk => i_tse_clk
-  );
+  gen_tse_clk_buf: IF g_tse_clk_buf=TRUE GENERATE
+    -- Separate clkbuf for the 1GbE tse_clk:
+    u_tse_clk_buf : ENTITY tech_clkbuf_lib.tech_clkbuf
+    GENERIC MAP (
+      g_technology   => g_technology,
+      g_clock_net    => "GLOBAL"
+    )
+    PORT MAP (
+      inclk  => i_xo_ethclk,
+      outclk => i_tse_clk
+    );
+  END GENERATE;
+
+  gen_tse_no_clk_buf: IF g_tse_clk_buf=FALSE GENERATE
+      i_tse_clk <= i_xo_ethclk;
+  END GENERATE;
+
   
 
   gen_same_clk: IF g_udp_offload=TRUE GENERATE
@@ -715,8 +723,7 @@ BEGIN
       -- Clocks and reset
       mm_rst            => eth1g_mm_rst, -- use reset from QSYS
       mm_clk            => i_mm_clk,     -- use mm_clk direct
-      --eth_clk           => i_tse_clk,    -- 125 MHz clock
-      eth_clk           => i_xo_ethclk,    -- 125 MHz clock
+      eth_clk           => i_tse_clk,    -- 125 MHz clock
       st_rst            => eth1g_st_rst,
       st_clk            => eth1g_st_clk,