diff --git a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
index f4cec63c6bf137390fbe6e2d70a06749a641936b..43a23ca099b31cba38a8ceb60aaf2b0915065a5d 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
+++ b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
@@ -117,7 +117,7 @@
{
datum baseAddress
{
- value = "12752";
+ value = "12760";
type = "String";
}
}
@@ -154,7 +154,7 @@
{
datum _sortIndex
{
- value = "11";
+ value = "12";
type = "int";
}
}
@@ -162,7 +162,7 @@
{
datum baseAddress
{
- value = "12744";
+ value = "12752";
type = "String";
}
}
@@ -170,7 +170,7 @@
{
datum _sortIndex
{
- value = "10";
+ value = "11";
type = "int";
}
}
@@ -210,7 +210,7 @@
{
datum _sortIndex
{
- value = "34";
+ value = "35";
type = "int";
}
}
@@ -226,7 +226,7 @@
{
datum _sortIndex
{
- value = "33";
+ value = "34";
type = "int";
}
}
@@ -242,7 +242,7 @@
{
datum _sortIndex
{
- value = "30";
+ value = "31";
type = "int";
}
}
@@ -258,7 +258,7 @@
{
datum _sortIndex
{
- value = "29";
+ value = "30";
type = "int";
}
}
@@ -274,7 +274,7 @@
{
datum _sortIndex
{
- value = "47";
+ value = "48";
type = "int";
}
}
@@ -290,7 +290,7 @@
{
datum _sortIndex
{
- value = "48";
+ value = "49";
type = "int";
}
}
@@ -306,7 +306,7 @@
{
datum _sortIndex
{
- value = "26";
+ value = "27";
type = "int";
}
}
@@ -322,7 +322,7 @@
{
datum _sortIndex
{
- value = "25";
+ value = "26";
type = "int";
}
}
@@ -338,7 +338,7 @@
{
datum _sortIndex
{
- value = "32";
+ value = "33";
type = "int";
}
}
@@ -354,7 +354,7 @@
{
datum _sortIndex
{
- value = "31";
+ value = "32";
type = "int";
}
}
@@ -370,7 +370,7 @@
{
datum _sortIndex
{
- value = "28";
+ value = "29";
type = "int";
}
}
@@ -386,7 +386,7 @@
{
datum _sortIndex
{
- value = "27";
+ value = "28";
type = "int";
}
}
@@ -402,7 +402,7 @@
{
datum _sortIndex
{
- value = "45";
+ value = "46";
type = "int";
}
}
@@ -418,7 +418,7 @@
{
datum _sortIndex
{
- value = "46";
+ value = "47";
type = "int";
}
}
@@ -434,7 +434,7 @@
{
datum _sortIndex
{
- value = "38";
+ value = "39";
type = "int";
}
}
@@ -450,7 +450,7 @@
{
datum _sortIndex
{
- value = "36";
+ value = "37";
type = "int";
}
}
@@ -466,7 +466,7 @@
{
datum _sortIndex
{
- value = "43";
+ value = "44";
type = "int";
}
}
@@ -482,7 +482,7 @@
{
datum _sortIndex
{
- value = "44";
+ value = "45";
type = "int";
}
}
@@ -498,7 +498,7 @@
{
datum _sortIndex
{
- value = "37";
+ value = "38";
type = "int";
}
}
@@ -514,7 +514,7 @@
{
datum _sortIndex
{
- value = "35";
+ value = "36";
type = "int";
}
}
@@ -530,7 +530,7 @@
{
datum _sortIndex
{
- value = "41";
+ value = "42";
type = "int";
}
}
@@ -546,7 +546,7 @@
{
datum _sortIndex
{
- value = "42";
+ value = "43";
type = "int";
}
}
@@ -562,7 +562,7 @@
{
datum _sortIndex
{
- value = "15";
+ value = "16";
type = "int";
}
}
@@ -570,7 +570,7 @@
{
datum baseAddress
{
- value = "12736";
+ value = "12744";
type = "String";
}
}
@@ -578,7 +578,7 @@
{
datum _sortIndex
{
- value = "16";
+ value = "17";
type = "int";
}
}
@@ -586,7 +586,7 @@
{
datum baseAddress
{
- value = "12728";
+ value = "12736";
type = "String";
}
}
@@ -594,7 +594,7 @@
{
datum _sortIndex
{
- value = "14";
+ value = "15";
type = "int";
}
}
@@ -610,7 +610,7 @@
{
datum _sortIndex
{
- value = "23";
+ value = "24";
type = "int";
}
}
@@ -626,7 +626,7 @@
{
datum _sortIndex
{
- value = "24";
+ value = "25";
type = "int";
}
}
@@ -642,7 +642,7 @@
{
datum _sortIndex
{
- value = "22";
+ value = "23";
type = "int";
}
}
@@ -654,11 +654,27 @@
type = "String";
}
}
+ element reg_fpga_sens
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ }
+ element reg_fpga_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "12296";
+ type = "String";
+ }
+ }
element reg_io_ddr_MB_I
{
datum _sortIndex
{
- value = "39";
+ value = "40";
type = "int";
}
}
@@ -674,7 +690,7 @@
{
datum _sortIndex
{
- value = "40";
+ value = "41";
type = "int";
}
}
@@ -690,7 +706,7 @@
{
datum _sortIndex
{
- value = "17";
+ value = "18";
type = "int";
}
}
@@ -698,7 +714,7 @@
{
datum baseAddress
{
- value = "12720";
+ value = "12728";
type = "String";
}
}
@@ -706,7 +722,7 @@
{
datum _sortIndex
{
- value = "18";
+ value = "19";
type = "int";
}
}
@@ -714,7 +730,7 @@
{
datum baseAddress
{
- value = "12296";
+ value = "12720";
type = "String";
}
}
@@ -722,7 +738,7 @@
{
datum _sortIndex
{
- value = "13";
+ value = "14";
type = "int";
}
}
@@ -738,7 +754,7 @@
{
datum _sortIndex
{
- value = "20";
+ value = "21";
type = "int";
}
}
@@ -754,7 +770,7 @@
{
datum _sortIndex
{
- value = "21";
+ value = "22";
type = "int";
}
}
@@ -770,7 +786,7 @@
{
datum _sortIndex
{
- value = "19";
+ value = "20";
type = "int";
}
}
@@ -802,7 +818,7 @@
{
datum _sortIndex
{
- value = "12";
+ value = "13";
type = "int";
}
}
@@ -823,7 +839,7 @@
{
datum _sortIndex
{
- value = "9";
+ value = "10";
type = "int";
}
}
@@ -2111,6 +2127,41 @@
internal="reg_eth10g_qsfp_ring.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_fpga_sens_address"
+ internal="reg_fpga_sens.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_sens_clk"
+ internal="reg_fpga_sens.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_sens_read"
+ internal="reg_fpga_sens.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_sens_readdata"
+ internal="reg_fpga_sens.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_sens_reset"
+ internal="reg_fpga_sens.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_sens_write"
+ internal="reg_fpga_sens.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_sens_writedata"
+ internal="reg_fpga_sens.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_io_ddr_mb_i_address"
internal="reg_io_ddr_MB_I.address"
@@ -2528,7 +2579,7 @@
<parameter name="dataAddrWidth" value="23" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x80' end='0x100' /><slave name='reg_eth10g_back1.mem' start='0x100' end='0x200' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' /><slave name='reg_eth10g_back0.mem' start='0x400' end='0x500' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x500' end='0x580' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x580' end='0x600' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x600' end='0x680' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x680' end='0x700' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x700' end='0x780' /><slave name='avs_eth_1.mms_reg' start='0x780' end='0x7C0' /><slave name='avs_eth_0.mms_reg' start='0x7C0' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3040' end='0x3080' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x3080' end='0x30A0' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x30A0' end='0x30C0' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x30C0' end='0x30E0' /><slave name='reg_diag_bg_10gbe.mem' start='0x30E0' end='0x3100' /><slave name='reg_diag_bg_1gbe.mem' start='0x3100' end='0x3120' /><slave name='reg_epcs.mem' start='0x3120' end='0x3140' /><slave name='reg_remu.mem' start='0x3140' end='0x3160' /><slave name='reg_unb_sens.mem' start='0x3160' end='0x3180' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x3180' end='0x3190' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x3190' end='0x31A0' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x31A0' end='0x31B0' /><slave name='reg_mmdp_ctrl.mem' start='0x31B0' end='0x31B8' /><slave name='reg_dpmm_data.mem' start='0x31B8' end='0x31C0' /><slave name='reg_dpmm_ctrl.mem' start='0x31C0' end='0x31C8' /><slave name='pio_pps.mem' start='0x31C8' end='0x31D0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x31D0' end='0x31D8' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0x4000' end='0x6000' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x6000' end='0x8000' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0x8000' end='0xA000' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xC000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xC000' end='0xE000' /><slave name='avs_eth_0.mms_tse' start='0xE000' end='0xF000' /><slave name='avs_eth_1.mms_ram' start='0xF000' end='0x10000' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x80' end='0x100' /><slave name='reg_eth10g_back1.mem' start='0x100' end='0x200' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' /><slave name='reg_eth10g_back0.mem' start='0x400' end='0x500' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x500' end='0x580' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x580' end='0x600' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x600' end='0x680' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x680' end='0x700' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x700' end='0x780' /><slave name='avs_eth_1.mms_reg' start='0x780' end='0x7C0' /><slave name='avs_eth_0.mms_reg' start='0x7C0' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='reg_fpga_sens.mem' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3040' end='0x3080' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x3080' end='0x30A0' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x30A0' end='0x30C0' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x30C0' end='0x30E0' /><slave name='reg_diag_bg_10gbe.mem' start='0x30E0' end='0x3100' /><slave name='reg_diag_bg_1gbe.mem' start='0x3100' end='0x3120' /><slave name='reg_epcs.mem' start='0x3120' end='0x3140' /><slave name='reg_remu.mem' start='0x3140' end='0x3160' /><slave name='reg_unb_sens.mem' start='0x3160' end='0x3180' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x3180' end='0x3190' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x3190' end='0x31A0' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x31A0' end='0x31B0' /><slave name='reg_mmdp_data.mem' start='0x31B0' end='0x31B8' /><slave name='reg_mmdp_ctrl.mem' start='0x31B8' end='0x31C0' /><slave name='reg_dpmm_data.mem' start='0x31C0' end='0x31C8' /><slave name='reg_dpmm_ctrl.mem' start='0x31C8' end='0x31D0' /><slave name='pio_pps.mem' start='0x31D0' end='0x31D8' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x31D8' end='0x31E0' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0x4000' end='0x6000' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x6000' end='0x8000' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0x8000' end='0xA000' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xC000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xC000' end='0xE000' /><slave name='avs_eth_0.mms_tse' start='0xE000' end='0xF000' /><slave name='avs_eth_1.mms_ram' start='0xF000' end='0x10000' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@@ -2996,6 +3047,11 @@
<parameter name="g_adr_w" value="7" />
<parameter name="g_dat_w" value="32" />
</module>
+ <module name="reg_fpga_sens" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
<module name="reg_io_ddr_MB_I" kind="avs_common_mm" version="1.0" enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
<parameter name="g_adr_w" value="16" />
@@ -3085,7 +3141,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31d0" />
+ <parameter name="baseAddress" value="0x31d8" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3130,7 +3186,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31c8" />
+ <parameter name="baseAddress" value="0x31d0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3166,7 +3222,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31c0" />
+ <parameter name="baseAddress" value="0x31c8" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3175,7 +3231,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31b8" />
+ <parameter name="baseAddress" value="0x31c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3184,7 +3240,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31b0" />
+ <parameter name="baseAddress" value="0x31b8" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3193,7 +3249,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3008" />
+ <parameter name="baseAddress" value="0x31b0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3466,6 +3522,15 @@
<parameter name="baseAddress" value="0x0100" />
<parameter name="defaultConnection" value="false" />
</connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_fpga_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3008" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
kind="avalon"
version="15.0"
@@ -3765,6 +3830,11 @@
version="15.0"
start="clk_0.clk"
end="reg_eth10g_back1.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_fpga_sens.system" />
<connection
kind="interrupt"
version="15.0"
@@ -4025,6 +4095,11 @@
version="15.0"
start="clk_0.clk_reset"
end="reg_eth10g_back1.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_fpga_sens.system_reset" />
<connection
kind="reset"
version="15.0"
@@ -4265,6 +4340,11 @@
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_eth10g_back1.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_fpga_sens.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 33573db31f269fa327902c0d3ea331dc8bc39b44..a72604547b2d19f61d5fa893213e225973cc4ec3 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -29,7 +29,7 @@ PACKAGE qsys_unb2_test_pkg IS
-- $RADIOHDL/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
-----------------------------------------------------------------------------
- component qsys_unb2_test is
+ component qsys_unb2_test is
port (
avs_eth_0_clk_export : out std_logic; -- export
avs_eth_0_irq_export : in std_logic := 'X'; -- export
@@ -260,6 +260,34 @@ PACKAGE qsys_unb2_test_pkg IS
reg_epcs_reset_export : out std_logic; -- export
reg_epcs_write_export : out std_logic; -- export
reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back0_clk_export : out std_logic; -- export
+ reg_eth10g_back0_read_export : out std_logic; -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back0_reset_export : out std_logic; -- export
+ reg_eth10g_back0_write_export : out std_logic; -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back1_clk_export : out std_logic; -- export
+ reg_eth10g_back1_read_export : out std_logic; -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back1_reset_export : out std_logic; -- export
+ reg_eth10g_back1_write_export : out std_logic; -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_sens_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_fpga_sens_clk_export : out std_logic; -- export
+ reg_fpga_sens_read_export : out std_logic; -- export
+ reg_fpga_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_sens_reset_export : out std_logic; -- export
+ reg_fpga_sens_write_export : out std_logic; -- export
+ reg_fpga_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
reg_io_ddr_mb_i_clk_export : out std_logic; -- export
reg_io_ddr_mb_i_read_export : out std_logic; -- export
@@ -340,28 +368,7 @@ PACKAGE qsys_unb2_test_pkg IS
rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
rom_system_info_reset_export : out std_logic; -- export
rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_reset_export : out std_logic -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_unb2_test;