From 880633c0fb963cee942c5e9ecedb5c7c8262e2bd Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 17 Dec 2014 14:30:36 +0000
Subject: [PATCH] Added DDR3 IP technology wrapper for straticiv using UniPhy.
---
libraries/technology/ddr3/hdllib.cfg | 6 +-
libraries/technology/ddr3/tech_ddr3.vhd | 75 +++++++
.../technology/ddr3/tech_ddr3_stratixiv.vhd | 186 ++++++++++++++++++
3 files changed, 264 insertions(+), 3 deletions(-)
create mode 100644 libraries/technology/ddr3/tech_ddr3.vhd
create mode 100644 libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
diff --git a/libraries/technology/ddr3/hdllib.cfg b/libraries/technology/ddr3/hdllib.cfg
index 60839ec90a..f72a2e586c 100644
--- a/libraries/technology/ddr3/hdllib.cfg
+++ b/libraries/technology/ddr3/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_ddr3
hdl_library_clause_name = tech_ddr3_lib
-hdl_lib_uses = technology ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave
+hdl_lib_uses = technology tech_ddr ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave common
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
@@ -8,8 +8,8 @@ build_dir_synth = $HDL_BUILD_DIR
synth_files =
tech_ddr3_component_pkg.vhd
- #tech_ddr3_stratixiv.vhd
- #tech_ddr3.vhd
+ tech_ddr3_stratixiv.vhd
+ tech_ddr3.vhd
test_bench_files =
diff --git a/libraries/technology/ddr3/tech_ddr3.vhd b/libraries/technology/ddr3/tech_ddr3.vhd
new file mode 100644
index 0000000000..8c38c491fe
--- /dev/null
+++ b/libraries/technology/ddr3/tech_ddr3.vhd
@@ -0,0 +1,75 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, technology_lib, tech_ddr_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+
+ENTITY tech_ddr3 IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ g_master : BOOLEAN := TRUE;
+ g_ddr_phy : t_c_tech_ddr_phy;
+ g_ddr_ctlr : t_c_tech_ddr_ctlr
+ );
+ PORT (
+ -- PLL reference clock
+ ctlr_ref_clk : IN STD_LOGIC;
+ ctlr_ref_rst : IN STD_LOGIC;
+
+ -- Controller user interface
+ ctlr_gen_clk : OUT STD_LOGIC;
+ ctlr_gen_rst : OUT STD_LOGIC;
+ ctlr_gen_clk_2x : OUT STD_LOGIC;
+ ctlr_gen_rst_2x : OUT STD_LOGIC;
+
+ ctlr_init_done : OUT STD_LOGIC;
+
+ ctrl_mosi : IN t_tech_ddr_mosi;
+ ctrl_miso : OUT t_tech_ddr_miso;
+
+ -- PHY interface
+ phy_in : IN t_tech_ddr_phy_in;
+ phy_io : INOUT t_tech_ddr_phy_io;
+ phy_ou : OUT t_tech_ddr_phy_ou
+ );
+END tech_ddr3;
+
+
+ARCHITECTURE str OF tech_ddr3 IS
+
+BEGIN
+
+ gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ u0 : ENTITY work.tech_ddr3_stratixiv
+ GENERIC MAP (g_master, g_ddr_phy, g_ddr_ctlr)
+ PORT MAP (ctlr_ref_clk, ctlr_ref_rst,
+ ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
+ ctlr_init_done,
+ ctrl_mosi, ctrl_miso,
+ phy_in, phy_io, phy_ou);
+ END GENERATE;
+
+END str;
+
diff --git a/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd b/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
new file mode 100644
index 0000000000..3b847387c8
--- /dev/null
+++ b/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
@@ -0,0 +1,186 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_stratixiv_ddr3_uphy_4g_800_master_lib;
+LIBRARY ip_stratixiv_ddr3_uphy_4g_800_slave_lib;
+
+LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE work.tech_ddr3_component_pkg.ALL;
+
+ENTITY tech_ddr3_stratixiv IS
+ GENERIC (
+ g_master : BOOLEAN := TRUE;
+ g_ddr_phy : t_c_tech_ddr_phy;
+ g_ddr_ctlr : t_c_tech_ddr_ctlr
+ );
+ PORT (
+ -- PLL reference clock
+ ctlr_ref_clk : IN STD_LOGIC;
+ ctlr_ref_rst : IN STD_LOGIC;
+
+ -- Controller user interface
+ ctlr_gen_clk : OUT STD_LOGIC;
+ ctlr_gen_rst : OUT STD_LOGIC;
+ ctlr_gen_clk_2x : OUT STD_LOGIC;
+ ctlr_gen_rst_2x : OUT STD_LOGIC;
+
+ ctlr_init_done : OUT STD_LOGIC;
+
+ ctrl_mosi : IN t_tech_ddr_mosi;
+ ctrl_miso : OUT t_tech_ddr_miso;
+
+ -- PHY interface
+ phy_in : IN t_tech_ddr_phy_in;
+ phy_io : INOUT t_tech_ddr_phy_io;
+ phy_ou : OUT t_tech_ddr_phy_ou
+ );
+END tech_ddr3_stratixiv;
+
+
+ARCHITECTURE str OF tech_ddr3_stratixiv IS
+
+ SIGNAL i_ctlr_gen_rst : STD_LOGIC;
+ SIGNAL i_ctlr_gen_clk_2x : STD_LOGIC;
+
+BEGIN
+
+ gen_master : IF g_master=TRUE GENERATE
+ u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master
+ PORT MAP (
+ pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
+ global_reset_n => ctlr_ref_rst, -- global_reset.reset_n
+ soft_reset_n => '0', -- soft_reset.reset_n
+ afi_clk => ctlr_gen_clk, -- afi_clk.clk
+ afi_half_clk => OPEN, -- afi_half_clk.clk
+ afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n
+ mem_a => phy_ou.a(g_ddr_phy.a_w-1 DOWNTO 0), -- memory.mem_a
+ mem_ba => phy_ou.ba(g_ddr_phy.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_ck => phy_io.clk(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_ck
+ mem_ck_n => phy_io.clk_n(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_cke => phy_ou.cke(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_ddr_phy.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_dm => phy_ou.dm(g_ddr_phy.dm_w-1 DOWNTO 0), -- .mem_dm
+ mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
+ mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
+ mem_we_n => phy_ou.we_n, -- .mem_we_n
+ mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
+ mem_dq => phy_io.dq(g_ddr_phy.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dqs => phy_io.dqs(g_ddr_phy.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_ddr_phy.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_odt => phy_ou.odt(g_ddr_phy.cs_w-1 DOWNTO 0), -- .mem_odt
+ avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
+ avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
+ avl_addr => ctrl_mosi.address(g_ddr_ctlr.address_w-1 DOWNTO 0), -- .address
+ avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
+ avl_rdata => ctrl_miso.rddata(g_ddr_ctlr.data_w-1 DOWNTO 0), -- .readdata
+ avl_wdata => ctrl_mosi.wrdata(g_ddr_ctlr.data_w-1 DOWNTO 0), -- .writedata
+ avl_be => (OTHERS=>'1'), -- .byteenable
+ avl_read_req => ctrl_mosi.rd, -- .read
+ avl_write_req => ctrl_mosi.wr, -- .write
+ avl_size => ctrl_mosi.burstsize(g_ddr_ctlr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ local_init_done => ctlr_init_done, -- status.local_init_done
+ local_cal_success => OPEN, -- .local_cal_success
+ local_cal_fail => OPEN, -- .local_cal_fail
+ oct_rdn => phy_in.oct_rdn, -- oct.rdn
+ oct_rup => phy_in.oct_rup, -- .rup
+ seriesterminationcontrol => phy_ou.seriesterminationcontrol(g_ddr_phy.terminationcontrol_w-1 DOWNTO 0), -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol => phy_ou.parallelterminationcontrol(g_ddr_phy.terminationcontrol_w-1 DOWNTO 0), -- .parallelterminationcontrol
+ pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
+ pll_write_clk => OPEN, -- .pll_write_clk
+ pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
+ pll_locked => OPEN, -- .pll_locked
+ pll_avl_clk => OPEN, -- .pll_avl_clk
+ pll_config_clk => OPEN, -- .pll_config_clk
+ dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
+ );
+ END GENERATE;
+
+ gen_slave : IF g_master=FALSE GENERATE
+ u_ip_stratixiv_ddr3_uphy_4g_800_slave : ip_stratixiv_ddr3_uphy_4g_800_slave
+ PORT MAP (
+ pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
+ global_reset_n => ctlr_ref_rst, -- global_reset.reset_n
+ soft_reset_n => '0', -- soft_reset.reset_n
+ afi_clk => ctlr_gen_clk, -- afi_clk.clk
+ afi_half_clk => OPEN, -- afi_half_clk.clk
+ afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n
+ mem_a => phy_ou.a(g_ddr_phy.a_w-1 DOWNTO 0), -- memory.mem_a
+ mem_ba => phy_ou.ba(g_ddr_phy.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_ck => phy_io.clk(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_ck
+ mem_ck_n => phy_io.clk_n(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_cke => phy_ou.cke(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_ddr_phy.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_dm => phy_ou.dm(g_ddr_phy.dm_w-1 DOWNTO 0), -- .mem_dm
+ mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
+ mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
+ mem_we_n => phy_ou.we_n, -- .mem_we_n
+ mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
+ mem_dq => phy_io.dq(g_ddr_phy.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dqs => phy_io.dqs(g_ddr_phy.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_ddr_phy.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_odt => phy_ou.odt(g_ddr_phy.cs_w-1 DOWNTO 0), -- .mem_odt
+ avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
+ avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
+ avl_addr => ctrl_mosi.address(g_ddr_ctlr.address_w-1 DOWNTO 0), -- .address
+ avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
+ avl_rdata => ctrl_miso.rddata(g_ddr_ctlr.data_w-1 DOWNTO 0), -- .readdata
+ avl_wdata => ctrl_mosi.wrdata(g_ddr_ctlr.data_w-1 DOWNTO 0), -- .writedata
+ avl_be => (OTHERS=>'1'), -- .byteenable
+ avl_read_req => ctrl_mosi.rd, -- .read
+ avl_write_req => ctrl_mosi.wr, -- .write
+ avl_size => ctrl_mosi.burstsize(g_ddr_ctlr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ local_init_done => ctlr_init_done, -- status.local_init_done
+ local_cal_success => OPEN, -- .local_cal_success
+ local_cal_fail => OPEN, -- .local_cal_fail
+ seriesterminationcontrol => phy_in.seriesterminationcontrol(g_ddr_phy.terminationcontrol_w-1 DOWNTO 0), -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol => phy_in.parallelterminationcontrol(g_ddr_phy.terminationcontrol_w-1 DOWNTO 0), -- .parallelterminationcontrol
+ pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
+ pll_write_clk => OPEN, -- .pll_write_clk
+ pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
+ pll_locked => OPEN, -- .pll_locked
+ pll_avl_clk => OPEN, -- .pll_avl_clk
+ pll_config_clk => OPEN, -- .pll_config_clk
+ dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
+ );
+ END GENERATE;
+
+ ctlr_gen_rst <= i_ctlr_gen_rst;
+ ctlr_gen_clk_2x <= i_ctlr_gen_clk_2x;
+
+ u_async_ctlr_gen_rst_2x: ENTITY common_lib.common_async
+ GENERIC MAP(
+ g_rst_level => '0'
+ )
+ PORT MAP(
+ rst => ctlr_ref_rst,
+ clk => i_ctlr_gen_clk_2x,
+ din => i_ctlr_gen_rst,
+ dout => ctlr_gen_rst_2x
+ );
+
+END str;
--
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