From 879aba4642bc6a8c738a6753cdabac1930c65e6f Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 12 May 2016 10:59:05 +0000
Subject: [PATCH] Adapt tb_end for regresion test.
---
.../tb/vhdl/tb_tb_tr_nonbonded.vhd | 21 +++++++++++++++----
.../tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd | 12 ++++++++++-
.../io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd | 6 +++++-
3 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
index 23ea1ca296..01e642e948 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
@@ -36,13 +36,26 @@ END tb_tb_tr_nonbonded;
ARCHITECTURE tb OF tb_tb_tr_nonbonded IS
+ CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ SIGNAL tb_end : STD_LOGIC := '0';
BEGIN
- -- g_data_w : NATURAL := 32;
- -- g_sim_level : NATURAL := 0
+ -- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ -- g_data_w : NATURAL := 32;
+ -- g_sim_level : NATURAL := 1
- u_tech : ENTITY work.tb_tr_nonbonded GENERIC MAP (32, 0);
- u_sim : ENTITY work.tb_tr_nonbonded GENERIC MAP (32, 1);
+ u_tech : ENTITY work.tb_tr_nonbonded GENERIC MAP (FALSE, 32, 0) PORT MAP (tb_end_vec(0));
+ u_sim : ENTITY work.tb_tr_nonbonded GENERIC MAP (FALSE, 32, 1) PORT MAP (tb_end_vec(1));
+ tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT UNTIL tb_end='1';
+ WAIT FOR 1 ns;
+ REPORT "Multi tb simulation finished." SEVERITY FAILURE;
+ WAIT;
+ END PROCESS;
END tb;
diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
index 8969b9a7ff..dd8942fb07 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
@@ -71,9 +71,13 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY tb_tr_nonbonded IS
GENERIC (
+ g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
g_data_w : NATURAL := 32;
g_sim_level : NATURAL := 1
);
+ PORT (
+ tb_end : OUT STD_LOGIC
+ );
END ENTITY tb_tr_nonbonded;
ARCHITECTURE str of tb_tr_nonbonded IS
@@ -292,8 +296,14 @@ BEGIN
-- Duration
p_tb_end : PROCESS
BEGIN
+ tb_end <= '0';
WAIT for 50 us;
- ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+ tb_end <= '1';
+ IF g_tb_end=FALSE THEN
+ REPORT "Tb Simulation finished." SEVERITY NOTE;
+ ELSE
+ REPORT "Tb Simulation finished." SEVERITY FAILURE;
+ END IF;
WAIT;
END PROCESS;
diff --git a/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd b/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
index bdef46b6ca..8e4d2646f7 100644
--- a/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
@@ -38,6 +38,7 @@ END tb_tb_tr_xaui;
ARCHITECTURE tb OF tb_tb_tr_xaui IS
CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=>'1');
SIGNAL tb_end_vec : STD_LOGIC_VECTOR(31 DOWNTO 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ SIGNAL tb_end : STD_LOGIC := '0';
BEGIN
-- g_technology : NATURAL := c_tech_stratixiv;
@@ -47,9 +48,12 @@ BEGIN
u_tr_xaui_sim_level_0 : ENTITY work.tb_tr_xaui GENERIC MAP (c_tech_select_default, FALSE, 0) PORT MAP (tb_end_vec(0));
u_tr_xaui_sim_level_1 : ENTITY work.tb_tr_xaui GENERIC MAP (c_tech_select_default, FALSE, 1) PORT MAP (tb_end_vec(1));
+ tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+
p_tb_end : PROCESS
BEGIN
- WAIT UNTIL tb_end_vec=c_tb_end_vec;
+ WAIT UNTIL tb_end='1';
+ WAIT FOR 1 ns;
REPORT "Multi tb simulation finished." SEVERITY FAILURE;
WAIT;
END PROCESS;
--
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