diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
index a87110eabc5df42106d8ca04d377ab5af3452fa5..6f4cc22060eaee773e53c4e1ec30d40936544d55 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
@@ -45,31 +45,6 @@ set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
set_location_assignment PIN_AT31 -to QSFP_RST
-set_location_assignment PIN_AY33 -to QSFP_SCL[0]
-set_location_assignment PIN_AY32 -to QSFP_SCL[1]
-set_location_assignment PIN_AY30 -to QSFP_SCL[2]
-set_location_assignment PIN_AN33 -to QSFP_SCL[3]
-set_location_assignment PIN_AN31 -to QSFP_SCL[4]
-set_location_assignment PIN_AJ33 -to QSFP_SCL[5]
-set_location_assignment PIN_BA32 -to QSFP_SDA[0]
-set_location_assignment PIN_BA31 -to QSFP_SDA[1]
-set_location_assignment PIN_AP33 -to QSFP_SDA[2]
-set_location_assignment PIN_AM33 -to QSFP_SDA[3]
-set_location_assignment PIN_AK33 -to QSFP_SDA[4]
-set_location_assignment PIN_AH32 -to QSFP_SDA[5]
-
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[4]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
### QSFP_1_0
@@ -118,14 +93,10 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[4]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[6]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[7]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[8]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[9]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[10]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[11]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[4]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[5]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[6]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[7]
#set_location_assignment PIN_B9 -to BCK_RX[0]
set_location_assignment PIN_D9 -to BCK_RX[1]
@@ -524,11 +495,12 @@ set_location_assignment PIN_V9 -to BCK_REF_CLK
set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
set_location_assignment PIN_Y13 -to JESD204B_SYSREF
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYSREF
-
-set_location_assignment PIN_U12 -to JESD204B_SYNC_N[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
-set_location_assignment PIN_U14 -to JESD204B_SYNC_N[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
-
+set_location_assignment PIN_AD12 -to JESD204B_SYNC_N[0]
+set_location_assignment PIN_AC13 -to JESD204B_SYNC_N[1]
+set_location_assignment PIN_AA13 -to JESD204B_SYNC_N[2]
+set_location_assignment PIN_AA12 -to JESD204B_SYNC_N[3]
+#set_location_assignment PIN_V14 -to JESD204B_SYNC_N[4]
+#set_location_assignment PIN_V12 -to JESD204B_SYNC_N[5]
+#set_location_assignment PIN_U14 -to JESD204B_SYNC_N[6]
+#set_location_assignment PIN_R13 -to JESD204B_SYNC_N[7]
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index c3eb40039564fe99c6254b8d5cd73a0d93742e60..b88d6390037a6a087ac23f0c47d319d56bfec13a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -94,7 +94,7 @@ ENTITY lofar2_unb2c_sdp_station IS
-- jesd204b syncronization signals
JESD204B_SYSREF : IN STD_LOGIC;
- JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0)
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR((c_sdp_S_pn / c_sdp_S_rcu)-1 DOWNTO 0)
);
END lofar2_unb2c_sdp_station;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 90b501d48f3aceba942ae70091199d09ceef9fc5..895b22b73505274c2f9ff7441309519748e0cb35 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -101,7 +101,7 @@ ENTITY node_sdp_adc_input_and_timing IS
jesd204b_serial_data : IN STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0);
jesd204b_refclk : IN STD_LOGIC;
jesd204b_sysref : IN STD_LOGIC;
- jesd204b_sync_n : OUT STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
+ jesd204b_sync_n : OUT STD_LOGIC_VECTOR((c_sdp_S_pn / c_sdp_S_rcu)-1 DOWNTO 0);
-- Streaming data output
out_sosi_arr : OUT t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
@@ -123,7 +123,10 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
CONSTANT c_bs_bsn_w : NATURAL := 64; --51;
CONSTANT c_bs_block_size : NATURAL := c_sdp_N_fft; -- =1024;
CONSTANT c_dp_fifo_dc_size : NATURAL := 64;
-
+
+ -- Nof sync outputs
+ CONSTANT c_nof_sync_n : NATURAL := c_sdp_S_pn / c_sdp_S_rcu; -- 12/3 = 4. One sync for each RCU.
+
-- JESD signals
SIGNAL rx_clk : STD_LOGIC; -- formerly jesd204b_frame_clk
SIGNAL rx_rst : STD_LOGIC;
@@ -169,7 +172,7 @@ BEGIN
GENERIC MAP(
g_sim => g_sim,
g_nof_streams => c_sdp_S_pn,
- g_nof_sync_n => c_sdp_S_pn/c_sdp_S_rcu, -- = 12/3 = 4
+ g_nof_sync_n => c_nof_sync_n,
g_jesd_freq => c_sdp_jesd204b_freq
)
PORT MAP(
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index a7ce65a423c59fafc5aa03058c1410b9f40105b2..c62bcfbe1bf749408fecdbd870476423aae670fc 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -77,7 +77,7 @@ ENTITY sdp_station IS
-- jesd204b syncronization signals
JESD204B_SYSREF : IN STD_LOGIC;
- JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR((c_sdp_S_pn / c_sdp_S_rcu) -1 DOWNTO 0);
----------------------------------------------
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 105a6387e99a03de89c336edede0fb71ffca64d4..e1570a8bb2df4fbb85e2eeb6918610e18963e3c6 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -48,7 +48,7 @@ ENTITY ip_arria10_e1sg_jesd204b IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
@@ -125,7 +125,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL jesd204b_sync_n_internal_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
SIGNAL jesd204b_sync_n_enabled_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
- SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Component declarations for the IP blocks
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index 2b2c0162a44161a08587a70db58e15efafb9e457..72263827c36312d13ea97ddcd2c0b11cc28e2d4f 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -48,7 +48,7 @@ ENTITY ip_arria10_e2sg_jesd204b IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
@@ -127,7 +127,7 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
SIGNAL jesd204b_sync_n_internal_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
SIGNAL jesd204b_sync_n_enabled_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
- SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Component declarations for the IP blocks
diff --git a/libraries/technology/jesd204b/tech_jesd204b.vhd b/libraries/technology/jesd204b/tech_jesd204b.vhd
index 96ba775aea6096cd7a8ece8a3caf477462ebe151..d996d3682d5344dbaadd43cf1de9204d669739a2 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b.vhd
@@ -68,7 +68,7 @@ ENTITY tech_jesd204b IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
jesd204b_disable_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
index 2ff054424354a47838c528b57443b32db290de37..c6f97ec3e904b49fc32208a0391e7fe7c0b1e229 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
@@ -46,7 +46,7 @@ ENTITY tech_jesd204b_arria10_e2sg IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
@@ -74,7 +74,8 @@ BEGIN
u_ip_arria10_e2sg_jesd204b : ip_arria10_e2sg_jesd204b
GENERIC MAP(
g_sim => g_sim,
- g_nof_streams => g_nof_streams,
+ g_nof_streams => g_nof_streams,
+ g_nof_sync_n => g_nof_sync_n,
g_direction => g_direction
)
PORT MAP(