From 87499c6037bf1e9734ab52dcff3d04ef0dd86832 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Mon, 13 Dec 2021 17:27:08 +0100
Subject: [PATCH] Use start_pulse_dly to make sure mm_start_address_slv is
stable before mm_start_pulse.
---
.../base/dp/src/vhdl/dp_block_from_mm_dc.vhd | 23 +++++++++++++------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
index bb061f3bd1..cdf640ced4 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
@@ -62,9 +62,11 @@ ARCHITECTURE str OF dp_block_from_mm_dc IS
CONSTANT c_packet_size : NATURAL := g_nof_data * g_data_size; -- 512 * 2 = 1024 words.
CONSTANT c_fifo_size : NATURAL := c_packet_size * 2;
CONSTANT c_start_addr_w : NATURAL := c_natural_w;
+ CONSTANT c_delay_len : NATURAL := c_meta_delay_len;
SIGNAL mm_fifo_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL mm_fifo_siso : t_dp_siso;
+ SIGNAL start_pulse_dly : STD_LOGIC_VECTOR(0 TO c_delay_len) := (OTHERS => '0');
SIGNAL mm_start_pulse : STD_LOGIC := '0';
SIGNAL mm_done : STD_LOGIC := '0';
SIGNAL start_address_slv : STD_LOGIC_VECTOR(c_start_addr_w-1 DOWNTO 0) := (OTHERS => '0');
@@ -72,18 +74,22 @@ ARCHITECTURE str OF dp_block_from_mm_dc IS
SIGNAL mm_start_address : NATURAL := 0;
BEGIN
-
- p_common_spulse_start_pulse : ENTITY common_lib.common_spulse
+ -- Use start_pulse_dly to make sure mm_start_address_slv is stable before
+ -- mm_start_pulse, also when mm_clk is faster than dp_clk (e.g. in sim).
+ start_pulse_dly(0) <= start_pulse;
+ start_pulse_dly(1 TO c_delay_len) <= start_pulse_dly(0 TO c_delay_len-1) WHEN rising_edge(dp_clk);
+
+ u_common_spulse_start_pulse : ENTITY common_lib.common_spulse
PORT MAP (
in_rst => dp_rst,
in_clk => dp_clk,
- in_pulse => start_pulse,
+ in_pulse => start_pulse_dly(c_delay_len),
out_rst => mm_rst,
out_clk => mm_clk,
out_pulse => mm_start_pulse
);
- p_common_spulse_mm_done : ENTITY common_lib.common_spulse
+ u_common_spulse_mm_done : ENTITY common_lib.common_spulse
PORT MAP (
in_rst => mm_rst,
in_clk => mm_clk,
@@ -96,7 +102,10 @@ BEGIN
start_address_slv <= TO_UVEC(start_address, c_start_addr_w);
mm_start_address <= TO_UINT(mm_start_address_slv);
- p_common_async_slv_start_address : ENTITY common_lib.common_async_slv
+ u_common_async_slv_start_address : ENTITY common_lib.common_async_slv
+ GENERIC MAP (
+ g_delay_len => c_meta_delay_len
+ )
PORT MAP (
rst => dp_rst,
clk => dp_clk,
@@ -104,7 +113,7 @@ BEGIN
dout => mm_start_address_slv
);
- p_dp_fifo_fill_eop : ENTITY work.dp_fifo_fill_eop
+ u_dp_fifo_fill_eop : ENTITY work.dp_fifo_fill_eop
GENERIC MAP (
g_use_dual_clock => TRUE,
g_data_w => c_word_w,
@@ -124,7 +133,7 @@ BEGIN
src_in => out_siso
);
- p_dp_block_from_mm : ENTITY work.dp_block_from_mm
+ u_dp_block_from_mm : ENTITY work.dp_block_from_mm
GENERIC MAP (
g_data_size => g_data_size,
g_step_size => g_step_size,
--
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