diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 38214e72d7c3202a66b85fe2fed3e064fda6f004..6a102999a4b198ff37643cf257c9fe066758d4d1 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -52,8 +52,7 @@ ENTITY ddrctrl IS
g_nof_streams : NATURAL := 12; -- number of input streams
g_data_w : NATURAL := 14; -- data with of input data vectors
g_stop_percentage : NATURAL := 50;
- g_block_size : NATURAL := 1024;
- g_burstsize : NATURAL := 64
+ g_block_size : NATURAL := 1024
);
PORT (
clk : IN STD_LOGIC := '0';
@@ -87,8 +86,10 @@ ARCHITECTURE str OF ddrctrl IS
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- 576
CONSTANT c_wr_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ CONSTANT c_wr_fifo_uw_w : NATURAL := ceil_log2(c_wr_fifo_depth*(func_tech_ddr_ctlr_data_w(g_tech_ddr)/c_io_ddr_data_w));
CONSTANT c_rd_fifo_uw_w : NATURAL := ceil_log2(c_rd_fifo_depth*(func_tech_ddr_ctlr_data_w(g_tech_ddr)/c_io_ddr_data_w));
+ CONSTANT c_burstsize : NATURAL := g_tech_ddr.maxburstsize;
CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
CONSTANT c_max_adr : NATURAL := 2**(c_adr_w)-1; -- the maximal address that is possible within the vector length of the address
CONSTANT c_bim : NATURAL := (c_max_adr*c_io_ddr_data_w)/(g_block_size*g_nof_streams*g_data_w); -- the amount of whole blocks that fit in memory.
@@ -104,8 +105,8 @@ ARCHITECTURE str OF ddrctrl IS
-- the amount of overflow after one block is written
CONSTANT c_of_pb : NATURAL := (g_block_size*g_nof_streams*g_data_w)-(((g_block_size*g_nof_streams*g_data_w)/c_io_ddr_data_w)*c_io_ddr_data_w); -- amount of overflow after one block is written to memory
- CONSTANT c_aof_full_burst : NATURAL := c_nof_adr/g_burstsize;
- CONSTANT c_last_burstsize : NATURAL := c_nof_adr-(c_aof_full_burst*g_burstsize);
+ CONSTANT c_aof_full_burst : NATURAL := c_nof_adr/c_burstsize;
+ CONSTANT c_last_burstsize : NATURAL := c_nof_adr-(c_aof_full_burst*c_burstsize);
SIGNAL s_last_burstsize : NATURAL := c_last_burstsize;
@@ -122,12 +123,11 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL rd_siso : t_dp_siso := c_dp_siso_rst;
SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL stop : STD_LOGIC;
+ SIGNAL wr_fifo_usedw : STD_LOGIC_VECTOR(c_wr_fifo_uw_w-1 DOWNTO 0);
SIGNAL rd_fifo_usedw : STD_LOGIC_VECTOR(c_rd_fifo_uw_w-1 DOWNTO 0);
SIGNAL rd_ready : STD_LOGIC;
- SIGNAL inp_ds : NATURAL;
SIGNAL inp_bsn_adr : NATURAL;
- SIGNAL outp_ds : NATURAL;
- SIGNAL outp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ SIGNAL bsn_co : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
SIGNAL data_stopped : STD_LOGIC;
BEGIN
@@ -153,7 +153,6 @@ BEGIN
in_stop => stop,
out_sosi => out_sosi,
out_adr => out_adr,
- out_bsn_ds => inp_ds,
out_bsn_adr => inp_bsn_adr,
out_data_stopped => data_stopped
);
@@ -206,7 +205,7 @@ BEGIN
wr_clk => clk,
wr_rst => rst,
- wr_fifo_usedw => open,
+ wr_fifo_usedw => wr_fifo_usedw,
wr_sosi => wr_sosi,
wr_siso => open,
@@ -240,15 +239,15 @@ BEGIN
g_in_data_w => c_io_ddr_data_w,
g_nof_streams => g_nof_streams,
g_data_w => g_data_w,
- g_block_size => g_block_size
+ g_block_size => g_block_size,
+ g_bim => c_bim
)
PORT MAP(
clk => clk,
rst => rst,
in_sosi => rd_sosi,
- in_ds => outp_ds,
- in_bsn => outp_bsn,
+ in_bsn => bsn_co,
out_sosi_arr => out_sosi_arr,
out_ready => rd_ready
@@ -265,11 +264,13 @@ BEGIN
g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => c_io_ddr_data_w,
g_block_size => g_block_size,
+ g_wr_fifo_uw_w => c_wr_fifo_uw_w,
g_rd_fifo_uw_w => c_rd_fifo_uw_w,
g_max_adr => c_nof_adr,
- g_burstsize => g_burstsize,
+ g_burstsize => c_burstsize,
g_last_burstsize => c_last_burstsize,
- g_adr_per_b => c_adr_per_b
+ g_adr_per_b => c_adr_per_b,
+ g_bim => c_bim
)
PORT MAP(
clk => clk,
@@ -279,7 +280,6 @@ BEGIN
inp_of => out_of,
inp_sosi => out_sosi,
inp_adr => out_adr,
- inp_ds => inp_ds,
inp_bsn_adr => inp_bsn_adr,
inp_data_stopped => data_stopped,
rst_ddrctrl_input => rst_ddrctrl_input,
@@ -288,11 +288,11 @@ BEGIN
dvr_mosi => dvr_mosi,
dvr_miso => dvr_miso,
wr_sosi => wr_sosi,
+ wr_fifo_usedw => wr_fifo_usedw,
rd_fifo_usedw => rd_fifo_usedw,
-- ddrctrl_output
- outp_ds => outp_ds,
- outp_bsn => outp_bsn,
+ outp_bsn => bsn_co,
-- ddrctrl_controller
stop_in => stop_in,
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 3f4cab12b7d991c5abd15ddc3fe2030bb5ff222e..8a91295a14c756bef34e5da15016791a507e2340 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -46,11 +46,13 @@ ENTITY ddrctrl_controller IS
g_rd_fifo_depth : NATURAL; -- 256
g_rd_data_w : NATURAL; -- 256
g_block_size : NATURAL; -- 1024
+ g_wr_fifo_uw_w : NATURAL; -- 8
g_rd_fifo_uw_w : NATURAL; -- 8
g_max_adr : NATURAL; -- 16128
g_burstsize : NATURAL; -- 64
g_last_burstsize : NATURAL; -- 18
- g_adr_per_b : NATURAL -- 299
+ g_adr_per_b : NATURAL; -- 299
+ g_bim : NATURAL -- 54
);
PORT (
clk : IN STD_LOGIC;
@@ -60,7 +62,6 @@ ENTITY ddrctrl_controller IS
inp_of : IN NATURAL;
inp_sosi : IN t_dp_sosi;
inp_adr : IN NATURAL;
- inp_ds : IN NATURAL;
inp_bsn_adr : IN NATURAL;
inp_data_stopped : IN STD_LOGIC;
rst_ddrctrl_input : OUT STD_LOGIC;
@@ -69,10 +70,10 @@ ENTITY ddrctrl_controller IS
dvr_mosi : OUT t_mem_ctlr_mosi;
dvr_miso : IN t_mem_ctlr_miso;
wr_sosi : OUT t_dp_sosi;
+ wr_fifo_usedw : IN STD_LOGIC_VECTOR(g_wr_fifo_uw_w-1 DOWNTO 0);
rd_fifo_usedw : IN STD_LOGIC_VECTOR(g_rd_fifo_uw_w-1 DOWNTO 0);
-- ddrctrl_output
- outp_ds : OUT NATURAL;
outp_bsn : OUT STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
-- ddrctrl_controller
@@ -94,12 +95,10 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
CONSTANT c_rd_data_w : NATURAL := g_nof_streams*g_out_data_w; -- 168
CONSTANT c_rest : NATURAL := c_rd_data_w-(g_wr_data_w mod c_rd_data_w); -- 96
- CONSTANT c_max_read_cnt : NATURAL := (g_max_adr+1)/g_burstsize; -- 256
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
- CONSTANT c_proportion : NATURAL := (c_io_ddr_data_w/c_rd_data_w)+1;
-- type for statemachine
- TYPE t_state IS (RESET, WRITING, SET_STOP, STOP_WRITING, LAST_WRITE_BURST, START_READING, READING, STOP_READING, IDLE);
+ TYPE t_state IS (RESET, WAIT_FOR_SOP, START_WRITING, WRITING, SET_STOP, STOP_WRITING, LAST_WRITE_BURST, START_READING, READING, STOP_READING, IDLE);
-- record for readability
TYPE t_reg IS RECORD
@@ -116,12 +115,11 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
rst_ddrctrl_input : STD_LOGIC;
-- writing signals
- need_burst : STD_LOGIC;
+ wr_burst_en : STD_LOGIC;
-- reading signals
- outp_ds : NATURAL;
outp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
- read_cnt : NATURAL;
+ read_adr : NATURAL;
rd_burst_en : STD_LOGIC;
-- output
@@ -129,45 +127,74 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
wr_sosi : t_dp_sosi;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', '0', 0, (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
+ CONSTANT c_t_reg_init : t_reg := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', '0', (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
-- signals for readability
SIGNAL d_reg : t_reg := c_t_reg_init;
SIGNAL q_reg : t_reg := c_t_reg_init;
+
BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
- p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_ds, inp_bsn_adr, inp_data_stopped, dvr_miso, rd_fifo_usedw, stop_in)
+ p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_bsn_adr, inp_data_stopped, dvr_miso, rd_fifo_usedw, stop_in)
VARIABLE v : t_reg := c_t_reg_init;
BEGIN
- v := q_reg;
+ v := q_reg;
+ v.wr_sosi := inp_sosi;
CASE q_reg.state IS
WHEN RESET =>
- v := c_t_reg_init;
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := (OTHERS => '0');
- v.dvr_mosi.wr := '1';
+ v := c_t_reg_init;
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := (OTHERS => '0');
+ v.dvr_mosi.wr := '1';
+ v.wr_sosi.valid := '1';
+ WHEN WAIT_FOR_SOP =>
+ v.dvr_mosi.burstbegin := '0';
+ v.rst_ddrctrl_input := '0';
+ IF q_reg.started = '0' AND inp_sosi.eop = '1' THEN
+ v.wr_sosi.valid := '1';
+ ELSIF inp_sosi.sop = '1' THEN
+ v.state := WRITING; --START_WRITING;
+ ELSE
+ v.wr_sosi.valid := '0';
+ v.state := WAIT_FOR_SOP;
+ END IF;
- WHEN WRITING =>
- -- if adr mod g_burstsize = 0
- -- this makes sure that only ones every 64 writes a writeburst is started.
- IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_w-1 DOWNTO 0) = c_zeros AND q_reg.dvr_mosi.burstbegin = '0'THEN
- v.need_burst := '1';
+
+
+ WHEN START_WRITING =>
+ -- this state generates the first write burst.
+ IF TO_UINT(wr_fifo_usedw) > g_burstsize AND dvr_miso.done = '1' AND v.wr_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
+ v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+q_reg.stop_burstsize, c_adr_w);
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := TO_UVEC(g_burstsize-q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.wr_burst_en := '0';
+ v.wr_burst_en := '1';
+ v.state := WRITING;
+ ELSE
+ v.dvr_mosi.burstbegin := '0';
+ v.state := START_WRITING;
END IF;
- IF dvr_miso.done = '1' AND q_reg.need_burst = '1' THEN
+
+
+ WHEN WRITING =>
+ -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
+ IF TO_UINT(wr_fifo_usedw) > g_burstsize AND dvr_miso.done = '1' AND q_reg.wr_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
v.dvr_mosi.burstbegin := '1';
- v.need_burst := '0';
+ v.wr_burst_en := '0';
IF inp_adr < g_burstsize-1 THEN
v.dvr_mosi.address := TO_UVEC(g_max_adr-g_last_burstsize, dvr_mosi.address'length);
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
@@ -181,30 +208,45 @@ BEGIN
END IF;
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
- v.wr_sosi := inp_sosi;
+
+ IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_w-1 DOWNTO 0) = c_zeros AND q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ END IF;
+
+ IF stop_in = '1' THEN
+ v.ready_for_set_stop := '1';
+ END IF;
+
+ IF q_reg.ready_for_set_stop = '1' AND inp_sosi.eop = '1' THEN
+ v.state := SET_STOP;
+ ELSIF q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND q_reg.stopped = '0' THEN
+ v.state := STOP_WRITING;
+ ELSE
+ v.state := WRITING;
+ END IF;
WHEN SET_STOP =>
- --setting a stop address dependend on the g_stop_percentage
+ -- this state sets a stop address dependend on the g_stop_percentage.
IF inp_adr+c_pof_ma >= g_max_adr THEN
v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr-c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO 0);
ELSE
v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr+c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO 0);
END IF;
- v.ready_for_set_stop := '0';
+ v.ready_for_set_stop := '0';
v.last_adr_to_write_to(c_adr_w-1 DOWNTO c_bitshift_w) := v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_w);
v.last_adr_to_write_to(c_bitshift_w-1 DOWNTO 0) := (OTHERS => '0');
- v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w-1 DOWNTO 0))-TO_UINT(v.last_adr_to_write_to);
+ v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w-1 DOWNTO 0))-TO_UINT(v.last_adr_to_write_to)+1;
-- still a write cyle
-- if adr mod g_burstsize = 0
-- this makes sure that only ones every 64 writes a writeburst is started.
IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_w-1 DOWNTO 0) = c_zeros AND q_reg.dvr_mosi.burstbegin = '0'THEN
- v.need_burst := '1';
+ v.wr_burst_en := '1';
END IF;
- IF dvr_miso.done = '1' AND q_reg.need_burst = '1' THEN
+ IF dvr_miso.done = '1' AND q_reg.wr_burst_en = '1' THEN
v.dvr_mosi.burstbegin := '1';
- v.need_burst := '0';
+ v.wr_burst_en := '0';
IF inp_adr < g_burstsize-1 THEN
v.dvr_mosi.address := TO_UVEC(g_max_adr-g_last_burstsize, dvr_mosi.address'length);
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
@@ -218,20 +260,28 @@ BEGIN
END IF;
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
- v.wr_sosi := inp_sosi;
+
+ IF q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND q_reg.stopped = '0' THEN
+ v.state := STOP_WRITING;
+ ELSE
+ v.state := WRITING;
+ END IF;
+
WHEN STOP_WRITING =>
+ -- this state stops the writing by generatign one last whole write burst which almost empties wr_fifo.
+ v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0';
v.stopped := '1';
+ v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
-- wait until the write burst is finished
IF inp_data_stopped = '0' THEN
v.state := STOP_WRITING;
- ELSIF dvr_miso.done = '1' AND q_reg.dvr_mosi.burstbegin = '0' AND q_reg.need_burst = '0' THEN
- v.wr_sosi.valid := '0';
- v.state := LAST_WRITE_BURST;
+ ELSIF dvr_miso.done = '1' AND q_reg.dvr_mosi.burstbegin = '0' AND q_reg.wr_burst_en = '0' THEN
+ v.state := LAST_WRITE_BURST;
ELSE
- v.state := STOP_WRITING;
+ v.state := STOP_WRITING;
END IF;
@@ -239,11 +289,11 @@ BEGIN
-- if adr mod g_burstsize = 0
-- this makes sure that only ones every 64 writes a writeburst is started.
IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_w-1 DOWNTO 0) = c_zeros AND q_reg.dvr_mosi.burstbegin = '0'THEN
- v.need_burst := '1';
+ v.wr_burst_en := '1';
END IF;
- IF dvr_miso.done = '1' AND q_reg.need_burst = '1' THEN
+ IF dvr_miso.done = '1' AND q_reg.wr_burst_en = '1' THEN
v.dvr_mosi.burstbegin := '1';
- v.need_burst := '0';
+ v.wr_burst_en := '0';
IF inp_adr < g_burstsize-1 THEN
v.dvr_mosi.address := TO_UVEC(g_max_adr-g_last_burstsize, dvr_mosi.address'length);
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
@@ -257,16 +307,16 @@ BEGIN
END IF;
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
- v.wr_sosi := inp_sosi;
WHEN LAST_WRITE_BURST =>
-
+ -- this state stops the writing by generatign one last write burst which empties wr_fifo.
IF dvr_miso.done = '1' THEN
v.dvr_mosi.burstbegin := '1';
v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0);
v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
v.state := START_READING;
+ v.rd_burst_en := '1';
ELSE
v.dvr_mosi.burstbegin := '0';
v.state := LAST_WRITE_BURST;
@@ -277,48 +327,56 @@ BEGIN
WHEN START_READING =>
+ -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
v.dvr_mosi.burstbegin := '0';
- v.rd_burst_en := '1';
- v.outp_ds := inp_ds;
- v.read_cnt := 0;
+ v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn)-g_bim, c_dp_stream_bsn_w);
- FOR I IN 0 TO inp_bsn_adr+(g_max_adr-TO_UINT(q_reg.stop_adr)) LOOP -- takes a while WRONG, wil be fixed after L2SDP-705, 706 and 70
- IF v.outp_ds-c_rest <= 0 THEN
- v.outp_ds := v.outp_ds+c_rd_data_w-c_rest;
- ELSE
- v.outp_ds := v.outp_ds-c_rest;
- END IF;
- END LOOP;
- v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn), c_dp_stream_bsn_w); -- WRONG, wil be fixed after L2SDP-705, 706 and 707
- v.state := READING;
+ IF dvr_miso.done = '1' AND v.rd_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := TO_UVEC(g_burstsize-q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+q_reg.stop_burstsize, c_adr_w);
+ v.rd_burst_en := '0';
+ v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+g_burstsize;
+ END IF;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ IF dvr_miso.done = '0' AND q_reg.rd_burst_en = '0' THEN
+ v.rd_burst_en := '1';
+ v.state := READING;
+ ELSE
+ v.state := START_READING;
+ END IF;
WHEN READING =>
-- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
- IF TO_UINT(rd_fifo_usedw) <= 10 AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' AND dvr_miso.done = '1' THEN
- v.dvr_mosi.burstbegin := '0';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.outp_ds := inp_ds;
- IF TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+g_burstsize*q_reg.read_cnt >= g_max_adr THEN
- v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC((TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+g_burstsize*q_reg.read_cnt)-g_max_adr-1, c_adr_w);
+ IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.burstbegin := '1';
+ v.rd_burst_en := '0';
+ IF q_reg.read_adr > g_max_adr-g_burstsize THEN
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := 0;
ELSE
- v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+g_burstsize*q_reg.read_cnt, c_adr_w);
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := q_reg.read_adr+g_burstsize;
END IF;
- v.dvr_mosi.burstbegin := '1';
- v.read_cnt := v.read_cnt+1;
- v.rd_burst_en := '0';
ELSE
v.dvr_mosi.burstbegin := '0';
END IF;
-- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- IF TO_UINT(rd_fifo_usedw) = 11 THEN
+ IF dvr_miso.done = '0' THEN
v.rd_burst_en := '1';
END IF;
- IF q_reg.read_cnt >= c_max_read_cnt THEN
+ -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
+ IF q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0) = TO_UVEC(q_reg.read_adr, c_adr_w) THEN
v.state := STOP_READING;
ELSE
v.state := READING;
@@ -327,19 +385,33 @@ BEGIN
WHEN STOP_READING =>
- IF dvr_miso.done = '1' THEN
- v.rst_ddrctrl_input := '0';
- v.stopped := '0';
- v.state := IDLE;
- ELSE
- v.state := STOP_READING;
- END IF;
+ -- this is the last read burst, this make sure every data containing word in the memory has been read.
+ IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.stopped := '0';
+ v.wr_sosi.valid := '0';
+ v.state := WAIT_FOR_SOP;
+ v.wr_burst_en := '1';
+ v.rst_ddrctrl_input := '1';
+ ELSE
+ v.dvr_mosi.burstbegin := '0';
+ v.state := STOP_READING;
+ END IF;
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ IF dvr_miso.done = '0' THEN
+ v.rd_burst_en := '1';
+ END IF;
WHEN IDLE =>
- v.wr_sosi.valid := '0';
+ IF q_reg.started = '0' THEN
+ v.wr_sosi.valid := '0';
+ END IF;
-- the statemachine goes to Idle when its finished or when its waiting on other components.
WHEN OTHERS =>
@@ -349,16 +421,15 @@ BEGIN
END CASE;
- IF q_reg.state = RESET OR q_reg.state = WRITING OR q_reg.state = SET_STOP OR q_reg.state = IDLE THEN
+ IF q_reg.state = RESET OR q_reg.state = IDLE THEN
IF stop_in = '1' THEN
v.ready_for_set_stop := '1';
ELSIF q_reg.ready_for_set_stop = '1' AND inp_sosi.eop = '1' THEN
v.state := SET_STOP;
- ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND q_reg.stopped = '0' THEN
+ ELSIF q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND q_reg.stopped = '0' THEN
v.state := STOP_WRITING;
- ELSIF v.stopped = '0' AND inp_sosi.valid = '1' AND q_reg.started = '1' THEN
+ ELSIF v.stopped = '0' AND inp_sosi.valid = '1' AND q_reg.started = '1' THEN
v.state := WRITING;
- v.wr_sosi := inp_sosi;
ELSIF q_reg.stopped = '1' THEN
v.state := STOP_READING;
ELSE
@@ -373,7 +444,6 @@ BEGIN
IF inp_sosi.eop = '1' THEN
v.started := '1';
- v.wr_sosi.valid := '1';
END IF;
d_reg <= v;
@@ -385,7 +455,6 @@ BEGIN
wr_sosi <= q_reg.wr_sosi;
stop_out <= q_reg.stopped;
outp_bsn <= q_reg.outp_bsn;
- outp_ds <= q_reg.outp_ds;
rst_ddrctrl_input <= q_reg.rst_ddrctrl_input OR rst;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
index 208780472a0e4df9cfc607de8f8f3e87e0ffb783..c27c54acd3401cc8996d26e5dcebcd664ab65fb3 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -59,7 +59,6 @@ ENTITY ddrctrl_input IS
in_stop : IN STD_LOGIC;
out_sosi : OUT t_dp_sosi; -- output data
out_adr : OUT NATURAL;
- out_bsn_ds : OUT NATURAL;
out_bsn_adr : OUT NATURAL;
out_data_stopped : OUT STD_LOGIC
);
@@ -76,7 +75,6 @@ ARCHITECTURE str OF ddrctrl_input IS
SIGNAL sosi_p_rp : t_dp_sosi := c_dp_sosi_init;
SIGNAL sosi_rp_ac : t_dp_sosi := c_dp_sosi_init;
SIGNAL adr : NATURAL := 0;
- SIGNAL bsn_ds : NATURAL := 0;
SIGNAL valid : STD_LOGIC := '0';
SIGNAL data_stopped_rp_ac : STD_LOGIC := '0';
@@ -110,7 +108,6 @@ BEGIN
in_sosi => sosi_p_rp, -- input data
in_stop => in_stop,
out_sosi => sosi_rp_ac, -- output data
- out_bsn_ds => bsn_ds, -- amount of bits between adr [0] and sosi_arr[0][0] where bsn is assigned to
out_data_stopped => data_stopped_rp_ac
);
@@ -124,12 +121,10 @@ BEGIN
clk => clk,
rst => rst,
in_sosi => sosi_rp_ac, -- input data
- in_bsn_ds => bsn_ds,
in_data_stopped => data_stopped_rp_ac,
out_sosi => out_sosi, -- output data
out_adr => adr,
out_bsn_adr => out_bsn_adr,
- out_bsn_ds => out_bsn_ds,
out_data_stopped => out_data_stopped
);
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index 916bbb2a18196a555303ca81f99dc0f79b188292..874e81e5ea1a12a4dd40c0247d77818f41208549 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -48,12 +48,10 @@ ENTITY ddrctrl_input_address_counter IS
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi; -- input data
- in_bsn_ds : IN NATURAL;
in_data_stopped : IN STD_LOGIC;
out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
out_adr : OUT NATURAL;
out_bsn_adr : OUT NATURAL;
- out_bsn_ds : OUT NATURAL;
out_data_stopped : OUT STD_LOGIC
);
END ddrctrl_input_address_counter;
@@ -73,15 +71,13 @@ ARCHITECTURE rtl OF ddrctrl_input_address_counter IS
bsn_passed : STD_LOGIC;
out_sosi : t_dp_sosi;
out_bsn_adr : NATURAL;
- out_bsn_ds : NATURAL;
out_data_stopped : STD_LOGIC;
s_in_sosi : t_dp_sosi;
- s_in_bsn_ds : NATURAL;
s_in_data_stopped : STD_LOGIC;
s_adr : NATURAL;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, 0, '0', c_dp_sosi_init, 0, '0', 0);
+ CONSTANT c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, '0', c_dp_sosi_init, '0', 0);
-- signals for readability
@@ -93,7 +89,7 @@ BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- Increments the address each time in_sosi.valid = '1', if address = g_max_adr the address is reset to 0.
- p_adr : PROCESS(rst, in_sosi, in_bsn_ds, in_data_stopped, q_reg)
+ p_adr : PROCESS(rst, in_sosi, in_data_stopped, q_reg)
VARIABLE v : t_reg;
@@ -102,16 +98,14 @@ BEGIN
-- compensate for delay in ddrctrl_input_address_counter
v.out_sosi := q_reg.s_in_sosi;
- v.out_bsn_ds := q_reg.s_in_bsn_ds;
v.out_data_stopped := q_reg.s_in_data_stopped;
v.s_in_sosi := in_sosi;
- v.s_in_bsn_ds := in_bsn_ds;
v.s_in_data_stopped := in_data_stopped;
CASE q_reg.state IS
WHEN RESET =>
- v.s_adr := 0;
+ v := c_t_reg_init;
IF q_reg.s_in_sosi.sop = '1' THEN
v.out_bsn_adr := v.s_adr;
@@ -136,7 +130,7 @@ BEGIN
WHEN IDLE =>
-- after a reset skip the first data block so the ddr memory can initialize.
- IF NOT(q_reg.s_in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
+ IF in_sosi.sop = '1' THEN
v.bsn_passed := '1';
END IF;
@@ -160,7 +154,6 @@ BEGIN
out_sosi <= q_reg.out_sosi;
out_adr <= q_reg.s_adr;
out_bsn_adr <= q_reg.out_bsn_adr;
- out_bsn_ds <= q_reg.out_bsn_ds;
out_sosi.bsn <= q_reg.out_sosi.bsn;
out_data_stopped <= q_reg.out_data_stopped;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index 7b7a3ed0d98c5229929b4d25982b3aa41910a258..f85f1b201e9f30497302d8b684c47f73647325c9 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -48,7 +48,6 @@ ENTITY ddrctrl_input_repack IS
in_sosi : IN t_dp_sosi; -- input data
in_stop : IN STD_LOGIC := '0';
out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
- out_bsn_ds : OUT NATURAL := 0;
out_bsn_wr : OUT STD_LOGIC := '0';
out_data_stopped : OUT STD_LOGIC := '0'
);
@@ -69,19 +68,16 @@ ARCHITECTURE rtl OF ddrctrl_input_repack IS
state : t_state; -- the state the process is currently in;
c_v : STD_LOGIC_VECTOR(k_c_v_w-1 DOWNTO 0); -- the vector that stores the input data until the data is put into the output data vector
c_v_count : NATURAL; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
- a_of : NATURAL; -- this is the amount of bits that the first data word(168) is shifted from the first bit in the data word(576)
q_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
- q_sop : STD_LOGIC;
- q_out_bsn_ds : NATURAL;
+ q_sop : STD_LOGIC;
s_input_cnt : NATURAL;
out_of : NATURAL;
out_data_count : STD_LOGIC; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
- out_bsn_ds : NATURAL; -- this is the amount of bits that the data corresponding to out_bsn is shifted from the first bit in that data word
out_data_stopped : STD_LOGIC; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, (OTHERS => '0'), 0, 0, (OTHERS => '0'), '0', 0, 0, 0, '0', c_dp_sosi_init, 0, '0');
+ CONSTANT c_t_reg_init : t_reg := (RESET, (OTHERS => '0'), 0, (OTHERS => '0'), '0', 0, 0, '0', c_dp_sosi_init, '0');
-- signals for readability
@@ -125,7 +121,7 @@ BEGIN
v.state := FILL_VECTOR;
END IF;
- IF NOT (q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
+ IF in_sosi.eop = '1' THEN
v.s_input_cnt := 0;
v.state := BSN;
END IF;
@@ -139,7 +135,6 @@ BEGIN
v.out_data_count := '1'; -- increase the counter of out_sosi.data with 1
v.s_input_cnt := q_reg.s_input_cnt+1;
v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
- v.out_bsn_ds := q_reg.q_out_bsn_ds;
v.out_sosi.sop := q_reg.q_sop;
v.out_sosi.eop := '0';
v.out_data_stopped := '0';
@@ -155,7 +150,7 @@ BEGIN
v.state := FILL_VECTOR;
END IF;
- IF NOT (q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
+ IF in_sosi.eop = '1' THEN
v.s_input_cnt := 0;
v.state := BSN;
END IF;
@@ -186,7 +181,7 @@ BEGIN
v.state := FILL_VECTOR;
END IF;
- IF NOT (q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
+ IF in_sosi.eop = '1' THEN
v.s_input_cnt := 0;
v.state := BSN;
END IF;
@@ -195,23 +190,18 @@ BEGIN
WHEN BSN =>
v.c_v(k_c_v_w-1 DOWNTO ((g_in_data_w*q_reg.c_v_count)+q_reg.out_of)) := (OTHERS =>'0');
+ v.out_of := 0;
IF ((g_in_data_w*q_reg.c_v_count)+q_reg.out_of < c_out_data_w*1) THEN
v.out_sosi.data(c_out_data_w-1 DOWNTO 0) := v.c_v(c_out_data_w-1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
ELSE
v.out_sosi.data(c_out_data_w-1 DOWNTO 0) := v.c_v(k_c_v_w-1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
END IF;
-- BSN_INPUT
v.q_bsn := in_sosi.bsn; -- a bsn number is saved when the bsn changes
- IF g_in_data_w*q_reg.c_v_count+q_reg.out_of >= c_out_data_w THEN
- v.q_out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
- ELSE
- v.q_out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
- END IF;
v.q_sop := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
- v.a_of := 0;
v.c_v(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0); -- fill c_v
v.c_v_count := 1; -- increase the counter of c_v with 1
v.out_data_count := '0';
@@ -270,7 +260,6 @@ BEGIN
-- fill outputs
out_sosi <= q_reg.out_sosi;
- out_bsn_ds <= q_reg.out_bsn_ds;
out_data_stopped <= q_reg.out_data_stopped;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
index 7896dad2a2c726a34178cab7509d3d598e2ccbf0..2e48f3e4d7861b920a159cc8343f0283e10ef3ea 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
@@ -46,14 +46,14 @@ ENTITY ddrctrl_output IS
g_in_data_w : NATURAL := 576;
g_nof_streams : NATURAL := 12; -- number of input streams
g_data_w : NATURAL := 14; -- data with of input data vectors
- g_block_size : NATURAL := 1024
+ g_block_size : NATURAL := 1024;
+ g_bim : NATURAL := 54
);
PORT (
clk : IN STD_LOGIC := '0';
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi := c_dp_sosi_init; -- input data
- in_ds : IN NATURAL; -- amount of internal overflow this output
- in_bsn : IN STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0); -- bsn corresponding to the data at in_data[in_of]
+ in_bsn : IN STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- output data
out_ready : OUT STD_LOGIC
);
@@ -76,13 +76,13 @@ BEGIN
g_tech_ddr => g_tech_ddr,
g_in_data_w => g_in_data_w,
g_out_data_w => c_out_data_w,
- g_block_size => g_block_size
+ g_block_size => g_block_size,
+ g_bim => g_bim
)
PORT MAP(
clk => clk,
rst => rst,
in_sosi => in_sosi, -- input data
- in_ds => in_ds,
in_bsn => in_bsn,
out_sosi => sosi, -- output data
out_ready => out_ready
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
index 9c8555f3ea8561de24a5de65de0aeaf88bd57c69..fd2a2c43425cc68e36961da24a6ec62f21b62065 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
@@ -50,9 +50,11 @@ BEGIN
-- putting the data from the stream into different streams.
gen_repack_data : FOR I IN 0 TO g_nof_streams-1 GENERATE
- out_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= in_sosi.data(g_data_w*(I+1)-1 DOWNTO g_data_w*I);
- out_sosi_arr(I).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
- out_sosi_arr(I).valid <= in_sosi.valid;
+ out_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= in_sosi.data(g_data_w*(I+1)-1 DOWNTO g_data_w*I);
+ out_sosi_arr(I).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
+ out_sosi_arr(I).valid <= in_sosi.valid;
+ out_sosi_arr(I).sop <= in_sosi.sop;
+ out_sosi_arr(I).eop <= in_sosi.eop;
END GENERATE;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
index 823f5e3ec6ae6e3ad0d25bafedd34b46b25af57e..5f92f62557d7b530caf860856400fba7bef66338 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
@@ -42,13 +42,13 @@ ENTITY ddrctrl_output_unpack IS
g_tech_ddr : t_c_tech_ddr;
g_in_data_w : NATURAL;
g_out_data_w : NATURAL;
- g_block_size : NATURAL
+ g_block_size : NATURAL;
+ g_bim : NATURAL
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi := c_dp_sosi_init;
- in_ds : IN NATURAL;
in_bsn : IN STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
out_sosi : OUT t_dp_sosi := c_dp_sosi_init;
out_ready : OUT STD_LOGIC := '0'
@@ -58,8 +58,10 @@ END ddrctrl_output_unpack;
ARCHITECTURE rtl OF ddrctrl_output_unpack IS
+ CONSTANT c_v_w : NATURAL := g_in_data_w*2;
+
-- type for statemachine
- TYPE t_state IS ( READING, FIRST_READ, SECOND_READ, OVER_HALF, RESET, IDLE, OFF);
+ TYPE t_state IS ( READING, FIRST_READ, OVER_HALF, BSN, RESET, IDLE, OFF);
-- record for readability
TYPE t_reg IS RECORD
@@ -68,15 +70,14 @@ ARCHITECTURE rtl OF ddrctrl_output_unpack IS
op_data_cnt : NATURAL;
delay_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
dd_fresh : STD_LOGIC;
- c_v : STD_LOGIC_VECTOR(g_in_data_w*2-1 DOWNTO 0);
- sr_done : STD_LOGIC;
+ valid_data : STD_LOGIC;
+ c_v : STD_LOGIC_VECTOR(c_v_w-1 DOWNTO 0);
bsn_cnt : NATURAL;
out_sosi : t_dp_sosi;
out_ready : STD_LOGIC;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, 0, 0, (OTHERS => '0'), '0', (OTHERS => '0'), '0', 0, c_dp_sosi_init, '0');
-
+ CONSTANT c_t_reg_init : t_reg := (RESET, 0, 0, (OTHERS => '0'), '0', '0', (OTHERS => '0'), 0, c_dp_sosi_init, '0');
-- signals for readability
SIGNAL d_reg : t_reg := c_t_reg_init;
@@ -87,7 +88,7 @@ BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
- p_state : PROCESS(q_reg, rst, in_sosi, in_ds, in_bsn)
+ p_state : PROCESS(q_reg, rst, in_sosi)
VARIABLE v : t_reg;
@@ -104,107 +105,205 @@ BEGIN
v.bsn_cnt := q_reg.bsn_cnt+1;
v.op_data_cnt := q_reg.op_data_cnt+1;
- IF q_reg.bsn_cnt = g_block_size-1 THEN
- v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
- v.bsn_cnt := 0;
+ IF q_reg.dd_fresh = '1' AND q_reg.valid_data = '0' THEN
+ -- put the delay data into the second half of c_v beceause these are now zeros
+ v.c_v(c_v_w-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '0';
+ v.valid_data := '1';
END IF;
-
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '1';
END IF;
- IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
+ IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND (v.dd_fresh = '1' OR v.valid_data = '1')THEN
v.state := OVER_HALF;
- ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
+ ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' AND v.valid_data = '0' THEN
v.state := IDLE;
ELSE
v.state := READING;
END IF;
+ IF q_reg.out_sosi.eop = '1' THEN
+ v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+ v.out_sosi.eop := '0';
+ v.out_sosi.sop := '1';
+ v.bsn_cnt := 0;
+ ELSIF q_reg.out_sosi.sop = '1' THEN
+ v.out_sosi.sop := '0';
+ END IF;
+
+ IF q_reg.bsn_cnt = g_block_size-3 THEN
+ v.state := BSN;
+ v.out_ready := '1';
+ END IF;
+
+
WHEN OVER_HALF =>
-- generating output data from c_v but past the halfway point of c_v so there needs to be new data added
- v.out_ready := '1';
- v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
- v.out_sosi.valid := '1';
- v.bsn_cnt := q_reg.bsn_cnt+1;
- v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.c_v(g_in_data_w*2-1 DOWNTO g_in_data_w);
- v.c_v(g_in_data_w*2-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
- v.dd_fresh := '0';
- v.a_of := (g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-g_in_data_w;
- v.op_data_cnt := 0;
-
- IF q_reg.bsn_cnt = g_block_size-1 THEN
- v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
- v.bsn_cnt := 0;
+ IF q_reg.dd_fresh = '1' AND q_reg.valid_data = '1' THEN
+ v.out_ready := '1';
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt+1;
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.c_v(c_v_w-1 DOWNTO g_in_data_w);
+ -- put the delay data into the first half of c_v
+ v.c_v(c_v_w-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '0';
+ v.a_of := ((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of)-g_in_data_w;
+ v.op_data_cnt := 0;
+ ELSIF q_reg.dd_fresh = '0' AND q_reg.valid_data = '1' THEN
+ v.out_ready := '1';
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt+1;
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.c_v(c_v_w-1 DOWNTO g_in_data_w);
+ -- put zeros into the second half of c_v beceause dd_fresh is '0'
+ v.c_v(c_v_w-1 DOWNTO g_in_data_w) := (OTHERS => '0');
+ v.a_of := ((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of)-g_in_data_w;
+ v.op_data_cnt := 0;
+ v.valid_data := '0';
+ ELSIF q_reg.dd_fresh = '1' AND q_reg.valid_data = '0' THEN
+ v.out_ready := '1';
+ -- put the delay data into the second half of c_v beceause these are now zeros
+ v.c_v(c_v_w-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.c_v(c_v_w-1 DOWNTO g_in_data_w);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt+1;
+ v.dd_fresh := '0';
+ v.a_of := ((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of)-g_in_data_w;
+ v.op_data_cnt := 0;
END IF;
+
+
+
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
- v.dd_fresh := '1';
+ v.dd_fresh := '1';
END IF;
-
- IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
- v.state := OVER_HALF;
- ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
- v.state := IDLE;
+ IF (g_out_data_w*(v.op_data_cnt+1))+v.a_of >= g_in_data_w AND (v.dd_fresh = '1' OR v.valid_data = '1') THEN
+ v.state := OVER_HALF;
+ ELSIF q_reg.dd_fresh = '0' AND q_reg.valid_data = '0' THEN
+ v.state := IDLE;
ELSE
- v.state := READING;
+ v.state := READING;
+ END IF;
+
+ IF q_reg.out_sosi.sop = '1' THEN
+ v.out_sosi.sop := '0';
END IF;
+ IF q_reg.bsn_cnt = g_block_size-3 THEN
+ v.state := BSN;
+ v.dd_fresh := '1';
+ END IF;
WHEN FIRST_READ =>
- -- fills the first half of c_v and generates a output from it.
- v.out_ready := '0';
+ -- fills the first half of c_v and generates output from it.
+ v.out_ready := '0';
+ v.c_v(c_v_w-1 DOWNTO 0) := (OTHERS => '0');
v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
- v.dd_fresh := '0';
+ v.dd_fresh := '0';
v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v(g_out_data_w+v.a_of-1 DOWNTO v.a_of);
- v.out_sosi.valid := '1';
+ v.out_sosi.valid := '0';
v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := in_bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
-
+ v.out_sosi.sop := '1';
+ v.out_sosi.eop := '0';
+ v.bsn_cnt := 0;
+ v.op_data_cnt := q_reg.op_data_cnt+1;
+
+ IF v.dd_fresh = '1' AND v.valid_data = '0' THEN
+ -- put the delay data into the second half of c_v beceause these are now zeros
+ v.c_v(c_v_w-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '0';
+ v.valid_data := '1';
+ END IF;
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
- v.dd_fresh := '1';
+ v.dd_fresh := '1';
END IF;
- IF v.dd_fresh = '1' THEN
- v.state := SECOND_READ;
- ELSE
- v.state := IDLE;
+ v.state := READING;
+
+ WHEN BSN =>
+ -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added also increases the bsn output
+ v.out_sosi.valid := '0';
+ IF q_reg.dd_fresh = '1' AND q_reg.valid_data = '1' THEN
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt+1;
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.c_v(c_v_w-1 DOWNTO g_in_data_w);
+ -- put the delay data into the first half of c_v
+ v.c_v(c_v_w-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '0';
+ v.op_data_cnt := 0;
+ ELSIF q_reg.dd_fresh = '0' AND q_reg.valid_data = '1' THEN
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt+1;
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.c_v(c_v_w-1 DOWNTO g_in_data_w);
+ -- put zeros into the second half of c_v beceause dd_fresh is '0'
+ v.c_v(c_v_w-1 DOWNTO g_in_data_w) := (OTHERS => '0');
+ v.op_data_cnt := 0;
+ v.valid_data := '0';
+ ELSIF q_reg.dd_fresh = '1' AND q_reg.valid_data = '0' THEN
+ -- put the delay data into the second half of c_v beceause these are now zeros
+ v.c_v(c_v_w-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.c_v(c_v_w-1 DOWNTO g_in_data_w);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt+1;
+ v.dd_fresh := '0';
+ v.op_data_cnt := 0;
+ ELSIF q_reg.dd_fresh = '0' AND q_reg.valid_data = '0' AND (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of < g_in_data_w THEN
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt+1;
END IF;
- WHEN SECOND_READ =>
- -- fills the second half of c_v and generates a output from it.
- v.out_ready := '0';
- v.c_v(g_in_data_w*2-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
- v.dd_fresh := '0';
- v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v(g_out_data_w*2+q_reg.a_of-1 DOWNTO g_out_data_w+q_reg.a_of);
- v.out_sosi.valid := '1';
- v.bsn_cnt := 1;
- v.op_data_cnt := 2;
- v.sr_done := '1';
+ v.out_ready := '0';
+ v.out_sosi.eop := '1';
+ v.a_of := 0;
+ v.bsn_cnt := q_reg.bsn_cnt+1;
+ IF v.dd_fresh = '1' AND v.valid_data = '0' THEN
+ -- put the delay data into the second half of c_v beceause these are now zeros
+ v.c_v(c_v_w-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '0';
+ v.valid_data := '1';
+ END IF;
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
- v.dd_fresh := '1';
+ v.dd_fresh := '1';
END IF;
-
- IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
- v.state := OVER_HALF;
- ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
- v.state := IDLE;
+ IF g_bim+TO_UINT(in_bsn)-1 = TO_UINT(v.out_sosi.bsn) THEN
+ v.state := OFF;
ELSE
- v.state := READING;
+ v.state := READING;
END IF;
-
WHEN RESET =>
v := c_t_reg_init;
@@ -220,16 +319,20 @@ BEGIN
v.out_ready := '1';
v.out_sosi.valid := '0';
+ IF q_reg.dd_fresh = '1' AND q_reg.valid_data = '0' THEN
+ -- put the delay data into the second half of c_v beceause these are now zeros
+ v.c_v(c_v_w-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '0';
+ v.valid_data := '1';
+ END IF;
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '1';
END IF;
- IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '1' THEN
+ IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1'THEN
v.state := OVER_HALF;
- ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '0' THEN
- v.state := SECOND_READ;
ELSE
v.state := IDLE;
END IF;
@@ -240,7 +343,7 @@ BEGIN
-- the stamachine has a state off so it knows when to go to first read, it can't go to first read from IDLE
v.out_ready := '1';
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
-
+ v.out_sosi := c_dp_sosi_init;
IF in_sosi.valid = '1' THEN
v.state := FIRST_READ;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 422c72f091f333e4dc5d57da568da322917e21c5..881d039d0bfc8bbea512fcebfc74ac169d3b9801 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -1,3 +1,4 @@
+
-------------------------------------------------------------------------------
--
-- Copyright 2022
@@ -59,7 +60,7 @@ ARCHITECTURE tb OF tb_ddrctrl IS
-- constants for readability
CONSTANT c_ctrl_data_w : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr); -- 576
- CONSTANT c_in_data_w : NATURAL := g_nof_streams * g_data_w; -- output data with, 168
+ CONSTANT c_in_data_w : NATURAL := g_nof_streams*g_data_w; -- output data with, 168
-- constants for testbench
CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
@@ -128,7 +129,6 @@ ARCHITECTURE tb OF tb_ddrctrl IS
SIGNAL mm_rst : STD_LOGIC := '0';
SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- input data signal for ddrctrl_pack.vhd
SIGNAL stop_in : STD_LOGIC := '0';
- SIGNAL bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init);
-- testbench signal
@@ -158,6 +158,9 @@ BEGIN
-- excecuting test
p_test : PROCESS
+
+
+
BEGIN
-- start the test
@@ -180,29 +183,26 @@ BEGIN
make_data : FOR J IN 0 TO c_bim*g_block_size-1 LOOP
in_data_cnt <= in_data_cnt+1;
fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
- in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
- in_sosi_arr(I).valid <= '1';
- in_sosi_arr(I).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
IF bsn_cnt = g_block_size-1 THEN
- bsn_cnt <= 0;
- FOR I IN 0 TO g_nof_streams-1 LOOP
- in_sosi_arr(I).sop <= '1';
- in_sosi_arr(I).eop <= '0';
- END LOOP;
- bsn <= INCR_UVEC(bsn, 1);
+ IF I = 0 THEN
+ bsn_cnt <= 0;
+ END IF;
+ in_sosi_arr(I).sop <= '1';
+ in_sosi_arr(I).eop <= '0';
+ in_sosi_arr(I).bsn <= INCR_UVEC(in_sosi_arr(I).bsn, 1);
ELSE
- bsn_cnt <= bsn_cnt + 1;
- FOR I IN 0 TO g_nof_streams-1 LOOP
- in_sosi_arr(I).sop <= '0';
- END LOOP;
+ IF I = 0 THEN
+ bsn_cnt <= bsn_cnt + 1;
+ END IF;
+ in_sosi_arr(I).sop <= '0';
END IF;
IF bsn_cnt = g_block_size-2 THEN
- FOR I IN 0 TO g_nof_streams-1 LOOP
- in_sosi_arr(I).eop <= '1';
- END LOOP;
+ in_sosi_arr(I).eop <= '1';
END IF;
+ in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
+ in_sosi_arr(I).valid <= '1';
END LOOP;
- IF K = 1 AND J = c_bim*g_block_size-1 THEN
+ IF K = 0 AND J = c_bim*g_block_size-1 THEN
stop_in <= '1';
ELSE
stop_in <= '0';