From 85f8fb5d7af4994eef9230e8edc579bb6718899d Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 11 Jun 2014 12:41:18 +0000
Subject: [PATCH] Renamed gx_reconfig_4, 8, 12 into ip_stratixiv_gx_reconfig_4,
 8, 12, and added generic wrapper ip_stratixiv_gx_reconfig.vhd. The
 gx_reconfig_4 is used by the tse_sgmii_gx. The gx_reconfig_4, 8, 12 were were
 originaly in $UNB regenerated with Quartus v10.1, because the v9.1 version of
 ../gx_reconfig_12.vhd yielded a simulation error with the altera_mf.vhd model
 of v10.1.

---
 libraries/technology/ip_stratixiv/hdllib.cfg  |    5 +
 .../ip_stratixiv/ip_stratixiv_gx_reconfig.vhd |   79 +
 .../ip_stratixiv_gx_reconfig_12.vhd           | 1565 +++++++++++++++++
 .../ip_stratixiv_gx_reconfig_4.vhd            | 1509 ++++++++++++++++
 .../ip_stratixiv_gx_reconfig_8.vhd            | 1557 ++++++++++++++++
 5 files changed, 4715 insertions(+)
 create mode 100644 libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig.vhd
 create mode 100644 libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_12.vhd
 create mode 100644 libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_4.vhd
 create mode 100644 libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_8.vhd

diff --git a/libraries/technology/ip_stratixiv/hdllib.cfg b/libraries/technology/ip_stratixiv/hdllib.cfg
index 9efe515b29..0c60b2911b 100644
--- a/libraries/technology/ip_stratixiv/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/hdllib.cfg
@@ -22,6 +22,11 @@ synth_files =
     ip_stratixiv_asmi_parallel.vhd
     ip_stratixiv_remote_update.vhd
     
+    ip_stratixiv_gx_reconfig_4.vhd
+    ip_stratixiv_gx_reconfig_8.vhd
+    ip_stratixiv_gx_reconfig_12.vhd
+    ip_stratixiv_gx_reconfig.vhd
+    
     ip_stratixiv_gxb_reconfig_2.vhd
     ip_stratixiv_gxb_reconfig_4.vhd
     ip_stratixiv_gxb_reconfig_8.vhd
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig.vhd
new file mode 100644
index 0000000000..4a993b77f9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig.vhd
@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+-- Purpose : Create one gx_reconfig module for all ALTGX instances.
+   
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+ENTITY ip_stratixiv_gx_reconfig IS
+  GENERIC (
+    g_nof_gx        : NATURAL;
+    g_fromgxb_bus_w : NATURAL := 17;
+    g_togxb_bus_w   : NATURAL := 4
+  );
+  PORT (
+    reconfig_clk     : IN STD_LOGIC;
+    reconfig_fromgxb : IN STD_LOGIC_VECTOR(tech_ceil_div(g_nof_gx*g_fromgxb_bus_w, 4)-1 DOWNTO 0);
+    busy             : OUT STD_LOGIC;
+    reconfig_togxb   : OUT STD_LOGIC_VECTOR(g_togxb_bus_w-1 DOWNTO 0)
+  );
+END ip_stratixiv_gx_reconfig;
+
+
+ARCHITECTURE str OF ip_stratixiv_gx_reconfig IS
+BEGIN
+
+  gen_gx_reconfig_4 : IF g_nof_gx = 4 GENERATE  
+    u_gx_reconfig_4 : ENTITY work.ip_stratixiv_gx_reconfig_4
+    PORT MAP (
+      reconfig_clk        => reconfig_clk,
+      reconfig_fromgxb    => reconfig_fromgxb,
+      busy                => busy,
+      reconfig_togxb      => reconfig_togxb
+    );
+  END GENERATE;
+        
+  gen_gx_reconfig_8 : IF g_nof_gx = 8 GENERATE  
+    u_gx_reconfig_8 : ENTITY work.ip_stratixiv_gx_reconfig_8
+    PORT MAP (
+      reconfig_clk        => reconfig_clk,
+      reconfig_fromgxb    => reconfig_fromgxb,
+      busy                => busy,
+      reconfig_togxb      => reconfig_togxb
+    );
+  END GENERATE;
+
+  gen_gx_reconfig_12 : IF g_nof_gx = 12 GENERATE  
+    u_gx_reconfig_12 : ENTITY work.ip_stratixiv_gx_reconfig_12
+    PORT MAP (
+      reconfig_clk        => reconfig_clk,
+      reconfig_fromgxb    => reconfig_fromgxb,
+      busy                => busy,
+      reconfig_togxb      => reconfig_togxb
+    );
+  END GENERATE;
+
+END str;
+
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_12.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_12.vhd
new file mode 100644
index 0000000000..706dc71466
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_12.vhd
@@ -0,0 +1,1565 @@
+-- megafunction wizard: %ALTGX_RECONFIG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: alt2gxb_reconfig 
+
+-- ============================================================
+-- File Name: ip_stratixiv_gx_reconfig_12.vhd
+-- Megafunction Name(s):
+-- 			alt2gxb_reconfig
+--
+-- Simulation Library Files(s):
+-- 			altera_mf;lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.1 Build 153 11/29/2010 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+--alt2gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=12 NUMBER_OF_RECONFIG_PORTS=3 RECONFIG_FROMGXB_WIDTH=51 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
+--VERSION_BEGIN 10.1 cbx_alt2gxb_reconfig 2010:11:29:22:18:02:SJ cbx_alt_cal 2010:11:29:22:18:02:SJ cbx_alt_dprio 2010:11:29:22:18:02:SJ cbx_altsyncram 2010:11:29:22:18:02:SJ cbx_cycloneii 2010:11:29:22:18:02:SJ cbx_lpm_add_sub 2010:11:29:22:18:02:SJ cbx_lpm_compare 2010:11:29:22:18:02:SJ cbx_lpm_counter 2010:11:29:22:18:02:SJ cbx_lpm_decode 2010:11:29:22:18:02:SJ cbx_lpm_mux 2010:11:29:22:18:02:SJ cbx_lpm_shiftreg 2010:11:29:22:18:02:SJ cbx_mgl 2010:11:29:22:19:52:SJ cbx_stratix 2010:11:29:22:18:02:SJ cbx_stratixii 2010:11:29:22:18:02:SJ cbx_stratixiii 2010:11:29:22:18:02:SJ cbx_stratixv 2010:11:29:22:18:02:SJ cbx_util_mgl 2010:11:29:22:18:02:SJ  VERSION_END
+
+
+--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
+--VERSION_BEGIN 10.1 cbx_alt_dprio 2010:11:29:22:18:02:SJ cbx_cycloneii 2010:11:29:22:18:02:SJ cbx_lpm_add_sub 2010:11:29:22:18:02:SJ cbx_lpm_compare 2010:11:29:22:18:02:SJ cbx_lpm_counter 2010:11:29:22:18:02:SJ cbx_lpm_decode 2010:11:29:22:18:02:SJ cbx_lpm_shiftreg 2010:11:29:22:18:02:SJ cbx_mgl 2010:11:29:22:19:52:SJ cbx_stratix 2010:11:29:22:18:02:SJ cbx_stratixii 2010:11:29:22:18:02:SJ  VERSION_END
+
+ LIBRARY lpm;
+ USE lpm.all;
+
+--synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_stratixiv_gx_reconfig_12_alt_dprio_2vj IS 
+	 PORT 
+	 ( 
+		 address	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 busy	:	OUT  STD_LOGIC;
+		 datain	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => '0');
+		 dataout	:	OUT  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 dpclk	:	IN  STD_LOGIC;
+		 dpriodisable	:	OUT  STD_LOGIC;
+		 dprioin	:	OUT  STD_LOGIC;
+		 dprioload	:	OUT  STD_LOGIC;
+		 dprioout	:	IN  STD_LOGIC;
+		 quad_address	:	IN  STD_LOGIC_VECTOR (8 DOWNTO 0);
+		 rden	:	IN  STD_LOGIC := '0';
+		 reset	:	IN  STD_LOGIC := '0';
+		 wren	:	IN  STD_LOGIC := '0';
+		 wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+ END ip_stratixiv_gx_reconfig_12_alt_dprio_2vj;
+
+ ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_12_alt_dprio_2vj IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON";
+
+	 SIGNAL	 wire_addr_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_addr_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 addr_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF addr_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_addr_shift_reg_w_q_range222w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 in_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF in_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_rd_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 wire_rd_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 rd_out_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rd_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rd_out_data_shift_reg_w_q_range400w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_startup_cntr_d	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL	 startup_cntr	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF startup_cntr : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_startup_cntr_ena	:	STD_LOGIC_VECTOR(2 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range466w471w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range469w476w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range469w479w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range462w464w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range462w478w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range462w468w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range469w472w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range462w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range466w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range469w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 state_mc_reg	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF state_mc_reg : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_state_mc_reg_w_q_range60w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range79w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range95w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wr_out_data_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF wr_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_wr_out_data_shift_reg_w_q_range335w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb224w401w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb224w336w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_agb224w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_agb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_rd_data_output_cmpr_ageb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_alb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_state_mc_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_cnt_en	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_write_state45w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_q	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_decode_eq	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL	wire_dprioin_mux_dataout	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s0_to_063w64w65w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s1_to_082w83w84w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s2_to_098w99w100w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren51w74w87w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren51w74w75w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wr_addr_state223w226w227w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rd_data_output_state402w403w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_data_state337w338w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s0_to_063w64w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s1_to_082w83w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s2_to_098w99w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren51w74w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren51w52w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren51w69w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_w_lg_rden458w459w460w461w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_addr_state223w226w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state88w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state70w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state77w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state54w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state91w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rd_data_output_state402w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_data_state337w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_063w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_162w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_082w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_181w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_098w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_197w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_done456w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_idle457w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren51w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren_data73w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_rden458w459w460w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden49w50w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden458w459w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden49w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden458w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc86w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc68w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_166w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_185w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_1101w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_addr_state223w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren76w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren53w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren90w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  busy_state :	STD_LOGIC;
+	 SIGNAL  idle_state :	STD_LOGIC;
+	 SIGNAL  rd_addr_done :	STD_LOGIC;
+	 SIGNAL  rd_addr_state :	STD_LOGIC;
+	 SIGNAL  rd_data_done :	STD_LOGIC;
+	 SIGNAL  rd_data_input_state :	STD_LOGIC;
+	 SIGNAL  rd_data_output_state :	STD_LOGIC;
+	 SIGNAL  rd_data_state :	STD_LOGIC;
+	 SIGNAL  rdinc	:	STD_LOGIC;
+	 SIGNAL  read_state :	STD_LOGIC;
+	 SIGNAL  s0_to_0 :	STD_LOGIC;
+	 SIGNAL  s0_to_1 :	STD_LOGIC;
+	 SIGNAL  s1_to_0 :	STD_LOGIC;
+	 SIGNAL  s1_to_1 :	STD_LOGIC;
+	 SIGNAL  s2_to_0 :	STD_LOGIC;
+	 SIGNAL  s2_to_1 :	STD_LOGIC;
+	 SIGNAL  startup_done :	STD_LOGIC;
+	 SIGNAL  startup_idle :	STD_LOGIC;
+	 SIGNAL  wr_addr_done :	STD_LOGIC;
+	 SIGNAL  wr_addr_state :	STD_LOGIC;
+	 SIGNAL  wr_data_done :	STD_LOGIC;
+	 SIGNAL  wr_data_state :	STD_LOGIC;
+	 SIGNAL  write_state :	STD_LOGIC;
+	 COMPONENT  lpm_compare
+	 GENERIC 
+	 (
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_REPRESENTATION	:	STRING := "UNSIGNED";
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_compare"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aeb	:	OUT STD_LOGIC;
+		agb	:	OUT STD_LOGIC;
+		ageb	:	OUT STD_LOGIC;
+		alb	:	OUT STD_LOGIC;
+		aleb	:	OUT STD_LOGIC;
+		aneb	:	OUT STD_LOGIC;
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		dataa	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		datab	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_counter
+	 GENERIC 
+	 (
+		lpm_avalue	:	STRING := "0";
+		lpm_direction	:	STRING := "DEFAULT";
+		lpm_modulus	:	NATURAL := 0;
+		lpm_port_updown	:	STRING := "PORT_CONNECTIVITY";
+		lpm_pvalue	:	STRING := "0";
+		lpm_svalue	:	STRING := "0";
+		lpm_width	:	NATURAL;
+		lpm_type	:	STRING := "lpm_counter"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aload	:	IN STD_LOGIC := '0';
+		aset	:	IN STD_LOGIC := '0';
+		cin	:	IN STD_LOGIC := '1';
+		clk_en	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC;
+		cnt_en	:	IN STD_LOGIC := '1';
+		cout	:	OUT STD_LOGIC;
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		eq	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		q	:	OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
+		sclr	:	IN STD_LOGIC := '0';
+		sload	:	IN STD_LOGIC := '0';
+		sset	:	IN STD_LOGIC := '0';
+		updown	:	IN STD_LOGIC := '1'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_decode
+	 GENERIC 
+	 (
+		LPM_DECODES	:	NATURAL;
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_decode"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		enable	:	IN STD_LOGIC := '1';
+		eq	:	OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0)
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	wire_dprio_w_lg_w_lg_w_lg_s0_to_063w64w65w(0) <= wire_dprio_w_lg_w_lg_s0_to_063w64w(0) AND wire_state_mc_reg_w_q_range60w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s1_to_082w83w84w(0) <= wire_dprio_w_lg_w_lg_s1_to_082w83w(0) AND wire_state_mc_reg_w_q_range79w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s2_to_098w99w100w(0) <= wire_dprio_w_lg_w_lg_s2_to_098w99w(0) AND wire_state_mc_reg_w_q_range95w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren51w74w87w(0) <= wire_dprio_w_lg_w_lg_wren51w74w(0) AND wire_dprio_w_lg_rdinc86w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren51w74w75w(0) <= wire_dprio_w_lg_w_lg_wren51w74w(0) AND rden;
+	wire_dprio_w_lg_w_lg_w_lg_wr_addr_state223w226w227w(0) <= wire_dprio_w_lg_w_lg_wr_addr_state223w226w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_rd_data_output_state402w403w(0) <= wire_dprio_w_lg_rd_data_output_state402w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_wr_data_state337w338w(0) <= wire_dprio_w_lg_wr_data_state337w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_s0_to_063w64w(0) <= wire_dprio_w_lg_s0_to_063w(0) AND wire_dprio_w_lg_s0_to_162w(0);
+	wire_dprio_w_lg_w_lg_s1_to_082w83w(0) <= wire_dprio_w_lg_s1_to_082w(0) AND wire_dprio_w_lg_s1_to_181w(0);
+	wire_dprio_w_lg_w_lg_s2_to_098w99w(0) <= wire_dprio_w_lg_s2_to_098w(0) AND wire_dprio_w_lg_s2_to_197w(0);
+	wire_dprio_w_lg_w_lg_wren51w74w(0) <= wire_dprio_w_lg_wren51w(0) AND wire_dprio_w_lg_wren_data73w(0);
+	wire_dprio_w_lg_w_lg_wren51w52w(0) <= wire_dprio_w_lg_wren51w(0) AND wire_dprio_w_lg_w_lg_rden49w50w(0);
+	wire_dprio_w_lg_w_lg_wren51w69w(0) <= wire_dprio_w_lg_wren51w(0) AND wire_dprio_w_lg_rdinc68w(0);
+	wire_dprio_w_lg_w_lg_w_lg_w_lg_rden458w459w460w461w(0) <= wire_dprio_w_lg_w_lg_w_lg_rden458w459w460w(0) AND wire_dprio_w_lg_startup_done456w(0);
+	wire_dprio_w_lg_w_lg_wr_addr_state223w226w(0) <= wire_dprio_w_lg_wr_addr_state223w(0) AND wire_addr_shift_reg_w_q_range222w(0);
+	wire_dprio_w_lg_idle_state88w(0) <= idle_state AND wire_dprio_w_lg_w_lg_w_lg_wren51w74w87w(0);
+	wire_dprio_w_lg_idle_state70w(0) <= idle_state AND wire_dprio_w_lg_w_lg_wren51w69w(0);
+	wire_dprio_w_lg_idle_state77w(0) <= idle_state AND wire_dprio_w_lg_wren76w(0);
+	wire_dprio_w_lg_idle_state54w(0) <= idle_state AND wire_dprio_w_lg_wren53w(0);
+	wire_dprio_w_lg_idle_state91w(0) <= idle_state AND wire_dprio_w_lg_wren90w(0);
+	wire_dprio_w_lg_rd_data_output_state402w(0) <= rd_data_output_state AND wire_rd_out_data_shift_reg_w_q_range400w(0);
+	wire_dprio_w_lg_wr_data_state337w(0) <= wr_data_state AND wire_wr_out_data_shift_reg_w_q_range335w(0);
+	wire_dprio_w_lg_s0_to_063w(0) <= NOT s0_to_0;
+	wire_dprio_w_lg_s0_to_162w(0) <= NOT s0_to_1;
+	wire_dprio_w_lg_s1_to_082w(0) <= NOT s1_to_0;
+	wire_dprio_w_lg_s1_to_181w(0) <= NOT s1_to_1;
+	wire_dprio_w_lg_s2_to_098w(0) <= NOT s2_to_0;
+	wire_dprio_w_lg_s2_to_197w(0) <= NOT s2_to_1;
+	wire_dprio_w_lg_startup_done456w(0) <= NOT startup_done;
+	wire_dprio_w_lg_startup_idle457w(0) <= NOT startup_idle;
+	wire_dprio_w_lg_wren51w(0) <= NOT wren;
+	wire_dprio_w_lg_wren_data73w(0) <= NOT wren_data;
+	wire_dprio_w_lg_w_lg_w_lg_rden458w459w460w(0) <= wire_dprio_w_lg_w_lg_rden458w459w(0) OR wire_dprio_w_lg_startup_idle457w(0);
+	wire_dprio_w_lg_w_lg_rden49w50w(0) <= wire_dprio_w_lg_rden49w(0) OR wren_data;
+	wire_dprio_w_lg_w_lg_rden458w459w(0) <= wire_dprio_w_lg_rden458w(0) OR rdinc;
+	wire_dprio_w_lg_rden49w(0) <= rden OR rdinc;
+	wire_dprio_w_lg_rden458w(0) <= rden OR wren;
+	wire_dprio_w_lg_rdinc86w(0) <= rdinc OR rden;
+	wire_dprio_w_lg_rdinc68w(0) <= rdinc OR wren_data;
+	wire_dprio_w_lg_s0_to_166w(0) <= s0_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s0_to_063w64w65w(0);
+	wire_dprio_w_lg_s1_to_185w(0) <= s1_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s1_to_082w83w84w(0);
+	wire_dprio_w_lg_s2_to_1101w(0) <= s2_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s2_to_098w99w100w(0);
+	wire_dprio_w_lg_wr_addr_state223w(0) <= wr_addr_state OR rd_addr_state;
+	wire_dprio_w_lg_wren76w(0) <= wren OR wire_dprio_w_lg_w_lg_w_lg_wren51w74w75w(0);
+	wire_dprio_w_lg_wren53w(0) <= wren OR wire_dprio_w_lg_w_lg_wren51w52w(0);
+	wire_dprio_w_lg_wren90w(0) <= wren OR wren_data;
+	busy <= busy_state;
+	busy_state <= (write_state OR read_state);
+	dataout <= in_data_shift_reg;
+	dpriodisable <= (NOT wire_startup_cntr_w_lg_w_q_range469w479w(0));
+	dprioin <= wire_dprioin_mux_dataout;
+	dprioload <= (NOT (wire_startup_cntr_w_lg_w_q_range462w468w(0) AND (NOT startup_cntr(2))));
+	idle_state <= wire_state_mc_decode_eq(0);
+	rd_addr_done <= (rd_addr_state AND wire_state_mc_cmpr_aeb);
+	rd_addr_state <= (wire_state_mc_decode_eq(5) AND startup_done);
+	rd_data_done <= (rd_data_state AND wire_state_mc_cmpr_aeb);
+	rd_data_input_state <= (wire_rd_data_output_cmpr_ageb AND rd_data_state);
+	rd_data_output_state <= (wire_rd_data_output_cmpr_alb AND rd_data_state);
+	rd_data_state <= (wire_state_mc_decode_eq(7) AND startup_done);
+	rdinc <= '0';
+	read_state <= (rd_addr_state OR rd_data_state);
+	s0_to_0 <= ((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done));
+	s0_to_1 <= ((wire_dprio_w_lg_idle_state54w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s1_to_0 <= (((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state77w(0));
+	s1_to_1 <= ((wire_dprio_w_lg_idle_state70w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s2_to_0 <= ((((wr_addr_state AND wr_addr_done) OR (wr_data_state AND wr_data_done)) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state91w(0));
+	s2_to_1 <= (wire_dprio_w_lg_idle_state88w(0) OR (rd_addr_state AND rd_addr_done));
+	startup_done <= (wire_startup_cntr_w_lg_w_q_range469w476w(0) AND startup_cntr(1));
+	startup_idle <= (wire_startup_cntr_w_lg_w_q_range462w464w(0) AND (NOT (startup_cntr(2) XOR startup_cntr(1))));
+	wr_addr_done <= (wr_addr_state AND wire_state_mc_cmpr_aeb);
+	wr_addr_state <= (wire_state_mc_decode_eq(1) AND startup_done);
+	wr_data_done <= (wr_data_state AND wire_state_mc_cmpr_aeb);
+	wr_data_state <= (wire_state_mc_decode_eq(3) AND startup_done);
+	write_state <= (wr_addr_state OR wr_data_state);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(0) <= wire_addr_shift_reg_asdata(0);
+				ELSE addr_shift_reg(0) <= wire_addr_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(1) <= wire_addr_shift_reg_asdata(1);
+				ELSE addr_shift_reg(1) <= wire_addr_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(2) <= wire_addr_shift_reg_asdata(2);
+				ELSE addr_shift_reg(2) <= wire_addr_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(3) <= wire_addr_shift_reg_asdata(3);
+				ELSE addr_shift_reg(3) <= wire_addr_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(4) <= wire_addr_shift_reg_asdata(4);
+				ELSE addr_shift_reg(4) <= wire_addr_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(5) <= wire_addr_shift_reg_asdata(5);
+				ELSE addr_shift_reg(5) <= wire_addr_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(6) <= wire_addr_shift_reg_asdata(6);
+				ELSE addr_shift_reg(6) <= wire_addr_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(7) <= wire_addr_shift_reg_asdata(7);
+				ELSE addr_shift_reg(7) <= wire_addr_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(8) <= wire_addr_shift_reg_asdata(8);
+				ELSE addr_shift_reg(8) <= wire_addr_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(9) <= wire_addr_shift_reg_asdata(9);
+				ELSE addr_shift_reg(9) <= wire_addr_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(10) <= wire_addr_shift_reg_asdata(10);
+				ELSE addr_shift_reg(10) <= wire_addr_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(11) <= wire_addr_shift_reg_asdata(11);
+				ELSE addr_shift_reg(11) <= wire_addr_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(12) <= wire_addr_shift_reg_asdata(12);
+				ELSE addr_shift_reg(12) <= wire_addr_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(13) <= wire_addr_shift_reg_asdata(13);
+				ELSE addr_shift_reg(13) <= wire_addr_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(14) <= wire_addr_shift_reg_asdata(14);
+				ELSE addr_shift_reg(14) <= wire_addr_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(15) <= wire_addr_shift_reg_asdata(15);
+				ELSE addr_shift_reg(15) <= wire_addr_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(16) <= wire_addr_shift_reg_asdata(16);
+				ELSE addr_shift_reg(16) <= wire_addr_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(17) <= wire_addr_shift_reg_asdata(17);
+				ELSE addr_shift_reg(17) <= wire_addr_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(18) <= wire_addr_shift_reg_asdata(18);
+				ELSE addr_shift_reg(18) <= wire_addr_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(19) <= wire_addr_shift_reg_asdata(19);
+				ELSE addr_shift_reg(19) <= wire_addr_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(20) <= wire_addr_shift_reg_asdata(20);
+				ELSE addr_shift_reg(20) <= wire_addr_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(21) <= wire_addr_shift_reg_asdata(21);
+				ELSE addr_shift_reg(21) <= wire_addr_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(22) <= wire_addr_shift_reg_asdata(22);
+				ELSE addr_shift_reg(22) <= wire_addr_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(23) <= wire_addr_shift_reg_asdata(23);
+				ELSE addr_shift_reg(23) <= wire_addr_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(24) <= wire_addr_shift_reg_asdata(24);
+				ELSE addr_shift_reg(24) <= wire_addr_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(25) <= wire_addr_shift_reg_asdata(25);
+				ELSE addr_shift_reg(25) <= wire_addr_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(26) <= wire_addr_shift_reg_asdata(26);
+				ELSE addr_shift_reg(26) <= wire_addr_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(27) <= wire_addr_shift_reg_asdata(27);
+				ELSE addr_shift_reg(27) <= wire_addr_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(28) <= wire_addr_shift_reg_asdata(28);
+				ELSE addr_shift_reg(28) <= wire_addr_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(29) <= wire_addr_shift_reg_asdata(29);
+				ELSE addr_shift_reg(29) <= wire_addr_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(30) <= wire_addr_shift_reg_asdata(30);
+				ELSE addr_shift_reg(30) <= wire_addr_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(31) <= wire_addr_shift_reg_asdata(31);
+				ELSE addr_shift_reg(31) <= wire_addr_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_addr_shift_reg_asdata <= ( "00" & "00" & "0" & quad_address(8 DOWNTO 0) & "10" & address);
+	wire_addr_shift_reg_d <= ( addr_shift_reg(30 DOWNTO 0) & "0");
+	wire_addr_shift_reg_w_q_range222w(0) <= addr_shift_reg(31);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN in_data_shift_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+			IF (rd_data_input_state = '1') THEN in_data_shift_reg <= ( in_data_shift_reg(14 DOWNTO 0) & dprioout);
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_asdata(0);
+				ELSE rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_asdata(1);
+				ELSE rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_asdata(2);
+				ELSE rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_asdata(3);
+				ELSE rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_asdata(4);
+				ELSE rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_asdata(5);
+				ELSE rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_asdata(6);
+				ELSE rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_asdata(7);
+				ELSE rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_asdata(8);
+				ELSE rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_asdata(9);
+				ELSE rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_asdata(10);
+				ELSE rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_asdata(11);
+				ELSE rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_asdata(12);
+				ELSE rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_asdata(13);
+				ELSE rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_asdata(14);
+				ELSE rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_asdata(15);
+				ELSE rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_rd_out_data_shift_reg_asdata <= ( "00" & "1" & "1" & "0" & quad_address & "10");
+	wire_rd_out_data_shift_reg_d <= ( rd_out_data_shift_reg(14 DOWNTO 0) & "0");
+	wire_rd_out_data_shift_reg_w_q_range400w(0) <= rd_out_data_shift_reg(15);
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(0) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(0) <= '0';
+				ELSE startup_cntr(0) <= wire_startup_cntr_d(0);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(1) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(1) <= '0';
+				ELSE startup_cntr(1) <= wire_startup_cntr_d(1);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(2) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(2) <= '0';
+				ELSE startup_cntr(2) <= wire_startup_cntr_d(2);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_startup_cntr_d <= ( wire_startup_cntr_w_lg_w_q_range469w472w & wire_startup_cntr_w_lg_w_q_range462w468w & wire_startup_cntr_w_lg_w_q_range462w464w);
+	loop0 : FOR i IN 0 TO 2 GENERATE
+		wire_startup_cntr_ena(i) <= wire_dprio_w_lg_w_lg_w_lg_w_lg_rden458w459w460w461w(0);
+	END GENERATE loop0;
+	wire_startup_cntr_w_lg_w_q_range466w471w(0) <= wire_startup_cntr_w_q_range466w(0) AND wire_startup_cntr_w_q_range462w(0);
+	wire_startup_cntr_w_lg_w_q_range469w476w(0) <= wire_startup_cntr_w_q_range469w(0) AND wire_startup_cntr_w_lg_w_q_range462w464w(0);
+	wire_startup_cntr_w_lg_w_q_range469w479w(0) <= wire_startup_cntr_w_q_range469w(0) AND wire_startup_cntr_w_lg_w_q_range462w478w(0);
+	wire_startup_cntr_w_lg_w_q_range462w464w(0) <= NOT wire_startup_cntr_w_q_range462w(0);
+	wire_startup_cntr_w_lg_w_q_range462w478w(0) <= wire_startup_cntr_w_q_range462w(0) OR wire_startup_cntr_w_q_range466w(0);
+	wire_startup_cntr_w_lg_w_q_range462w468w(0) <= wire_startup_cntr_w_q_range462w(0) XOR wire_startup_cntr_w_q_range466w(0);
+	wire_startup_cntr_w_lg_w_q_range469w472w(0) <= wire_startup_cntr_w_q_range469w(0) XOR wire_startup_cntr_w_lg_w_q_range466w471w(0);
+	wire_startup_cntr_w_q_range462w(0) <= startup_cntr(0);
+	wire_startup_cntr_w_q_range466w(0) <= startup_cntr(1);
+	wire_startup_cntr_w_q_range469w(0) <= startup_cntr(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN state_mc_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN state_mc_reg <= ( wire_dprio_w_lg_s2_to_1101w & wire_dprio_w_lg_s1_to_185w & wire_dprio_w_lg_s0_to_166w);
+		END IF;
+	END PROCESS;
+	wire_state_mc_reg_w_q_range60w(0) <= state_mc_reg(0);
+	wire_state_mc_reg_w_q_range79w(0) <= state_mc_reg(1);
+	wire_state_mc_reg_w_q_range95w(0) <= state_mc_reg(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_asdata(0);
+				ELSE wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_asdata(1);
+				ELSE wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_asdata(2);
+				ELSE wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_asdata(3);
+				ELSE wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_asdata(4);
+				ELSE wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_asdata(5);
+				ELSE wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_asdata(6);
+				ELSE wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_asdata(7);
+				ELSE wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_asdata(8);
+				ELSE wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_asdata(9);
+				ELSE wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_asdata(10);
+				ELSE wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_asdata(11);
+				ELSE wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_asdata(12);
+				ELSE wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_asdata(13);
+				ELSE wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_asdata(14);
+				ELSE wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_asdata(15);
+				ELSE wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_asdata(16);
+				ELSE wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_asdata(17);
+				ELSE wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_asdata(18);
+				ELSE wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_asdata(19);
+				ELSE wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_asdata(20);
+				ELSE wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_asdata(21);
+				ELSE wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_asdata(22);
+				ELSE wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_asdata(23);
+				ELSE wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_asdata(24);
+				ELSE wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_asdata(25);
+				ELSE wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_asdata(26);
+				ELSE wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_asdata(27);
+				ELSE wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_asdata(28);
+				ELSE wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_asdata(29);
+				ELSE wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_asdata(30);
+				ELSE wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_asdata(31);
+				ELSE wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_wr_out_data_shift_reg_asdata <= ( "00" & "01" & "0" & quad_address(8 DOWNTO 0) & "10" & datain);
+	wire_wr_out_data_shift_reg_d <= ( wr_out_data_shift_reg(30 DOWNTO 0) & "0");
+	wire_wr_out_data_shift_reg_w_q_range335w(0) <= wr_out_data_shift_reg(31);
+	wire_pre_amble_cmpr_w_lg_w_lg_agb224w401w(0) <= wire_pre_amble_cmpr_w_lg_agb224w(0) AND rd_data_output_state;
+	wire_pre_amble_cmpr_w_lg_w_lg_agb224w336w(0) <= wire_pre_amble_cmpr_w_lg_agb224w(0) AND wr_data_state;
+	wire_pre_amble_cmpr_w_lg_agb224w(0) <= NOT wire_pre_amble_cmpr_agb;
+	wire_pre_amble_cmpr_datab <= "011111";
+	pre_amble_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_pre_amble_cmpr_aeb,
+		agb => wire_pre_amble_cmpr_agb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_pre_amble_cmpr_datab
+	  );
+	wire_rd_data_output_cmpr_datab <= "110000";
+	rd_data_output_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		ageb => wire_rd_data_output_cmpr_ageb,
+		alb => wire_rd_data_output_cmpr_alb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_rd_data_output_cmpr_datab
+	  );
+	wire_state_mc_cmpr_datab <= (OTHERS => '1');
+	state_mc_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_state_mc_cmpr_aeb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_state_mc_cmpr_datab
+	  );
+	wire_state_mc_counter_cnt_en <= wire_dprio_w_lg_write_state45w(0);
+	wire_dprio_w_lg_write_state45w(0) <= write_state OR read_state;
+	state_mc_counter :  lpm_counter
+	  GENERIC MAP (
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 6
+	  )
+	  PORT MAP ( 
+		clock => dpclk,
+		cnt_en => wire_state_mc_counter_cnt_en,
+		q => wire_state_mc_counter_q,
+		sclr => reset
+	  );
+	state_mc_decode :  lpm_decode
+	  GENERIC MAP (
+		LPM_DECODES => 8,
+		LPM_WIDTH => 3
+	  )
+	  PORT MAP ( 
+		data => state_mc_reg,
+		eq => wire_state_mc_decode_eq
+	  );
+	wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state223w226w227w(0) OR (wire_pre_amble_cmpr_w_lg_agb224w(0) AND wire_dprio_w_lg_wr_addr_state223w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state337w338w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb224w336w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state402w403w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb224w401w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
+
+ END RTL; --ip_stratixiv_gx_reconfig_12_alt_dprio_2vj
+
+
+--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=3 LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
+--VERSION_BEGIN 10.1 cbx_lpm_mux 2010:11:29:22:18:02:SJ cbx_mgl 2010:11:29:22:19:52:SJ  VERSION_END
+
+--synthesis_resources = lut 2 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_stratixiv_gx_reconfig_12_mux_66a IS 
+	 PORT 
+	 ( 
+		 data	:	IN  STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0');
+		 result	:	OUT  STD_LOGIC_VECTOR (0 DOWNTO 0);
+		 sel	:	IN  STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+ END ip_stratixiv_gx_reconfig_12_mux_66a;
+
+ ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_12_mux_66a IS
+
+	 SIGNAL  wire_dprioout_mux_w_lg_w_data_range486w487w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprioout_mux_w_lg_w_sel_range484w485w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  data0_wire :	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  data1_wire :	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  data2_wire :	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  result_node :	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprioout_mux_w_data_range486w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprioout_mux_w_sel_range484w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+	wire_dprioout_mux_w_lg_w_data_range486w487w(0) <= wire_dprioout_mux_w_data_range486w(0) AND wire_dprioout_mux_w_lg_w_sel_range484w485w(0);
+	wire_dprioout_mux_w_lg_w_sel_range484w485w(0) <= NOT wire_dprioout_mux_w_sel_range484w(0);
+	data0_wire(0) <= wire_dprioout_mux_w_lg_w_data_range486w487w(0);
+	data1_wire(0) <= (data(1) AND sel(0));
+	data2_wire(0) <= (data(2) AND sel(1));
+	result <= result_node;
+	result_node(0) <= (((data0_wire(0) OR data1_wire(0)) AND (NOT sel(1))) OR data2_wire(0));
+	wire_dprioout_mux_w_data_range486w(0) <= data(0);
+	wire_dprioout_mux_w_sel_range484w(0) <= sel(0);
+
+ END RTL; --ip_stratixiv_gx_reconfig_12_mux_66a
+
+ LIBRARY altera_mf;
+ USE altera_mf.all;
+
+--synthesis_resources = alt_cal 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 3 reg 114 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm IS 
+	 PORT 
+	 ( 
+		 busy	:	OUT  STD_LOGIC;
+		 reconfig_clk	:	IN  STD_LOGIC;
+		 reconfig_fromgxb	:	IN  STD_LOGIC_VECTOR (50 DOWNTO 0);
+		 reconfig_togxb	:	OUT  STD_LOGIC_VECTOR (3 DOWNTO 0)
+	 ); 
+ END ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm;
+
+ ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0";
+
+	 SIGNAL  wire_calibration_w_lg_busy12w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_w_lg_busy11w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_busy	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_addr	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_quad_addr	:	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  wire_calibration_reset	:	STD_LOGIC;
+	 SIGNAL  wire_w_lg_offset_cancellation_reset9w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_calibration_retain_addr	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_address	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_busy	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_datain	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dpriodisable	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioin	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioload	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy13w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy14w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 address_pres_reg	:	STD_LOGIC_VECTOR(11 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF address_pres_reg : SIGNAL IS "PRESERVE_REGISTER=ON";
+
+	 SIGNAL  wire_dprioout_mux_result	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  cal_busy :	STD_LOGIC;
+	 SIGNAL  cal_dprioout_wire :	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL  cal_testbuses :	STD_LOGIC_VECTOR (47 DOWNTO 0);
+	 SIGNAL  channel_address :	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL  dprio_address :	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  is_adce_all_control :	STD_LOGIC;
+	 SIGNAL  is_adce_continuous_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_one_time_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_standby_single_control :	STD_LOGIC;
+	 SIGNAL  offset_cancellation_reset	:	STD_LOGIC;
+	 SIGNAL  quad_address :	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  reconfig_reset_all :	STD_LOGIC;
+	 SIGNAL  start	:	STD_LOGIC;
+	 SIGNAL  transceiver_init	:	STD_LOGIC;
+	 COMPONENT  alt_cal
+	 GENERIC 
+	 (
+		CHANNEL_ADDRESS_WIDTH	:	NATURAL := 1;
+		NUMBER_OF_CHANNELS	:	NATURAL;
+		SIM_MODEL_MODE	:	STRING := "FALSE";
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "alt_cal"
+	 );
+	 PORT
+	 ( 
+		busy	:	OUT STD_LOGIC;
+		cal_error	:	OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
+		clock	:	IN STD_LOGIC;
+		dprio_addr	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_busy	:	IN STD_LOGIC;
+		dprio_datain	:	IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_dataout	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_rden	:	OUT STD_LOGIC;
+		dprio_wren	:	OUT STD_LOGIC;
+		quad_addr	:	OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+		remap_addr	:	IN STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
+		reset	:	IN STD_LOGIC := '0';
+		retain_addr	:	OUT STD_LOGIC;
+		start	:	IN STD_LOGIC := '0';
+		testbuses	:	IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS*4-1 DOWNTO 0) := (OTHERS => '0');
+		transceiver_init	:	IN STD_LOGIC
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  ip_stratixiv_gx_reconfig_12_alt_dprio_2vj
+	 PORT
+	 ( 
+		address	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		busy	:	OUT  STD_LOGIC;
+		datain	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
+		dataout	:	OUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dpclk	:	IN  STD_LOGIC;
+		dpriodisable	:	OUT  STD_LOGIC;
+		dprioin	:	OUT  STD_LOGIC;
+		dprioload	:	OUT  STD_LOGIC;
+		dprioout	:	IN  STD_LOGIC;
+		quad_address	:	IN  STD_LOGIC_VECTOR(8 DOWNTO 0);
+		rden	:	IN  STD_LOGIC := '0';
+		reset	:	IN  STD_LOGIC := '0';
+		wren	:	IN  STD_LOGIC := '0';
+		wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  ip_stratixiv_gx_reconfig_12_mux_66a
+	 PORT
+	 ( 
+		data	:	IN  STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
+		result	:	OUT  STD_LOGIC_VECTOR(0 DOWNTO 0);
+		sel	:	IN  STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	busy <= cal_busy;
+	cal_busy <= wire_calibration_busy;
+	cal_dprioout_wire <= ( reconfig_fromgxb(34) & reconfig_fromgxb(17) & reconfig_fromgxb(0));
+	cal_testbuses <= ( reconfig_fromgxb(50 DOWNTO 35) & reconfig_fromgxb(33 DOWNTO 18) & reconfig_fromgxb(16 DOWNTO 1));
+	channel_address <= wire_calibration_dprio_addr(14 DOWNTO 12);
+	dprio_address <= ( wire_calibration_dprio_addr(15) & address_pres_reg(2 DOWNTO 0) & wire_calibration_dprio_addr(11 DOWNTO 0));
+	offset_cancellation_reset <= '0';
+	quad_address <= wire_calibration_quad_addr;
+	reconfig_reset_all <= '0';
+	reconfig_togxb <= ( wire_calibration_busy & wire_dprio_dprioload & wire_dprio_dpriodisable & wire_dprio_dprioin);
+	start <= '0';
+	transceiver_init <= '0';
+	loop1 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy12w(i) <= wire_calibration_busy AND dprio_address(i);
+	END GENERATE loop1;
+	loop2 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy11w(i) <= wire_calibration_busy AND wire_calibration_dprio_dataout(i);
+	END GENERATE loop2;
+	wire_calibration_reset <= wire_w_lg_offset_cancellation_reset9w(0);
+	wire_w_lg_offset_cancellation_reset9w(0) <= offset_cancellation_reset OR reconfig_reset_all;
+	calibration :  alt_cal
+	  GENERIC MAP (
+		CHANNEL_ADDRESS_WIDTH => 4,
+		NUMBER_OF_CHANNELS => 12,
+		SIM_MODEL_MODE => "FALSE"
+	  )
+	  PORT MAP ( 
+		busy => wire_calibration_busy,
+		clock => reconfig_clk,
+		dprio_addr => wire_calibration_dprio_addr,
+		dprio_busy => wire_dprio_busy,
+		dprio_datain => wire_dprio_dataout,
+		dprio_dataout => wire_calibration_dprio_dataout,
+		dprio_rden => wire_calibration_dprio_rden,
+		dprio_wren => wire_calibration_dprio_wren,
+		quad_addr => wire_calibration_quad_addr,
+		remap_addr => address_pres_reg,
+		reset => wire_calibration_reset,
+		retain_addr => wire_calibration_retain_addr,
+		start => start,
+		testbuses => cal_testbuses,
+		transceiver_init => transceiver_init
+	  );
+	wire_dprio_address <= wire_calibration_w_lg_busy12w;
+	wire_dprio_datain <= wire_calibration_w_lg_busy11w;
+	wire_dprio_rden <= wire_calibration_w_lg_busy13w(0);
+	wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
+	wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
+	wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
+	dprio :  ip_stratixiv_gx_reconfig_12_alt_dprio_2vj
+	  PORT MAP ( 
+		address => wire_dprio_address,
+		busy => wire_dprio_busy,
+		datain => wire_dprio_datain,
+		dataout => wire_dprio_dataout,
+		dpclk => reconfig_clk,
+		dpriodisable => wire_dprio_dpriodisable,
+		dprioin => wire_dprio_dprioin,
+		dprioload => wire_dprio_dprioload,
+		dprioout => wire_dprioout_mux_result(0),
+		quad_address => address_pres_reg(11 DOWNTO 3),
+		rden => wire_dprio_rden,
+		reset => reconfig_reset_all,
+		wren => wire_dprio_wren,
+		wren_data => wire_calibration_retain_addr
+	  );
+	PROCESS (reconfig_clk, reconfig_reset_all)
+	BEGIN
+		IF (reconfig_reset_all = '1') THEN address_pres_reg <= (OTHERS => '0');
+		ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
+		END IF;
+	END PROCESS;
+	dprioout_mux :  ip_stratixiv_gx_reconfig_12_mux_66a
+	  PORT MAP ( 
+		data => cal_dprioout_wire,
+		result => wire_dprioout_mux_result,
+		sel => quad_address(1 DOWNTO 0)
+	  );
+
+ END RTL; --ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm
+--VALID FILE
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY ip_stratixiv_gx_reconfig_12 IS
+	PORT
+	(
+		reconfig_clk		: IN STD_LOGIC ;
+		reconfig_fromgxb		: IN STD_LOGIC_VECTOR (50 DOWNTO 0);
+		busy		: OUT STD_LOGIC ;
+		reconfig_togxb		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END ip_stratixiv_gx_reconfig_12;
+
+
+ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_12 IS
+
+	ATTRIBUTE synthesis_clearbox: natural;
+	ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
+	ATTRIBUTE clearbox_macroname: string;
+	ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt2gxb_reconfig";
+	ATTRIBUTE clearbox_defparam: string;
+	ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "cbx_blackbox_list=-lpm_mux;intended_device_family=Stratix IV;number_of_channels=12;number_of_reconfig_ports=3;enable_buf_cal=true;reconfig_fromgxb_width=51;reconfig_togxb_width=4;";
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+
+
+	COMPONENT ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm
+	PORT (
+			busy	: OUT STD_LOGIC ;
+			reconfig_clk	: IN STD_LOGIC ;
+			reconfig_fromgxb	: IN STD_LOGIC_VECTOR (50 DOWNTO 0);
+			reconfig_togxb	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	busy    <= sub_wire0;
+	reconfig_togxb    <= sub_wire1(3 DOWNTO 0);
+
+	ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm_component : ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm
+	PORT MAP (
+		reconfig_clk => reconfig_clk,
+		reconfig_fromgxb => reconfig_fromgxb,
+		busy => sub_wire0,
+		reconfig_togxb => sub_wire1
+	);
+
+
+
+END RTL;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
+-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
+-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: PMA NUMERIC "0"
+-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "12"
+-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "3"
+-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
+-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "51"
+-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
+-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 51 0 INPUT NODEFVAL "reconfig_fromgxb[50..0]"
+-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
+-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 51 0 reconfig_fromgxb 0 0 51 0
+-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_12.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_12.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_12.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_12.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_12_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_4.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_4.vhd
new file mode 100644
index 0000000000..7bb2d99f9e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_4.vhd
@@ -0,0 +1,1509 @@
+-- megafunction wizard: %ALTGX_RECONFIG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: alt2gxb_reconfig 
+
+-- ============================================================
+-- File Name: ip_stratixiv_gx_reconfig_4.vhd
+-- Megafunction Name(s):
+-- 			alt2gxb_reconfig
+--
+-- Simulation Library Files(s):
+-- 			altera_mf;lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.1 Build 153 11/29/2010 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+--alt2gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=4 NUMBER_OF_RECONFIG_PORTS=1 RECONFIG_FROMGXB_WIDTH=17 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
+--VERSION_BEGIN 10.1 cbx_alt2gxb_reconfig 2010:11:29:22:18:02:SJ cbx_alt_cal 2010:11:29:22:18:02:SJ cbx_alt_dprio 2010:11:29:22:18:02:SJ cbx_altsyncram 2010:11:29:22:18:02:SJ cbx_cycloneii 2010:11:29:22:18:02:SJ cbx_lpm_add_sub 2010:11:29:22:18:02:SJ cbx_lpm_compare 2010:11:29:22:18:02:SJ cbx_lpm_counter 2010:11:29:22:18:02:SJ cbx_lpm_decode 2010:11:29:22:18:02:SJ cbx_lpm_mux 2010:11:29:22:18:02:SJ cbx_lpm_shiftreg 2010:11:29:22:18:02:SJ cbx_mgl 2010:11:29:22:19:52:SJ cbx_stratix 2010:11:29:22:18:02:SJ cbx_stratixii 2010:11:29:22:18:02:SJ cbx_stratixiii 2010:11:29:22:18:02:SJ cbx_stratixv 2010:11:29:22:18:02:SJ cbx_util_mgl 2010:11:29:22:18:02:SJ  VERSION_END
+
+
+--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
+--VERSION_BEGIN 10.1 cbx_alt_dprio 2010:11:29:22:18:02:SJ cbx_cycloneii 2010:11:29:22:18:02:SJ cbx_lpm_add_sub 2010:11:29:22:18:02:SJ cbx_lpm_compare 2010:11:29:22:18:02:SJ cbx_lpm_counter 2010:11:29:22:18:02:SJ cbx_lpm_decode 2010:11:29:22:18:02:SJ cbx_lpm_shiftreg 2010:11:29:22:18:02:SJ cbx_mgl 2010:11:29:22:19:52:SJ cbx_stratix 2010:11:29:22:18:02:SJ cbx_stratixii 2010:11:29:22:18:02:SJ  VERSION_END
+
+ LIBRARY lpm;
+ USE lpm.all;
+
+--synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_stratixiv_gx_reconfig_4_alt_dprio_2vj IS 
+	 PORT 
+	 ( 
+		 address	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 busy	:	OUT  STD_LOGIC;
+		 datain	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => '0');
+		 dataout	:	OUT  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 dpclk	:	IN  STD_LOGIC;
+		 dpriodisable	:	OUT  STD_LOGIC;
+		 dprioin	:	OUT  STD_LOGIC;
+		 dprioload	:	OUT  STD_LOGIC;
+		 dprioout	:	IN  STD_LOGIC;
+		 quad_address	:	IN  STD_LOGIC_VECTOR (8 DOWNTO 0);
+		 rden	:	IN  STD_LOGIC := '0';
+		 reset	:	IN  STD_LOGIC := '0';
+		 wren	:	IN  STD_LOGIC := '0';
+		 wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+ END ip_stratixiv_gx_reconfig_4_alt_dprio_2vj;
+
+ ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_4_alt_dprio_2vj IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON";
+
+	 SIGNAL	 wire_addr_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_addr_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 addr_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF addr_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_addr_shift_reg_w_q_range213w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 in_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF in_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_rd_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 wire_rd_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 rd_out_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rd_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rd_out_data_shift_reg_w_q_range391w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_startup_cntr_d	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL	 startup_cntr	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF startup_cntr : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_startup_cntr_ena	:	STD_LOGIC_VECTOR(2 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range457w462w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range460w467w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range460w470w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range453w455w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range453w469w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range453w459w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range460w463w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range453w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range457w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range460w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 state_mc_reg	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF state_mc_reg : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_state_mc_reg_w_q_range51w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range70w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range86w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wr_out_data_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF wr_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_wr_out_data_shift_reg_w_q_range326w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb215w392w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb215w327w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_agb215w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_agb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_rd_data_output_cmpr_ageb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_alb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_state_mc_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_cnt_en	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_write_state36w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_q	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_decode_eq	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL	wire_dprioin_mux_dataout	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s0_to_054w55w56w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s1_to_073w74w75w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s2_to_089w90w91w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren42w65w78w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren42w65w66w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wr_addr_state214w217w218w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rd_data_output_state393w394w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_data_state328w329w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s0_to_054w55w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s1_to_073w74w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s2_to_089w90w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren42w65w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren42w43w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren42w60w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_w_lg_rden449w450w451w452w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_addr_state214w217w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state79w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state61w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state68w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state45w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state82w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rd_data_output_state393w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_data_state328w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_054w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_153w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_073w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_172w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_089w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_188w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_done447w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_idle448w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren42w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren_data64w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_rden449w450w451w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden40w41w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden449w450w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden40w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden449w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc77w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc59w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_157w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_176w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_192w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_addr_state214w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren67w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren44w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren81w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  busy_state :	STD_LOGIC;
+	 SIGNAL  idle_state :	STD_LOGIC;
+	 SIGNAL  rd_addr_done :	STD_LOGIC;
+	 SIGNAL  rd_addr_state :	STD_LOGIC;
+	 SIGNAL  rd_data_done :	STD_LOGIC;
+	 SIGNAL  rd_data_input_state :	STD_LOGIC;
+	 SIGNAL  rd_data_output_state :	STD_LOGIC;
+	 SIGNAL  rd_data_state :	STD_LOGIC;
+	 SIGNAL  rdinc	:	STD_LOGIC;
+	 SIGNAL  read_state :	STD_LOGIC;
+	 SIGNAL  s0_to_0 :	STD_LOGIC;
+	 SIGNAL  s0_to_1 :	STD_LOGIC;
+	 SIGNAL  s1_to_0 :	STD_LOGIC;
+	 SIGNAL  s1_to_1 :	STD_LOGIC;
+	 SIGNAL  s2_to_0 :	STD_LOGIC;
+	 SIGNAL  s2_to_1 :	STD_LOGIC;
+	 SIGNAL  startup_done :	STD_LOGIC;
+	 SIGNAL  startup_idle :	STD_LOGIC;
+	 SIGNAL  wr_addr_done :	STD_LOGIC;
+	 SIGNAL  wr_addr_state :	STD_LOGIC;
+	 SIGNAL  wr_data_done :	STD_LOGIC;
+	 SIGNAL  wr_data_state :	STD_LOGIC;
+	 SIGNAL  write_state :	STD_LOGIC;
+	 COMPONENT  lpm_compare
+	 GENERIC 
+	 (
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_REPRESENTATION	:	STRING := "UNSIGNED";
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_compare"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aeb	:	OUT STD_LOGIC;
+		agb	:	OUT STD_LOGIC;
+		ageb	:	OUT STD_LOGIC;
+		alb	:	OUT STD_LOGIC;
+		aleb	:	OUT STD_LOGIC;
+		aneb	:	OUT STD_LOGIC;
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		dataa	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		datab	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_counter
+	 GENERIC 
+	 (
+		lpm_avalue	:	STRING := "0";
+		lpm_direction	:	STRING := "DEFAULT";
+		lpm_modulus	:	NATURAL := 0;
+		lpm_port_updown	:	STRING := "PORT_CONNECTIVITY";
+		lpm_pvalue	:	STRING := "0";
+		lpm_svalue	:	STRING := "0";
+		lpm_width	:	NATURAL;
+		lpm_type	:	STRING := "lpm_counter"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aload	:	IN STD_LOGIC := '0';
+		aset	:	IN STD_LOGIC := '0';
+		cin	:	IN STD_LOGIC := '1';
+		clk_en	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC;
+		cnt_en	:	IN STD_LOGIC := '1';
+		cout	:	OUT STD_LOGIC;
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		eq	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		q	:	OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
+		sclr	:	IN STD_LOGIC := '0';
+		sload	:	IN STD_LOGIC := '0';
+		sset	:	IN STD_LOGIC := '0';
+		updown	:	IN STD_LOGIC := '1'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_decode
+	 GENERIC 
+	 (
+		LPM_DECODES	:	NATURAL;
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_decode"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		enable	:	IN STD_LOGIC := '1';
+		eq	:	OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0)
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	wire_dprio_w_lg_w_lg_w_lg_s0_to_054w55w56w(0) <= wire_dprio_w_lg_w_lg_s0_to_054w55w(0) AND wire_state_mc_reg_w_q_range51w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s1_to_073w74w75w(0) <= wire_dprio_w_lg_w_lg_s1_to_073w74w(0) AND wire_state_mc_reg_w_q_range70w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s2_to_089w90w91w(0) <= wire_dprio_w_lg_w_lg_s2_to_089w90w(0) AND wire_state_mc_reg_w_q_range86w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren42w65w78w(0) <= wire_dprio_w_lg_w_lg_wren42w65w(0) AND wire_dprio_w_lg_rdinc77w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren42w65w66w(0) <= wire_dprio_w_lg_w_lg_wren42w65w(0) AND rden;
+	wire_dprio_w_lg_w_lg_w_lg_wr_addr_state214w217w218w(0) <= wire_dprio_w_lg_w_lg_wr_addr_state214w217w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_rd_data_output_state393w394w(0) <= wire_dprio_w_lg_rd_data_output_state393w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_wr_data_state328w329w(0) <= wire_dprio_w_lg_wr_data_state328w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_s0_to_054w55w(0) <= wire_dprio_w_lg_s0_to_054w(0) AND wire_dprio_w_lg_s0_to_153w(0);
+	wire_dprio_w_lg_w_lg_s1_to_073w74w(0) <= wire_dprio_w_lg_s1_to_073w(0) AND wire_dprio_w_lg_s1_to_172w(0);
+	wire_dprio_w_lg_w_lg_s2_to_089w90w(0) <= wire_dprio_w_lg_s2_to_089w(0) AND wire_dprio_w_lg_s2_to_188w(0);
+	wire_dprio_w_lg_w_lg_wren42w65w(0) <= wire_dprio_w_lg_wren42w(0) AND wire_dprio_w_lg_wren_data64w(0);
+	wire_dprio_w_lg_w_lg_wren42w43w(0) <= wire_dprio_w_lg_wren42w(0) AND wire_dprio_w_lg_w_lg_rden40w41w(0);
+	wire_dprio_w_lg_w_lg_wren42w60w(0) <= wire_dprio_w_lg_wren42w(0) AND wire_dprio_w_lg_rdinc59w(0);
+	wire_dprio_w_lg_w_lg_w_lg_w_lg_rden449w450w451w452w(0) <= wire_dprio_w_lg_w_lg_w_lg_rden449w450w451w(0) AND wire_dprio_w_lg_startup_done447w(0);
+	wire_dprio_w_lg_w_lg_wr_addr_state214w217w(0) <= wire_dprio_w_lg_wr_addr_state214w(0) AND wire_addr_shift_reg_w_q_range213w(0);
+	wire_dprio_w_lg_idle_state79w(0) <= idle_state AND wire_dprio_w_lg_w_lg_w_lg_wren42w65w78w(0);
+	wire_dprio_w_lg_idle_state61w(0) <= idle_state AND wire_dprio_w_lg_w_lg_wren42w60w(0);
+	wire_dprio_w_lg_idle_state68w(0) <= idle_state AND wire_dprio_w_lg_wren67w(0);
+	wire_dprio_w_lg_idle_state45w(0) <= idle_state AND wire_dprio_w_lg_wren44w(0);
+	wire_dprio_w_lg_idle_state82w(0) <= idle_state AND wire_dprio_w_lg_wren81w(0);
+	wire_dprio_w_lg_rd_data_output_state393w(0) <= rd_data_output_state AND wire_rd_out_data_shift_reg_w_q_range391w(0);
+	wire_dprio_w_lg_wr_data_state328w(0) <= wr_data_state AND wire_wr_out_data_shift_reg_w_q_range326w(0);
+	wire_dprio_w_lg_s0_to_054w(0) <= NOT s0_to_0;
+	wire_dprio_w_lg_s0_to_153w(0) <= NOT s0_to_1;
+	wire_dprio_w_lg_s1_to_073w(0) <= NOT s1_to_0;
+	wire_dprio_w_lg_s1_to_172w(0) <= NOT s1_to_1;
+	wire_dprio_w_lg_s2_to_089w(0) <= NOT s2_to_0;
+	wire_dprio_w_lg_s2_to_188w(0) <= NOT s2_to_1;
+	wire_dprio_w_lg_startup_done447w(0) <= NOT startup_done;
+	wire_dprio_w_lg_startup_idle448w(0) <= NOT startup_idle;
+	wire_dprio_w_lg_wren42w(0) <= NOT wren;
+	wire_dprio_w_lg_wren_data64w(0) <= NOT wren_data;
+	wire_dprio_w_lg_w_lg_w_lg_rden449w450w451w(0) <= wire_dprio_w_lg_w_lg_rden449w450w(0) OR wire_dprio_w_lg_startup_idle448w(0);
+	wire_dprio_w_lg_w_lg_rden40w41w(0) <= wire_dprio_w_lg_rden40w(0) OR wren_data;
+	wire_dprio_w_lg_w_lg_rden449w450w(0) <= wire_dprio_w_lg_rden449w(0) OR rdinc;
+	wire_dprio_w_lg_rden40w(0) <= rden OR rdinc;
+	wire_dprio_w_lg_rden449w(0) <= rden OR wren;
+	wire_dprio_w_lg_rdinc77w(0) <= rdinc OR rden;
+	wire_dprio_w_lg_rdinc59w(0) <= rdinc OR wren_data;
+	wire_dprio_w_lg_s0_to_157w(0) <= s0_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s0_to_054w55w56w(0);
+	wire_dprio_w_lg_s1_to_176w(0) <= s1_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s1_to_073w74w75w(0);
+	wire_dprio_w_lg_s2_to_192w(0) <= s2_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s2_to_089w90w91w(0);
+	wire_dprio_w_lg_wr_addr_state214w(0) <= wr_addr_state OR rd_addr_state;
+	wire_dprio_w_lg_wren67w(0) <= wren OR wire_dprio_w_lg_w_lg_w_lg_wren42w65w66w(0);
+	wire_dprio_w_lg_wren44w(0) <= wren OR wire_dprio_w_lg_w_lg_wren42w43w(0);
+	wire_dprio_w_lg_wren81w(0) <= wren OR wren_data;
+	busy <= busy_state;
+	busy_state <= (write_state OR read_state);
+	dataout <= in_data_shift_reg;
+	dpriodisable <= (NOT wire_startup_cntr_w_lg_w_q_range460w470w(0));
+	dprioin <= wire_dprioin_mux_dataout;
+	dprioload <= (NOT (wire_startup_cntr_w_lg_w_q_range453w459w(0) AND (NOT startup_cntr(2))));
+	idle_state <= wire_state_mc_decode_eq(0);
+	rd_addr_done <= (rd_addr_state AND wire_state_mc_cmpr_aeb);
+	rd_addr_state <= (wire_state_mc_decode_eq(5) AND startup_done);
+	rd_data_done <= (rd_data_state AND wire_state_mc_cmpr_aeb);
+	rd_data_input_state <= (wire_rd_data_output_cmpr_ageb AND rd_data_state);
+	rd_data_output_state <= (wire_rd_data_output_cmpr_alb AND rd_data_state);
+	rd_data_state <= (wire_state_mc_decode_eq(7) AND startup_done);
+	rdinc <= '0';
+	read_state <= (rd_addr_state OR rd_data_state);
+	s0_to_0 <= ((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done));
+	s0_to_1 <= ((wire_dprio_w_lg_idle_state45w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s1_to_0 <= (((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state68w(0));
+	s1_to_1 <= ((wire_dprio_w_lg_idle_state61w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s2_to_0 <= ((((wr_addr_state AND wr_addr_done) OR (wr_data_state AND wr_data_done)) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state82w(0));
+	s2_to_1 <= (wire_dprio_w_lg_idle_state79w(0) OR (rd_addr_state AND rd_addr_done));
+	startup_done <= (wire_startup_cntr_w_lg_w_q_range460w467w(0) AND startup_cntr(1));
+	startup_idle <= (wire_startup_cntr_w_lg_w_q_range453w455w(0) AND (NOT (startup_cntr(2) XOR startup_cntr(1))));
+	wr_addr_done <= (wr_addr_state AND wire_state_mc_cmpr_aeb);
+	wr_addr_state <= (wire_state_mc_decode_eq(1) AND startup_done);
+	wr_data_done <= (wr_data_state AND wire_state_mc_cmpr_aeb);
+	wr_data_state <= (wire_state_mc_decode_eq(3) AND startup_done);
+	write_state <= (wr_addr_state OR wr_data_state);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(0) <= wire_addr_shift_reg_asdata(0);
+				ELSE addr_shift_reg(0) <= wire_addr_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(1) <= wire_addr_shift_reg_asdata(1);
+				ELSE addr_shift_reg(1) <= wire_addr_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(2) <= wire_addr_shift_reg_asdata(2);
+				ELSE addr_shift_reg(2) <= wire_addr_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(3) <= wire_addr_shift_reg_asdata(3);
+				ELSE addr_shift_reg(3) <= wire_addr_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(4) <= wire_addr_shift_reg_asdata(4);
+				ELSE addr_shift_reg(4) <= wire_addr_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(5) <= wire_addr_shift_reg_asdata(5);
+				ELSE addr_shift_reg(5) <= wire_addr_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(6) <= wire_addr_shift_reg_asdata(6);
+				ELSE addr_shift_reg(6) <= wire_addr_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(7) <= wire_addr_shift_reg_asdata(7);
+				ELSE addr_shift_reg(7) <= wire_addr_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(8) <= wire_addr_shift_reg_asdata(8);
+				ELSE addr_shift_reg(8) <= wire_addr_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(9) <= wire_addr_shift_reg_asdata(9);
+				ELSE addr_shift_reg(9) <= wire_addr_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(10) <= wire_addr_shift_reg_asdata(10);
+				ELSE addr_shift_reg(10) <= wire_addr_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(11) <= wire_addr_shift_reg_asdata(11);
+				ELSE addr_shift_reg(11) <= wire_addr_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(12) <= wire_addr_shift_reg_asdata(12);
+				ELSE addr_shift_reg(12) <= wire_addr_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(13) <= wire_addr_shift_reg_asdata(13);
+				ELSE addr_shift_reg(13) <= wire_addr_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(14) <= wire_addr_shift_reg_asdata(14);
+				ELSE addr_shift_reg(14) <= wire_addr_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(15) <= wire_addr_shift_reg_asdata(15);
+				ELSE addr_shift_reg(15) <= wire_addr_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(16) <= wire_addr_shift_reg_asdata(16);
+				ELSE addr_shift_reg(16) <= wire_addr_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(17) <= wire_addr_shift_reg_asdata(17);
+				ELSE addr_shift_reg(17) <= wire_addr_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(18) <= wire_addr_shift_reg_asdata(18);
+				ELSE addr_shift_reg(18) <= wire_addr_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(19) <= wire_addr_shift_reg_asdata(19);
+				ELSE addr_shift_reg(19) <= wire_addr_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(20) <= wire_addr_shift_reg_asdata(20);
+				ELSE addr_shift_reg(20) <= wire_addr_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(21) <= wire_addr_shift_reg_asdata(21);
+				ELSE addr_shift_reg(21) <= wire_addr_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(22) <= wire_addr_shift_reg_asdata(22);
+				ELSE addr_shift_reg(22) <= wire_addr_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(23) <= wire_addr_shift_reg_asdata(23);
+				ELSE addr_shift_reg(23) <= wire_addr_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(24) <= wire_addr_shift_reg_asdata(24);
+				ELSE addr_shift_reg(24) <= wire_addr_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(25) <= wire_addr_shift_reg_asdata(25);
+				ELSE addr_shift_reg(25) <= wire_addr_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(26) <= wire_addr_shift_reg_asdata(26);
+				ELSE addr_shift_reg(26) <= wire_addr_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(27) <= wire_addr_shift_reg_asdata(27);
+				ELSE addr_shift_reg(27) <= wire_addr_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(28) <= wire_addr_shift_reg_asdata(28);
+				ELSE addr_shift_reg(28) <= wire_addr_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(29) <= wire_addr_shift_reg_asdata(29);
+				ELSE addr_shift_reg(29) <= wire_addr_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(30) <= wire_addr_shift_reg_asdata(30);
+				ELSE addr_shift_reg(30) <= wire_addr_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(31) <= wire_addr_shift_reg_asdata(31);
+				ELSE addr_shift_reg(31) <= wire_addr_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_addr_shift_reg_asdata <= ( "00" & "00" & "0" & quad_address(8 DOWNTO 0) & "10" & address);
+	wire_addr_shift_reg_d <= ( addr_shift_reg(30 DOWNTO 0) & "0");
+	wire_addr_shift_reg_w_q_range213w(0) <= addr_shift_reg(31);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN in_data_shift_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+			IF (rd_data_input_state = '1') THEN in_data_shift_reg <= ( in_data_shift_reg(14 DOWNTO 0) & dprioout);
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_asdata(0);
+				ELSE rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_asdata(1);
+				ELSE rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_asdata(2);
+				ELSE rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_asdata(3);
+				ELSE rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_asdata(4);
+				ELSE rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_asdata(5);
+				ELSE rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_asdata(6);
+				ELSE rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_asdata(7);
+				ELSE rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_asdata(8);
+				ELSE rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_asdata(9);
+				ELSE rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_asdata(10);
+				ELSE rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_asdata(11);
+				ELSE rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_asdata(12);
+				ELSE rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_asdata(13);
+				ELSE rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_asdata(14);
+				ELSE rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_asdata(15);
+				ELSE rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_rd_out_data_shift_reg_asdata <= ( "00" & "1" & "1" & "0" & quad_address & "10");
+	wire_rd_out_data_shift_reg_d <= ( rd_out_data_shift_reg(14 DOWNTO 0) & "0");
+	wire_rd_out_data_shift_reg_w_q_range391w(0) <= rd_out_data_shift_reg(15);
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(0) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(0) <= '0';
+				ELSE startup_cntr(0) <= wire_startup_cntr_d(0);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(1) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(1) <= '0';
+				ELSE startup_cntr(1) <= wire_startup_cntr_d(1);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(2) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(2) <= '0';
+				ELSE startup_cntr(2) <= wire_startup_cntr_d(2);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_startup_cntr_d <= ( wire_startup_cntr_w_lg_w_q_range460w463w & wire_startup_cntr_w_lg_w_q_range453w459w & wire_startup_cntr_w_lg_w_q_range453w455w);
+	loop0 : FOR i IN 0 TO 2 GENERATE
+		wire_startup_cntr_ena(i) <= wire_dprio_w_lg_w_lg_w_lg_w_lg_rden449w450w451w452w(0);
+	END GENERATE loop0;
+	wire_startup_cntr_w_lg_w_q_range457w462w(0) <= wire_startup_cntr_w_q_range457w(0) AND wire_startup_cntr_w_q_range453w(0);
+	wire_startup_cntr_w_lg_w_q_range460w467w(0) <= wire_startup_cntr_w_q_range460w(0) AND wire_startup_cntr_w_lg_w_q_range453w455w(0);
+	wire_startup_cntr_w_lg_w_q_range460w470w(0) <= wire_startup_cntr_w_q_range460w(0) AND wire_startup_cntr_w_lg_w_q_range453w469w(0);
+	wire_startup_cntr_w_lg_w_q_range453w455w(0) <= NOT wire_startup_cntr_w_q_range453w(0);
+	wire_startup_cntr_w_lg_w_q_range453w469w(0) <= wire_startup_cntr_w_q_range453w(0) OR wire_startup_cntr_w_q_range457w(0);
+	wire_startup_cntr_w_lg_w_q_range453w459w(0) <= wire_startup_cntr_w_q_range453w(0) XOR wire_startup_cntr_w_q_range457w(0);
+	wire_startup_cntr_w_lg_w_q_range460w463w(0) <= wire_startup_cntr_w_q_range460w(0) XOR wire_startup_cntr_w_lg_w_q_range457w462w(0);
+	wire_startup_cntr_w_q_range453w(0) <= startup_cntr(0);
+	wire_startup_cntr_w_q_range457w(0) <= startup_cntr(1);
+	wire_startup_cntr_w_q_range460w(0) <= startup_cntr(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN state_mc_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN state_mc_reg <= ( wire_dprio_w_lg_s2_to_192w & wire_dprio_w_lg_s1_to_176w & wire_dprio_w_lg_s0_to_157w);
+		END IF;
+	END PROCESS;
+	wire_state_mc_reg_w_q_range51w(0) <= state_mc_reg(0);
+	wire_state_mc_reg_w_q_range70w(0) <= state_mc_reg(1);
+	wire_state_mc_reg_w_q_range86w(0) <= state_mc_reg(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_asdata(0);
+				ELSE wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_asdata(1);
+				ELSE wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_asdata(2);
+				ELSE wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_asdata(3);
+				ELSE wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_asdata(4);
+				ELSE wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_asdata(5);
+				ELSE wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_asdata(6);
+				ELSE wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_asdata(7);
+				ELSE wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_asdata(8);
+				ELSE wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_asdata(9);
+				ELSE wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_asdata(10);
+				ELSE wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_asdata(11);
+				ELSE wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_asdata(12);
+				ELSE wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_asdata(13);
+				ELSE wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_asdata(14);
+				ELSE wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_asdata(15);
+				ELSE wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_asdata(16);
+				ELSE wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_asdata(17);
+				ELSE wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_asdata(18);
+				ELSE wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_asdata(19);
+				ELSE wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_asdata(20);
+				ELSE wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_asdata(21);
+				ELSE wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_asdata(22);
+				ELSE wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_asdata(23);
+				ELSE wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_asdata(24);
+				ELSE wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_asdata(25);
+				ELSE wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_asdata(26);
+				ELSE wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_asdata(27);
+				ELSE wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_asdata(28);
+				ELSE wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_asdata(29);
+				ELSE wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_asdata(30);
+				ELSE wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_asdata(31);
+				ELSE wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_wr_out_data_shift_reg_asdata <= ( "00" & "01" & "0" & quad_address(8 DOWNTO 0) & "10" & datain);
+	wire_wr_out_data_shift_reg_d <= ( wr_out_data_shift_reg(30 DOWNTO 0) & "0");
+	wire_wr_out_data_shift_reg_w_q_range326w(0) <= wr_out_data_shift_reg(31);
+	wire_pre_amble_cmpr_w_lg_w_lg_agb215w392w(0) <= wire_pre_amble_cmpr_w_lg_agb215w(0) AND rd_data_output_state;
+	wire_pre_amble_cmpr_w_lg_w_lg_agb215w327w(0) <= wire_pre_amble_cmpr_w_lg_agb215w(0) AND wr_data_state;
+	wire_pre_amble_cmpr_w_lg_agb215w(0) <= NOT wire_pre_amble_cmpr_agb;
+	wire_pre_amble_cmpr_datab <= "011111";
+	pre_amble_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_pre_amble_cmpr_aeb,
+		agb => wire_pre_amble_cmpr_agb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_pre_amble_cmpr_datab
+	  );
+	wire_rd_data_output_cmpr_datab <= "110000";
+	rd_data_output_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		ageb => wire_rd_data_output_cmpr_ageb,
+		alb => wire_rd_data_output_cmpr_alb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_rd_data_output_cmpr_datab
+	  );
+	wire_state_mc_cmpr_datab <= (OTHERS => '1');
+	state_mc_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_state_mc_cmpr_aeb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_state_mc_cmpr_datab
+	  );
+	wire_state_mc_counter_cnt_en <= wire_dprio_w_lg_write_state36w(0);
+	wire_dprio_w_lg_write_state36w(0) <= write_state OR read_state;
+	state_mc_counter :  lpm_counter
+	  GENERIC MAP (
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 6
+	  )
+	  PORT MAP ( 
+		clock => dpclk,
+		cnt_en => wire_state_mc_counter_cnt_en,
+		q => wire_state_mc_counter_q,
+		sclr => reset
+	  );
+	state_mc_decode :  lpm_decode
+	  GENERIC MAP (
+		LPM_DECODES => 8,
+		LPM_WIDTH => 3
+	  )
+	  PORT MAP ( 
+		data => state_mc_reg,
+		eq => wire_state_mc_decode_eq
+	  );
+	wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state214w217w218w(0) OR (wire_pre_amble_cmpr_w_lg_agb215w(0) AND wire_dprio_w_lg_wr_addr_state214w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state328w329w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb215w327w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state393w394w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb215w392w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
+
+ END RTL; --ip_stratixiv_gx_reconfig_4_alt_dprio_2vj
+
+ LIBRARY altera_mf;
+ USE altera_mf.all;
+
+--synthesis_resources = alt_cal 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 114 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm IS 
+	 PORT 
+	 ( 
+		 busy	:	OUT  STD_LOGIC;
+		 reconfig_clk	:	IN  STD_LOGIC;
+		 reconfig_fromgxb	:	IN  STD_LOGIC_VECTOR (16 DOWNTO 0);
+		 reconfig_togxb	:	OUT  STD_LOGIC_VECTOR (3 DOWNTO 0)
+	 ); 
+ END ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm;
+
+ ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0";
+
+	 SIGNAL  wire_calibration_w_lg_busy12w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_w_lg_busy11w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_busy	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_addr	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_quad_addr	:	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  wire_calibration_reset	:	STD_LOGIC;
+	 SIGNAL  wire_w_lg_offset_cancellation_reset9w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_calibration_retain_addr	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_address	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_busy	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_datain	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dpriodisable	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioin	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioload	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy13w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy14w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 address_pres_reg	:	STD_LOGIC_VECTOR(11 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF address_pres_reg : SIGNAL IS "PRESERVE_REGISTER=ON";
+
+	 SIGNAL  cal_busy :	STD_LOGIC;
+	 SIGNAL  cal_dprioout_wire :	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  cal_testbuses :	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  channel_address :	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL  dprio_address :	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  is_adce_all_control :	STD_LOGIC;
+	 SIGNAL  is_adce_continuous_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_one_time_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_standby_single_control :	STD_LOGIC;
+	 SIGNAL  offset_cancellation_reset	:	STD_LOGIC;
+	 SIGNAL  quad_address :	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  reconfig_reset_all :	STD_LOGIC;
+	 SIGNAL  start	:	STD_LOGIC;
+	 SIGNAL  transceiver_init	:	STD_LOGIC;
+	 COMPONENT  alt_cal
+	 GENERIC 
+	 (
+		CHANNEL_ADDRESS_WIDTH	:	NATURAL := 1;
+		NUMBER_OF_CHANNELS	:	NATURAL;
+		SIM_MODEL_MODE	:	STRING := "FALSE";
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "alt_cal"
+	 );
+	 PORT
+	 ( 
+		busy	:	OUT STD_LOGIC;
+		cal_error	:	OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
+		clock	:	IN STD_LOGIC;
+		dprio_addr	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_busy	:	IN STD_LOGIC;
+		dprio_datain	:	IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_dataout	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_rden	:	OUT STD_LOGIC;
+		dprio_wren	:	OUT STD_LOGIC;
+		quad_addr	:	OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+		remap_addr	:	IN STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
+		reset	:	IN STD_LOGIC := '0';
+		retain_addr	:	OUT STD_LOGIC;
+		start	:	IN STD_LOGIC := '0';
+		testbuses	:	IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS*4-1 DOWNTO 0) := (OTHERS => '0');
+		transceiver_init	:	IN STD_LOGIC
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  ip_stratixiv_gx_reconfig_4_alt_dprio_2vj
+	 PORT
+	 ( 
+		address	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		busy	:	OUT  STD_LOGIC;
+		datain	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
+		dataout	:	OUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dpclk	:	IN  STD_LOGIC;
+		dpriodisable	:	OUT  STD_LOGIC;
+		dprioin	:	OUT  STD_LOGIC;
+		dprioload	:	OUT  STD_LOGIC;
+		dprioout	:	IN  STD_LOGIC;
+		quad_address	:	IN  STD_LOGIC_VECTOR(8 DOWNTO 0);
+		rden	:	IN  STD_LOGIC := '0';
+		reset	:	IN  STD_LOGIC := '0';
+		wren	:	IN  STD_LOGIC := '0';
+		wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	busy <= cal_busy;
+	cal_busy <= wire_calibration_busy;
+	cal_dprioout_wire(0) <= ( reconfig_fromgxb(0));
+	cal_testbuses <= ( reconfig_fromgxb(16 DOWNTO 1));
+	channel_address <= wire_calibration_dprio_addr(14 DOWNTO 12);
+	dprio_address <= ( wire_calibration_dprio_addr(15) & address_pres_reg(2 DOWNTO 0) & wire_calibration_dprio_addr(11 DOWNTO 0));
+	offset_cancellation_reset <= '0';
+	quad_address <= wire_calibration_quad_addr;
+	reconfig_reset_all <= '0';
+	reconfig_togxb <= ( wire_calibration_busy & wire_dprio_dprioload & wire_dprio_dpriodisable & wire_dprio_dprioin);
+	start <= '0';
+	transceiver_init <= '0';
+	loop1 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy12w(i) <= wire_calibration_busy AND dprio_address(i);
+	END GENERATE loop1;
+	loop2 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy11w(i) <= wire_calibration_busy AND wire_calibration_dprio_dataout(i);
+	END GENERATE loop2;
+	wire_calibration_reset <= wire_w_lg_offset_cancellation_reset9w(0);
+	wire_w_lg_offset_cancellation_reset9w(0) <= offset_cancellation_reset OR reconfig_reset_all;
+	calibration :  alt_cal
+	  GENERIC MAP (
+		CHANNEL_ADDRESS_WIDTH => 2,
+		NUMBER_OF_CHANNELS => 4,
+		SIM_MODEL_MODE => "FALSE"
+	  )
+	  PORT MAP ( 
+		busy => wire_calibration_busy,
+		clock => reconfig_clk,
+		dprio_addr => wire_calibration_dprio_addr,
+		dprio_busy => wire_dprio_busy,
+		dprio_datain => wire_dprio_dataout,
+		dprio_dataout => wire_calibration_dprio_dataout,
+		dprio_rden => wire_calibration_dprio_rden,
+		dprio_wren => wire_calibration_dprio_wren,
+		quad_addr => wire_calibration_quad_addr,
+		remap_addr => address_pres_reg,
+		reset => wire_calibration_reset,
+		retain_addr => wire_calibration_retain_addr,
+		start => start,
+		testbuses => cal_testbuses,
+		transceiver_init => transceiver_init
+	  );
+	wire_dprio_address <= wire_calibration_w_lg_busy12w;
+	wire_dprio_datain <= wire_calibration_w_lg_busy11w;
+	wire_dprio_rden <= wire_calibration_w_lg_busy13w(0);
+	wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
+	wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
+	wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
+	dprio :  ip_stratixiv_gx_reconfig_4_alt_dprio_2vj
+	  PORT MAP ( 
+		address => wire_dprio_address,
+		busy => wire_dprio_busy,
+		datain => wire_dprio_datain,
+		dataout => wire_dprio_dataout,
+		dpclk => reconfig_clk,
+		dpriodisable => wire_dprio_dpriodisable,
+		dprioin => wire_dprio_dprioin,
+		dprioload => wire_dprio_dprioload,
+		dprioout => cal_dprioout_wire(0),
+		quad_address => address_pres_reg(11 DOWNTO 3),
+		rden => wire_dprio_rden,
+		reset => reconfig_reset_all,
+		wren => wire_dprio_wren,
+		wren_data => wire_calibration_retain_addr
+	  );
+	PROCESS (reconfig_clk, reconfig_reset_all)
+	BEGIN
+		IF (reconfig_reset_all = '1') THEN address_pres_reg <= (OTHERS => '0');
+		ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
+		END IF;
+	END PROCESS;
+
+ END RTL; --ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm
+--VALID FILE
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY ip_stratixiv_gx_reconfig_4 IS
+	PORT
+	(
+		reconfig_clk		: IN STD_LOGIC ;
+		reconfig_fromgxb		: IN STD_LOGIC_VECTOR (16 DOWNTO 0);
+		busy		: OUT STD_LOGIC ;
+		reconfig_togxb		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END ip_stratixiv_gx_reconfig_4;
+
+
+ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_4 IS
+
+	ATTRIBUTE synthesis_clearbox: natural;
+	ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
+	ATTRIBUTE clearbox_macroname: string;
+	ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt2gxb_reconfig";
+	ATTRIBUTE clearbox_defparam: string;
+	ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "cbx_blackbox_list=-lpm_mux;intended_device_family=Stratix IV;number_of_channels=4;number_of_reconfig_ports=1;enable_buf_cal=true;reconfig_fromgxb_width=17;reconfig_togxb_width=4;";
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+
+
+	COMPONENT ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm
+	PORT (
+			busy	: OUT STD_LOGIC ;
+			reconfig_clk	: IN STD_LOGIC ;
+			reconfig_fromgxb	: IN STD_LOGIC_VECTOR (16 DOWNTO 0);
+			reconfig_togxb	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	busy    <= sub_wire0;
+	reconfig_togxb    <= sub_wire1(3 DOWNTO 0);
+
+	ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm_component : ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm
+	PORT MAP (
+		reconfig_clk => reconfig_clk,
+		reconfig_fromgxb => reconfig_fromgxb,
+		busy => sub_wire0,
+		reconfig_togxb => sub_wire1
+	);
+
+
+
+END RTL;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
+-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
+-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: PMA NUMERIC "0"
+-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
+-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
+-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "17"
+-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
+-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 INPUT NODEFVAL "reconfig_fromgxb[16..0]"
+-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
+-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 17 0 reconfig_fromgxb 0 0 17 0
+-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_4.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_4.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_8.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_8.vhd
new file mode 100644
index 0000000000..be0e6f4423
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_8.vhd
@@ -0,0 +1,1557 @@
+-- megafunction wizard: %ALTGX_RECONFIG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: alt2gxb_reconfig 
+
+-- ============================================================
+-- File Name: ip_stratixiv_gx_reconfig_8.vhd
+-- Megafunction Name(s):
+-- 			alt2gxb_reconfig
+--
+-- Simulation Library Files(s):
+-- 			altera_mf;lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.1 Build 153 11/29/2010 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+--alt2gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=8 NUMBER_OF_RECONFIG_PORTS=2 RECONFIG_FROMGXB_WIDTH=34 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
+--VERSION_BEGIN 10.1 cbx_alt2gxb_reconfig 2010:11:29:22:18:02:SJ cbx_alt_cal 2010:11:29:22:18:02:SJ cbx_alt_dprio 2010:11:29:22:18:02:SJ cbx_altsyncram 2010:11:29:22:18:02:SJ cbx_cycloneii 2010:11:29:22:18:02:SJ cbx_lpm_add_sub 2010:11:29:22:18:02:SJ cbx_lpm_compare 2010:11:29:22:18:02:SJ cbx_lpm_counter 2010:11:29:22:18:02:SJ cbx_lpm_decode 2010:11:29:22:18:02:SJ cbx_lpm_mux 2010:11:29:22:18:02:SJ cbx_lpm_shiftreg 2010:11:29:22:18:02:SJ cbx_mgl 2010:11:29:22:19:52:SJ cbx_stratix 2010:11:29:22:18:02:SJ cbx_stratixii 2010:11:29:22:18:02:SJ cbx_stratixiii 2010:11:29:22:18:02:SJ cbx_stratixv 2010:11:29:22:18:02:SJ cbx_util_mgl 2010:11:29:22:18:02:SJ  VERSION_END
+
+
+--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
+--VERSION_BEGIN 10.1 cbx_alt_dprio 2010:11:29:22:18:02:SJ cbx_cycloneii 2010:11:29:22:18:02:SJ cbx_lpm_add_sub 2010:11:29:22:18:02:SJ cbx_lpm_compare 2010:11:29:22:18:02:SJ cbx_lpm_counter 2010:11:29:22:18:02:SJ cbx_lpm_decode 2010:11:29:22:18:02:SJ cbx_lpm_shiftreg 2010:11:29:22:18:02:SJ cbx_mgl 2010:11:29:22:19:52:SJ cbx_stratix 2010:11:29:22:18:02:SJ cbx_stratixii 2010:11:29:22:18:02:SJ  VERSION_END
+
+ LIBRARY lpm;
+ USE lpm.all;
+
+--synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_stratixiv_gx_reconfig_8_alt_dprio_2vj IS 
+	 PORT 
+	 ( 
+		 address	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 busy	:	OUT  STD_LOGIC;
+		 datain	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => '0');
+		 dataout	:	OUT  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 dpclk	:	IN  STD_LOGIC;
+		 dpriodisable	:	OUT  STD_LOGIC;
+		 dprioin	:	OUT  STD_LOGIC;
+		 dprioload	:	OUT  STD_LOGIC;
+		 dprioout	:	IN  STD_LOGIC;
+		 quad_address	:	IN  STD_LOGIC_VECTOR (8 DOWNTO 0);
+		 rden	:	IN  STD_LOGIC := '0';
+		 reset	:	IN  STD_LOGIC := '0';
+		 wren	:	IN  STD_LOGIC := '0';
+		 wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+ END ip_stratixiv_gx_reconfig_8_alt_dprio_2vj;
+
+ ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_8_alt_dprio_2vj IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON";
+
+	 SIGNAL	 wire_addr_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_addr_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 addr_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF addr_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_addr_shift_reg_w_q_range218w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 in_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF in_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_rd_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 wire_rd_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 rd_out_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rd_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rd_out_data_shift_reg_w_q_range396w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_startup_cntr_d	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL	 startup_cntr	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF startup_cntr : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_startup_cntr_ena	:	STD_LOGIC_VECTOR(2 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range462w467w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range465w472w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range465w475w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range458w460w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range458w474w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range458w464w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range465w468w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range458w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range462w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range465w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 state_mc_reg	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF state_mc_reg : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_state_mc_reg_w_q_range56w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range75w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range91w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wr_out_data_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF wr_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_wr_out_data_shift_reg_w_q_range331w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb220w397w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb220w332w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_agb220w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_agb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_rd_data_output_cmpr_ageb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_alb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_state_mc_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_cnt_en	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_write_state41w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_q	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_decode_eq	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL	wire_dprioin_mux_dataout	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s0_to_059w60w61w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s1_to_078w79w80w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s2_to_094w95w96w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren47w70w83w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren47w70w71w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wr_addr_state219w222w223w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rd_data_output_state398w399w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_data_state333w334w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s0_to_059w60w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s1_to_078w79w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s2_to_094w95w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren47w70w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren47w48w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren47w65w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_w_lg_rden454w455w456w457w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_addr_state219w222w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state84w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state66w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state73w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state50w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state87w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rd_data_output_state398w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_data_state333w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_059w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_158w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_078w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_177w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_094w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_193w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_done452w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_idle453w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren47w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren_data69w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_rden454w455w456w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden45w46w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden454w455w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden45w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden454w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc82w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc64w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_162w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_181w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_197w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_addr_state219w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren72w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren49w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren86w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  busy_state :	STD_LOGIC;
+	 SIGNAL  idle_state :	STD_LOGIC;
+	 SIGNAL  rd_addr_done :	STD_LOGIC;
+	 SIGNAL  rd_addr_state :	STD_LOGIC;
+	 SIGNAL  rd_data_done :	STD_LOGIC;
+	 SIGNAL  rd_data_input_state :	STD_LOGIC;
+	 SIGNAL  rd_data_output_state :	STD_LOGIC;
+	 SIGNAL  rd_data_state :	STD_LOGIC;
+	 SIGNAL  rdinc	:	STD_LOGIC;
+	 SIGNAL  read_state :	STD_LOGIC;
+	 SIGNAL  s0_to_0 :	STD_LOGIC;
+	 SIGNAL  s0_to_1 :	STD_LOGIC;
+	 SIGNAL  s1_to_0 :	STD_LOGIC;
+	 SIGNAL  s1_to_1 :	STD_LOGIC;
+	 SIGNAL  s2_to_0 :	STD_LOGIC;
+	 SIGNAL  s2_to_1 :	STD_LOGIC;
+	 SIGNAL  startup_done :	STD_LOGIC;
+	 SIGNAL  startup_idle :	STD_LOGIC;
+	 SIGNAL  wr_addr_done :	STD_LOGIC;
+	 SIGNAL  wr_addr_state :	STD_LOGIC;
+	 SIGNAL  wr_data_done :	STD_LOGIC;
+	 SIGNAL  wr_data_state :	STD_LOGIC;
+	 SIGNAL  write_state :	STD_LOGIC;
+	 COMPONENT  lpm_compare
+	 GENERIC 
+	 (
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_REPRESENTATION	:	STRING := "UNSIGNED";
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_compare"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aeb	:	OUT STD_LOGIC;
+		agb	:	OUT STD_LOGIC;
+		ageb	:	OUT STD_LOGIC;
+		alb	:	OUT STD_LOGIC;
+		aleb	:	OUT STD_LOGIC;
+		aneb	:	OUT STD_LOGIC;
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		dataa	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		datab	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_counter
+	 GENERIC 
+	 (
+		lpm_avalue	:	STRING := "0";
+		lpm_direction	:	STRING := "DEFAULT";
+		lpm_modulus	:	NATURAL := 0;
+		lpm_port_updown	:	STRING := "PORT_CONNECTIVITY";
+		lpm_pvalue	:	STRING := "0";
+		lpm_svalue	:	STRING := "0";
+		lpm_width	:	NATURAL;
+		lpm_type	:	STRING := "lpm_counter"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aload	:	IN STD_LOGIC := '0';
+		aset	:	IN STD_LOGIC := '0';
+		cin	:	IN STD_LOGIC := '1';
+		clk_en	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC;
+		cnt_en	:	IN STD_LOGIC := '1';
+		cout	:	OUT STD_LOGIC;
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		eq	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		q	:	OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
+		sclr	:	IN STD_LOGIC := '0';
+		sload	:	IN STD_LOGIC := '0';
+		sset	:	IN STD_LOGIC := '0';
+		updown	:	IN STD_LOGIC := '1'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_decode
+	 GENERIC 
+	 (
+		LPM_DECODES	:	NATURAL;
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_decode"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		enable	:	IN STD_LOGIC := '1';
+		eq	:	OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0)
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	wire_dprio_w_lg_w_lg_w_lg_s0_to_059w60w61w(0) <= wire_dprio_w_lg_w_lg_s0_to_059w60w(0) AND wire_state_mc_reg_w_q_range56w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s1_to_078w79w80w(0) <= wire_dprio_w_lg_w_lg_s1_to_078w79w(0) AND wire_state_mc_reg_w_q_range75w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s2_to_094w95w96w(0) <= wire_dprio_w_lg_w_lg_s2_to_094w95w(0) AND wire_state_mc_reg_w_q_range91w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren47w70w83w(0) <= wire_dprio_w_lg_w_lg_wren47w70w(0) AND wire_dprio_w_lg_rdinc82w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren47w70w71w(0) <= wire_dprio_w_lg_w_lg_wren47w70w(0) AND rden;
+	wire_dprio_w_lg_w_lg_w_lg_wr_addr_state219w222w223w(0) <= wire_dprio_w_lg_w_lg_wr_addr_state219w222w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_rd_data_output_state398w399w(0) <= wire_dprio_w_lg_rd_data_output_state398w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_wr_data_state333w334w(0) <= wire_dprio_w_lg_wr_data_state333w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_s0_to_059w60w(0) <= wire_dprio_w_lg_s0_to_059w(0) AND wire_dprio_w_lg_s0_to_158w(0);
+	wire_dprio_w_lg_w_lg_s1_to_078w79w(0) <= wire_dprio_w_lg_s1_to_078w(0) AND wire_dprio_w_lg_s1_to_177w(0);
+	wire_dprio_w_lg_w_lg_s2_to_094w95w(0) <= wire_dprio_w_lg_s2_to_094w(0) AND wire_dprio_w_lg_s2_to_193w(0);
+	wire_dprio_w_lg_w_lg_wren47w70w(0) <= wire_dprio_w_lg_wren47w(0) AND wire_dprio_w_lg_wren_data69w(0);
+	wire_dprio_w_lg_w_lg_wren47w48w(0) <= wire_dprio_w_lg_wren47w(0) AND wire_dprio_w_lg_w_lg_rden45w46w(0);
+	wire_dprio_w_lg_w_lg_wren47w65w(0) <= wire_dprio_w_lg_wren47w(0) AND wire_dprio_w_lg_rdinc64w(0);
+	wire_dprio_w_lg_w_lg_w_lg_w_lg_rden454w455w456w457w(0) <= wire_dprio_w_lg_w_lg_w_lg_rden454w455w456w(0) AND wire_dprio_w_lg_startup_done452w(0);
+	wire_dprio_w_lg_w_lg_wr_addr_state219w222w(0) <= wire_dprio_w_lg_wr_addr_state219w(0) AND wire_addr_shift_reg_w_q_range218w(0);
+	wire_dprio_w_lg_idle_state84w(0) <= idle_state AND wire_dprio_w_lg_w_lg_w_lg_wren47w70w83w(0);
+	wire_dprio_w_lg_idle_state66w(0) <= idle_state AND wire_dprio_w_lg_w_lg_wren47w65w(0);
+	wire_dprio_w_lg_idle_state73w(0) <= idle_state AND wire_dprio_w_lg_wren72w(0);
+	wire_dprio_w_lg_idle_state50w(0) <= idle_state AND wire_dprio_w_lg_wren49w(0);
+	wire_dprio_w_lg_idle_state87w(0) <= idle_state AND wire_dprio_w_lg_wren86w(0);
+	wire_dprio_w_lg_rd_data_output_state398w(0) <= rd_data_output_state AND wire_rd_out_data_shift_reg_w_q_range396w(0);
+	wire_dprio_w_lg_wr_data_state333w(0) <= wr_data_state AND wire_wr_out_data_shift_reg_w_q_range331w(0);
+	wire_dprio_w_lg_s0_to_059w(0) <= NOT s0_to_0;
+	wire_dprio_w_lg_s0_to_158w(0) <= NOT s0_to_1;
+	wire_dprio_w_lg_s1_to_078w(0) <= NOT s1_to_0;
+	wire_dprio_w_lg_s1_to_177w(0) <= NOT s1_to_1;
+	wire_dprio_w_lg_s2_to_094w(0) <= NOT s2_to_0;
+	wire_dprio_w_lg_s2_to_193w(0) <= NOT s2_to_1;
+	wire_dprio_w_lg_startup_done452w(0) <= NOT startup_done;
+	wire_dprio_w_lg_startup_idle453w(0) <= NOT startup_idle;
+	wire_dprio_w_lg_wren47w(0) <= NOT wren;
+	wire_dprio_w_lg_wren_data69w(0) <= NOT wren_data;
+	wire_dprio_w_lg_w_lg_w_lg_rden454w455w456w(0) <= wire_dprio_w_lg_w_lg_rden454w455w(0) OR wire_dprio_w_lg_startup_idle453w(0);
+	wire_dprio_w_lg_w_lg_rden45w46w(0) <= wire_dprio_w_lg_rden45w(0) OR wren_data;
+	wire_dprio_w_lg_w_lg_rden454w455w(0) <= wire_dprio_w_lg_rden454w(0) OR rdinc;
+	wire_dprio_w_lg_rden45w(0) <= rden OR rdinc;
+	wire_dprio_w_lg_rden454w(0) <= rden OR wren;
+	wire_dprio_w_lg_rdinc82w(0) <= rdinc OR rden;
+	wire_dprio_w_lg_rdinc64w(0) <= rdinc OR wren_data;
+	wire_dprio_w_lg_s0_to_162w(0) <= s0_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s0_to_059w60w61w(0);
+	wire_dprio_w_lg_s1_to_181w(0) <= s1_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s1_to_078w79w80w(0);
+	wire_dprio_w_lg_s2_to_197w(0) <= s2_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s2_to_094w95w96w(0);
+	wire_dprio_w_lg_wr_addr_state219w(0) <= wr_addr_state OR rd_addr_state;
+	wire_dprio_w_lg_wren72w(0) <= wren OR wire_dprio_w_lg_w_lg_w_lg_wren47w70w71w(0);
+	wire_dprio_w_lg_wren49w(0) <= wren OR wire_dprio_w_lg_w_lg_wren47w48w(0);
+	wire_dprio_w_lg_wren86w(0) <= wren OR wren_data;
+	busy <= busy_state;
+	busy_state <= (write_state OR read_state);
+	dataout <= in_data_shift_reg;
+	dpriodisable <= (NOT wire_startup_cntr_w_lg_w_q_range465w475w(0));
+	dprioin <= wire_dprioin_mux_dataout;
+	dprioload <= (NOT (wire_startup_cntr_w_lg_w_q_range458w464w(0) AND (NOT startup_cntr(2))));
+	idle_state <= wire_state_mc_decode_eq(0);
+	rd_addr_done <= (rd_addr_state AND wire_state_mc_cmpr_aeb);
+	rd_addr_state <= (wire_state_mc_decode_eq(5) AND startup_done);
+	rd_data_done <= (rd_data_state AND wire_state_mc_cmpr_aeb);
+	rd_data_input_state <= (wire_rd_data_output_cmpr_ageb AND rd_data_state);
+	rd_data_output_state <= (wire_rd_data_output_cmpr_alb AND rd_data_state);
+	rd_data_state <= (wire_state_mc_decode_eq(7) AND startup_done);
+	rdinc <= '0';
+	read_state <= (rd_addr_state OR rd_data_state);
+	s0_to_0 <= ((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done));
+	s0_to_1 <= ((wire_dprio_w_lg_idle_state50w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s1_to_0 <= (((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state73w(0));
+	s1_to_1 <= ((wire_dprio_w_lg_idle_state66w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s2_to_0 <= ((((wr_addr_state AND wr_addr_done) OR (wr_data_state AND wr_data_done)) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state87w(0));
+	s2_to_1 <= (wire_dprio_w_lg_idle_state84w(0) OR (rd_addr_state AND rd_addr_done));
+	startup_done <= (wire_startup_cntr_w_lg_w_q_range465w472w(0) AND startup_cntr(1));
+	startup_idle <= (wire_startup_cntr_w_lg_w_q_range458w460w(0) AND (NOT (startup_cntr(2) XOR startup_cntr(1))));
+	wr_addr_done <= (wr_addr_state AND wire_state_mc_cmpr_aeb);
+	wr_addr_state <= (wire_state_mc_decode_eq(1) AND startup_done);
+	wr_data_done <= (wr_data_state AND wire_state_mc_cmpr_aeb);
+	wr_data_state <= (wire_state_mc_decode_eq(3) AND startup_done);
+	write_state <= (wr_addr_state OR wr_data_state);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(0) <= wire_addr_shift_reg_asdata(0);
+				ELSE addr_shift_reg(0) <= wire_addr_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(1) <= wire_addr_shift_reg_asdata(1);
+				ELSE addr_shift_reg(1) <= wire_addr_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(2) <= wire_addr_shift_reg_asdata(2);
+				ELSE addr_shift_reg(2) <= wire_addr_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(3) <= wire_addr_shift_reg_asdata(3);
+				ELSE addr_shift_reg(3) <= wire_addr_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(4) <= wire_addr_shift_reg_asdata(4);
+				ELSE addr_shift_reg(4) <= wire_addr_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(5) <= wire_addr_shift_reg_asdata(5);
+				ELSE addr_shift_reg(5) <= wire_addr_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(6) <= wire_addr_shift_reg_asdata(6);
+				ELSE addr_shift_reg(6) <= wire_addr_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(7) <= wire_addr_shift_reg_asdata(7);
+				ELSE addr_shift_reg(7) <= wire_addr_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(8) <= wire_addr_shift_reg_asdata(8);
+				ELSE addr_shift_reg(8) <= wire_addr_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(9) <= wire_addr_shift_reg_asdata(9);
+				ELSE addr_shift_reg(9) <= wire_addr_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(10) <= wire_addr_shift_reg_asdata(10);
+				ELSE addr_shift_reg(10) <= wire_addr_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(11) <= wire_addr_shift_reg_asdata(11);
+				ELSE addr_shift_reg(11) <= wire_addr_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(12) <= wire_addr_shift_reg_asdata(12);
+				ELSE addr_shift_reg(12) <= wire_addr_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(13) <= wire_addr_shift_reg_asdata(13);
+				ELSE addr_shift_reg(13) <= wire_addr_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(14) <= wire_addr_shift_reg_asdata(14);
+				ELSE addr_shift_reg(14) <= wire_addr_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(15) <= wire_addr_shift_reg_asdata(15);
+				ELSE addr_shift_reg(15) <= wire_addr_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(16) <= wire_addr_shift_reg_asdata(16);
+				ELSE addr_shift_reg(16) <= wire_addr_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(17) <= wire_addr_shift_reg_asdata(17);
+				ELSE addr_shift_reg(17) <= wire_addr_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(18) <= wire_addr_shift_reg_asdata(18);
+				ELSE addr_shift_reg(18) <= wire_addr_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(19) <= wire_addr_shift_reg_asdata(19);
+				ELSE addr_shift_reg(19) <= wire_addr_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(20) <= wire_addr_shift_reg_asdata(20);
+				ELSE addr_shift_reg(20) <= wire_addr_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(21) <= wire_addr_shift_reg_asdata(21);
+				ELSE addr_shift_reg(21) <= wire_addr_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(22) <= wire_addr_shift_reg_asdata(22);
+				ELSE addr_shift_reg(22) <= wire_addr_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(23) <= wire_addr_shift_reg_asdata(23);
+				ELSE addr_shift_reg(23) <= wire_addr_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(24) <= wire_addr_shift_reg_asdata(24);
+				ELSE addr_shift_reg(24) <= wire_addr_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(25) <= wire_addr_shift_reg_asdata(25);
+				ELSE addr_shift_reg(25) <= wire_addr_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(26) <= wire_addr_shift_reg_asdata(26);
+				ELSE addr_shift_reg(26) <= wire_addr_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(27) <= wire_addr_shift_reg_asdata(27);
+				ELSE addr_shift_reg(27) <= wire_addr_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(28) <= wire_addr_shift_reg_asdata(28);
+				ELSE addr_shift_reg(28) <= wire_addr_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(29) <= wire_addr_shift_reg_asdata(29);
+				ELSE addr_shift_reg(29) <= wire_addr_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(30) <= wire_addr_shift_reg_asdata(30);
+				ELSE addr_shift_reg(30) <= wire_addr_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(31) <= wire_addr_shift_reg_asdata(31);
+				ELSE addr_shift_reg(31) <= wire_addr_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_addr_shift_reg_asdata <= ( "00" & "00" & "0" & quad_address(8 DOWNTO 0) & "10" & address);
+	wire_addr_shift_reg_d <= ( addr_shift_reg(30 DOWNTO 0) & "0");
+	wire_addr_shift_reg_w_q_range218w(0) <= addr_shift_reg(31);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN in_data_shift_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+			IF (rd_data_input_state = '1') THEN in_data_shift_reg <= ( in_data_shift_reg(14 DOWNTO 0) & dprioout);
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_asdata(0);
+				ELSE rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_asdata(1);
+				ELSE rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_asdata(2);
+				ELSE rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_asdata(3);
+				ELSE rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_asdata(4);
+				ELSE rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_asdata(5);
+				ELSE rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_asdata(6);
+				ELSE rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_asdata(7);
+				ELSE rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_asdata(8);
+				ELSE rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_asdata(9);
+				ELSE rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_asdata(10);
+				ELSE rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_asdata(11);
+				ELSE rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_asdata(12);
+				ELSE rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_asdata(13);
+				ELSE rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_asdata(14);
+				ELSE rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_asdata(15);
+				ELSE rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_rd_out_data_shift_reg_asdata <= ( "00" & "1" & "1" & "0" & quad_address & "10");
+	wire_rd_out_data_shift_reg_d <= ( rd_out_data_shift_reg(14 DOWNTO 0) & "0");
+	wire_rd_out_data_shift_reg_w_q_range396w(0) <= rd_out_data_shift_reg(15);
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(0) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(0) <= '0';
+				ELSE startup_cntr(0) <= wire_startup_cntr_d(0);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(1) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(1) <= '0';
+				ELSE startup_cntr(1) <= wire_startup_cntr_d(1);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(2) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(2) <= '0';
+				ELSE startup_cntr(2) <= wire_startup_cntr_d(2);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_startup_cntr_d <= ( wire_startup_cntr_w_lg_w_q_range465w468w & wire_startup_cntr_w_lg_w_q_range458w464w & wire_startup_cntr_w_lg_w_q_range458w460w);
+	loop0 : FOR i IN 0 TO 2 GENERATE
+		wire_startup_cntr_ena(i) <= wire_dprio_w_lg_w_lg_w_lg_w_lg_rden454w455w456w457w(0);
+	END GENERATE loop0;
+	wire_startup_cntr_w_lg_w_q_range462w467w(0) <= wire_startup_cntr_w_q_range462w(0) AND wire_startup_cntr_w_q_range458w(0);
+	wire_startup_cntr_w_lg_w_q_range465w472w(0) <= wire_startup_cntr_w_q_range465w(0) AND wire_startup_cntr_w_lg_w_q_range458w460w(0);
+	wire_startup_cntr_w_lg_w_q_range465w475w(0) <= wire_startup_cntr_w_q_range465w(0) AND wire_startup_cntr_w_lg_w_q_range458w474w(0);
+	wire_startup_cntr_w_lg_w_q_range458w460w(0) <= NOT wire_startup_cntr_w_q_range458w(0);
+	wire_startup_cntr_w_lg_w_q_range458w474w(0) <= wire_startup_cntr_w_q_range458w(0) OR wire_startup_cntr_w_q_range462w(0);
+	wire_startup_cntr_w_lg_w_q_range458w464w(0) <= wire_startup_cntr_w_q_range458w(0) XOR wire_startup_cntr_w_q_range462w(0);
+	wire_startup_cntr_w_lg_w_q_range465w468w(0) <= wire_startup_cntr_w_q_range465w(0) XOR wire_startup_cntr_w_lg_w_q_range462w467w(0);
+	wire_startup_cntr_w_q_range458w(0) <= startup_cntr(0);
+	wire_startup_cntr_w_q_range462w(0) <= startup_cntr(1);
+	wire_startup_cntr_w_q_range465w(0) <= startup_cntr(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN state_mc_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN state_mc_reg <= ( wire_dprio_w_lg_s2_to_197w & wire_dprio_w_lg_s1_to_181w & wire_dprio_w_lg_s0_to_162w);
+		END IF;
+	END PROCESS;
+	wire_state_mc_reg_w_q_range56w(0) <= state_mc_reg(0);
+	wire_state_mc_reg_w_q_range75w(0) <= state_mc_reg(1);
+	wire_state_mc_reg_w_q_range91w(0) <= state_mc_reg(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_asdata(0);
+				ELSE wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_asdata(1);
+				ELSE wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_asdata(2);
+				ELSE wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_asdata(3);
+				ELSE wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_asdata(4);
+				ELSE wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_asdata(5);
+				ELSE wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_asdata(6);
+				ELSE wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_asdata(7);
+				ELSE wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_asdata(8);
+				ELSE wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_asdata(9);
+				ELSE wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_asdata(10);
+				ELSE wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_asdata(11);
+				ELSE wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_asdata(12);
+				ELSE wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_asdata(13);
+				ELSE wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_asdata(14);
+				ELSE wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_asdata(15);
+				ELSE wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_asdata(16);
+				ELSE wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_asdata(17);
+				ELSE wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_asdata(18);
+				ELSE wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_asdata(19);
+				ELSE wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_asdata(20);
+				ELSE wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_asdata(21);
+				ELSE wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_asdata(22);
+				ELSE wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_asdata(23);
+				ELSE wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_asdata(24);
+				ELSE wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_asdata(25);
+				ELSE wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_asdata(26);
+				ELSE wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_asdata(27);
+				ELSE wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_asdata(28);
+				ELSE wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_asdata(29);
+				ELSE wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_asdata(30);
+				ELSE wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_asdata(31);
+				ELSE wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_wr_out_data_shift_reg_asdata <= ( "00" & "01" & "0" & quad_address(8 DOWNTO 0) & "10" & datain);
+	wire_wr_out_data_shift_reg_d <= ( wr_out_data_shift_reg(30 DOWNTO 0) & "0");
+	wire_wr_out_data_shift_reg_w_q_range331w(0) <= wr_out_data_shift_reg(31);
+	wire_pre_amble_cmpr_w_lg_w_lg_agb220w397w(0) <= wire_pre_amble_cmpr_w_lg_agb220w(0) AND rd_data_output_state;
+	wire_pre_amble_cmpr_w_lg_w_lg_agb220w332w(0) <= wire_pre_amble_cmpr_w_lg_agb220w(0) AND wr_data_state;
+	wire_pre_amble_cmpr_w_lg_agb220w(0) <= NOT wire_pre_amble_cmpr_agb;
+	wire_pre_amble_cmpr_datab <= "011111";
+	pre_amble_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_pre_amble_cmpr_aeb,
+		agb => wire_pre_amble_cmpr_agb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_pre_amble_cmpr_datab
+	  );
+	wire_rd_data_output_cmpr_datab <= "110000";
+	rd_data_output_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		ageb => wire_rd_data_output_cmpr_ageb,
+		alb => wire_rd_data_output_cmpr_alb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_rd_data_output_cmpr_datab
+	  );
+	wire_state_mc_cmpr_datab <= (OTHERS => '1');
+	state_mc_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_state_mc_cmpr_aeb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_state_mc_cmpr_datab
+	  );
+	wire_state_mc_counter_cnt_en <= wire_dprio_w_lg_write_state41w(0);
+	wire_dprio_w_lg_write_state41w(0) <= write_state OR read_state;
+	state_mc_counter :  lpm_counter
+	  GENERIC MAP (
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 6
+	  )
+	  PORT MAP ( 
+		clock => dpclk,
+		cnt_en => wire_state_mc_counter_cnt_en,
+		q => wire_state_mc_counter_q,
+		sclr => reset
+	  );
+	state_mc_decode :  lpm_decode
+	  GENERIC MAP (
+		LPM_DECODES => 8,
+		LPM_WIDTH => 3
+	  )
+	  PORT MAP ( 
+		data => state_mc_reg,
+		eq => wire_state_mc_decode_eq
+	  );
+	wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state219w222w223w(0) OR (wire_pre_amble_cmpr_w_lg_agb220w(0) AND wire_dprio_w_lg_wr_addr_state219w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state333w334w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb220w332w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state398w399w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb220w397w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
+
+ END RTL; --ip_stratixiv_gx_reconfig_8_alt_dprio_2vj
+
+
+--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=2 LPM_WIDTH=1 LPM_WIDTHS=1 data result sel
+--VERSION_BEGIN 10.1 cbx_lpm_mux 2010:11:29:22:18:02:SJ cbx_mgl 2010:11:29:22:19:52:SJ  VERSION_END
+
+--synthesis_resources = lut 1 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_stratixiv_gx_reconfig_8_mux_46a IS 
+	 PORT 
+	 ( 
+		 data	:	IN  STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
+		 result	:	OUT  STD_LOGIC_VECTOR (0 DOWNTO 0);
+		 sel	:	IN  STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+ END ip_stratixiv_gx_reconfig_8_mux_46a;
+
+ ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_8_mux_46a IS
+
+	 SIGNAL	wire_l1_w0_n0_mux_dataout	:	STD_LOGIC;
+	 SIGNAL  data_wire :	STD_LOGIC_VECTOR (1 DOWNTO 0);
+	 SIGNAL  result_wire_ext :	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  sel_wire :	STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+	data_wire <= ( data);
+	result <= result_wire_ext;
+	result_wire_ext(0) <= ( wire_l1_w0_n0_mux_dataout);
+	sel_wire(0) <= ( sel(0));
+	wire_l1_w0_n0_mux_dataout <= data_wire(1) WHEN sel_wire(0) = '1'  ELSE data_wire(0);
+
+ END RTL; --ip_stratixiv_gx_reconfig_8_mux_46a
+
+ LIBRARY altera_mf;
+ USE altera_mf.all;
+
+--synthesis_resources = alt_cal 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 2 reg 114 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm IS 
+	 PORT 
+	 ( 
+		 busy	:	OUT  STD_LOGIC;
+		 reconfig_clk	:	IN  STD_LOGIC;
+		 reconfig_fromgxb	:	IN  STD_LOGIC_VECTOR (33 DOWNTO 0);
+		 reconfig_togxb	:	OUT  STD_LOGIC_VECTOR (3 DOWNTO 0)
+	 ); 
+ END ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm;
+
+ ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0";
+
+	 SIGNAL  wire_calibration_w_lg_busy12w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_w_lg_busy11w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_busy	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_addr	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_quad_addr	:	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  wire_calibration_reset	:	STD_LOGIC;
+	 SIGNAL  wire_w_lg_offset_cancellation_reset9w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_calibration_retain_addr	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_address	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_busy	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_datain	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dpriodisable	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioin	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioload	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy13w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy14w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 address_pres_reg	:	STD_LOGIC_VECTOR(11 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF address_pres_reg : SIGNAL IS "PRESERVE_REGISTER=ON";
+
+	 SIGNAL  wire_dprioout_mux_result	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  cal_busy :	STD_LOGIC;
+	 SIGNAL  cal_dprioout_wire :	STD_LOGIC_VECTOR (1 DOWNTO 0);
+	 SIGNAL  cal_testbuses :	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL  channel_address :	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL  dprio_address :	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  is_adce_all_control :	STD_LOGIC;
+	 SIGNAL  is_adce_continuous_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_one_time_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_standby_single_control :	STD_LOGIC;
+	 SIGNAL  offset_cancellation_reset	:	STD_LOGIC;
+	 SIGNAL  quad_address :	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  reconfig_reset_all :	STD_LOGIC;
+	 SIGNAL  start	:	STD_LOGIC;
+	 SIGNAL  transceiver_init	:	STD_LOGIC;
+	 COMPONENT  alt_cal
+	 GENERIC 
+	 (
+		CHANNEL_ADDRESS_WIDTH	:	NATURAL := 1;
+		NUMBER_OF_CHANNELS	:	NATURAL;
+		SIM_MODEL_MODE	:	STRING := "FALSE";
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "alt_cal"
+	 );
+	 PORT
+	 ( 
+		busy	:	OUT STD_LOGIC;
+		cal_error	:	OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
+		clock	:	IN STD_LOGIC;
+		dprio_addr	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_busy	:	IN STD_LOGIC;
+		dprio_datain	:	IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_dataout	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_rden	:	OUT STD_LOGIC;
+		dprio_wren	:	OUT STD_LOGIC;
+		quad_addr	:	OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+		remap_addr	:	IN STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
+		reset	:	IN STD_LOGIC := '0';
+		retain_addr	:	OUT STD_LOGIC;
+		start	:	IN STD_LOGIC := '0';
+		testbuses	:	IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS*4-1 DOWNTO 0) := (OTHERS => '0');
+		transceiver_init	:	IN STD_LOGIC
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  ip_stratixiv_gx_reconfig_8_alt_dprio_2vj
+	 PORT
+	 ( 
+		address	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		busy	:	OUT  STD_LOGIC;
+		datain	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
+		dataout	:	OUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dpclk	:	IN  STD_LOGIC;
+		dpriodisable	:	OUT  STD_LOGIC;
+		dprioin	:	OUT  STD_LOGIC;
+		dprioload	:	OUT  STD_LOGIC;
+		dprioout	:	IN  STD_LOGIC;
+		quad_address	:	IN  STD_LOGIC_VECTOR(8 DOWNTO 0);
+		rden	:	IN  STD_LOGIC := '0';
+		reset	:	IN  STD_LOGIC := '0';
+		wren	:	IN  STD_LOGIC := '0';
+		wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  ip_stratixiv_gx_reconfig_8_mux_46a
+	 PORT
+	 ( 
+		data	:	IN  STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
+		result	:	OUT  STD_LOGIC_VECTOR(0 DOWNTO 0);
+		sel	:	IN  STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	busy <= cal_busy;
+	cal_busy <= wire_calibration_busy;
+	cal_dprioout_wire <= ( reconfig_fromgxb(17) & reconfig_fromgxb(0));
+	cal_testbuses <= ( reconfig_fromgxb(33 DOWNTO 18) & reconfig_fromgxb(16 DOWNTO 1));
+	channel_address <= wire_calibration_dprio_addr(14 DOWNTO 12);
+	dprio_address <= ( wire_calibration_dprio_addr(15) & address_pres_reg(2 DOWNTO 0) & wire_calibration_dprio_addr(11 DOWNTO 0));
+	offset_cancellation_reset <= '0';
+	quad_address <= wire_calibration_quad_addr;
+	reconfig_reset_all <= '0';
+	reconfig_togxb <= ( wire_calibration_busy & wire_dprio_dprioload & wire_dprio_dpriodisable & wire_dprio_dprioin);
+	start <= '0';
+	transceiver_init <= '0';
+	loop1 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy12w(i) <= wire_calibration_busy AND dprio_address(i);
+	END GENERATE loop1;
+	loop2 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy11w(i) <= wire_calibration_busy AND wire_calibration_dprio_dataout(i);
+	END GENERATE loop2;
+	wire_calibration_reset <= wire_w_lg_offset_cancellation_reset9w(0);
+	wire_w_lg_offset_cancellation_reset9w(0) <= offset_cancellation_reset OR reconfig_reset_all;
+	calibration :  alt_cal
+	  GENERIC MAP (
+		CHANNEL_ADDRESS_WIDTH => 3,
+		NUMBER_OF_CHANNELS => 8,
+		SIM_MODEL_MODE => "FALSE"
+	  )
+	  PORT MAP ( 
+		busy => wire_calibration_busy,
+		clock => reconfig_clk,
+		dprio_addr => wire_calibration_dprio_addr,
+		dprio_busy => wire_dprio_busy,
+		dprio_datain => wire_dprio_dataout,
+		dprio_dataout => wire_calibration_dprio_dataout,
+		dprio_rden => wire_calibration_dprio_rden,
+		dprio_wren => wire_calibration_dprio_wren,
+		quad_addr => wire_calibration_quad_addr,
+		remap_addr => address_pres_reg,
+		reset => wire_calibration_reset,
+		retain_addr => wire_calibration_retain_addr,
+		start => start,
+		testbuses => cal_testbuses,
+		transceiver_init => transceiver_init
+	  );
+	wire_dprio_address <= wire_calibration_w_lg_busy12w;
+	wire_dprio_datain <= wire_calibration_w_lg_busy11w;
+	wire_dprio_rden <= wire_calibration_w_lg_busy13w(0);
+	wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
+	wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
+	wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
+	dprio :  ip_stratixiv_gx_reconfig_8_alt_dprio_2vj
+	  PORT MAP ( 
+		address => wire_dprio_address,
+		busy => wire_dprio_busy,
+		datain => wire_dprio_datain,
+		dataout => wire_dprio_dataout,
+		dpclk => reconfig_clk,
+		dpriodisable => wire_dprio_dpriodisable,
+		dprioin => wire_dprio_dprioin,
+		dprioload => wire_dprio_dprioload,
+		dprioout => wire_dprioout_mux_result(0),
+		quad_address => address_pres_reg(11 DOWNTO 3),
+		rden => wire_dprio_rden,
+		reset => reconfig_reset_all,
+		wren => wire_dprio_wren,
+		wren_data => wire_calibration_retain_addr
+	  );
+	PROCESS (reconfig_clk, reconfig_reset_all)
+	BEGIN
+		IF (reconfig_reset_all = '1') THEN address_pres_reg <= (OTHERS => '0');
+		ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
+		END IF;
+	END PROCESS;
+	dprioout_mux :  ip_stratixiv_gx_reconfig_8_mux_46a
+	  PORT MAP ( 
+		data => cal_dprioout_wire,
+		result => wire_dprioout_mux_result,
+		sel => quad_address(0 DOWNTO 0)
+	  );
+
+ END RTL; --ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm
+--VALID FILE
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY ip_stratixiv_gx_reconfig_8 IS
+	PORT
+	(
+		reconfig_clk		: IN STD_LOGIC ;
+		reconfig_fromgxb		: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
+		busy		: OUT STD_LOGIC ;
+		reconfig_togxb		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END ip_stratixiv_gx_reconfig_8;
+
+
+ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_8 IS
+
+	ATTRIBUTE synthesis_clearbox: natural;
+	ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
+	ATTRIBUTE clearbox_macroname: string;
+	ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt2gxb_reconfig";
+	ATTRIBUTE clearbox_defparam: string;
+	ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "cbx_blackbox_list=-lpm_mux;intended_device_family=Stratix IV;number_of_channels=8;number_of_reconfig_ports=2;enable_buf_cal=true;reconfig_fromgxb_width=34;reconfig_togxb_width=4;";
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+
+
+	COMPONENT ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm
+	PORT (
+			busy	: OUT STD_LOGIC ;
+			reconfig_clk	: IN STD_LOGIC ;
+			reconfig_fromgxb	: IN STD_LOGIC_VECTOR (33 DOWNTO 0);
+			reconfig_togxb	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	busy    <= sub_wire0;
+	reconfig_togxb    <= sub_wire1(3 DOWNTO 0);
+
+	ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm_component : ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm
+	PORT MAP (
+		reconfig_clk => reconfig_clk,
+		reconfig_fromgxb => reconfig_fromgxb,
+		busy => sub_wire0,
+		reconfig_togxb => sub_wire1
+	);
+
+
+
+END RTL;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
+-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
+-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: PMA NUMERIC "0"
+-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
+-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "2"
+-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
+-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "34"
+-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
+-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 34 0 INPUT NODEFVAL "reconfig_fromgxb[33..0]"
+-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
+-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 34 0 reconfig_fromgxb 0 0 34 0
+-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_8.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_8.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_8.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_8.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_8_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: LIB_FILE: lpm
-- 
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