diff --git a/boards/uniboard1/designs/unb1_test/hdllib.cfg b/boards/uniboard1/designs/unb1_test/hdllib.cfg
index 2db456668eb268431afea55baac3ab36f045f163..521d1d8bc2e8324cc5317f8b197eedf0d124335e 100644
--- a/boards/uniboard1/designs/unb1_test/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = unb1_test
hdl_library_clause_name = unb1_test_lib
-hdl_lib_uses = common mm i2c unb1_board epcs dp eth tr_10GbE mdio diagnostics diag
+hdl_lib_uses = common technology tech_tse mm i2c unb1_board epcs dp eth tr_10GbE mdio diagnostics diag
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..f7ae6ab7823700b1d201103fca5d594ee32b1b01
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg
@@ -0,0 +1,39 @@
+hdl_lib_name = unb1_test_lpbk
+hdl_library_clause_name = unb1_test_lpbk_lib
+hdl_lib_uses = unb1_board unb1_test
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+ unb1_test_lpbk.vhd
+
+test_bench_files =
+ tb_unb1_test_lpbk.vhd
+
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_unb1_test.qsys .
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_0.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_1.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_2.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_0.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_1.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_2.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_0.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_1.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_2.hex ../..
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+ ../../quartus/unb1_test_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/quartus/unb1_test_lpbk/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/tb_unb1_test_lpbk.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/tb_unb1_test_lpbk.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6ea5b150f4688fe73d3b341c6568656f4a078eed
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/tb_unb1_test_lpbk.vhd
@@ -0,0 +1,41 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for unb1_test_lpbk.
+-- Description: see tb_unb1_test
+
+
+LIBRARY IEEE, unb1_test_lib;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb1_test_lpbk IS
+END tb_unb1_test_lpbk;
+
+
+ARCHITECTURE tb OF tb_unb1_test_lpbk IS
+BEGIN
+ u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
+ GENERIC MAP (
+ g_design_name => "unb1_test_lpbk"
+ );
+END tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..814377e5ddfe29c778b30e413baf6a23cab1f087
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd
@@ -0,0 +1,156 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, unb1_board_lib, unb1_test_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+
+ENTITY unb1_test_lpbk IS
+ GENERIC (
+ g_design_name : STRING := "unb1_test_lpbk"; -- use revision name = entity name = design name
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ --CLK : IN STD_LOGIC; -- System Clock - not used as the SOPC generates dp_clk.
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ sens_sc : INOUT STD_LOGIC;
+ sens_sd : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_clk : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC;
+ ETH_SGOUT : OUT STD_LOGIC
+
+ -- Transceiver clocks
+ --SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+
+ -- Serial I/O
+ --SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ --SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ --SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ --SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ --SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ --SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+
+ --BN_BI_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --BN_BI_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --BN_BI_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --BN_BI_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0)
+ );
+END unb1_test_lpbk;
+
+
+ARCHITECTURE str OF unb1_test_lpbk IS
+
+BEGIN
+
+ u_revision : ENTITY unb1_test_lib.unb1_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ PORT MAP (
+ -- GENERAL
+ --CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => '0',
+
+ -- Serial I/O
+ SI_FN_0_TX => OPEN,
+ SI_FN_0_RX => (OTHERS => '0'),
+ SI_FN_1_TX => OPEN,
+ SI_FN_1_RX => (OTHERS => '0'),
+ SI_FN_2_TX => OPEN,
+ SI_FN_2_RX => (OTHERS => '0'),
+ SI_FN_3_TX => OPEN,
+ SI_FN_3_RX => (OTHERS => '0'),
+
+ SI_FN_0_CNTRL => OPEN,
+ SI_FN_1_CNTRL => OPEN,
+ SI_FN_2_CNTRL => OPEN,
+ SI_FN_3_CNTRL => OPEN,
+ SI_FN_RSTN => OPEN,
+
+ BN_BI_0_TX => OPEN,
+ BN_BI_0_RX => (OTHERS => '0'),
+ BN_BI_1_TX => OPEN,
+ BN_BI_1_RX => (OTHERS => '0'),
+ BN_BI_2_TX => OPEN,
+ BN_BI_2_RX => (OTHERS => '0'),
+ BN_BI_3_TX => OPEN,
+ BN_BI_3_RX => (OTHERS => '0')
+ );
+
+END str;
+
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 4868d87374079cf31d16b7700111ad0d1067e4bf..8f5fd8404d6f5a9e6a8c3a0092052d9b65d225f6 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -19,11 +19,12 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, remu_lib, epcs_lib, eth_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, remu_lib, epcs_lib, eth_lib, technology_lib, tech_tse_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE common_lib.common_network_total_header_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
@@ -32,6 +33,9 @@ USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+--USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE work.qsys_unb1_test_pkg.ALL;
@@ -264,6 +268,32 @@ BEGIN
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ PORT MAP(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+
+ u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ PORT MAP(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+
+ u_mm_file_reg_dp_offload_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
+ PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
+
+ u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
+ PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
+
+ u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
+ PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
+
+ u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
+ PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
+
+ u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ PORT MAP(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+
+ u_mm_file_ram_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
+ PORT MAP(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+
+ u_mm_file_reg_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
+ PORT MAP(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
@@ -272,6 +302,39 @@ BEGIN
u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE", c_mm_clk_period, FALSE, 0)
PORT MAP(mm_rst, i_mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso );
+ u_mm_file_reg_tr_xaui : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI", c_mm_clk_period, FALSE, 0)
+ PORT MAP(mm_rst, i_mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso );
+
+
+ ----------------------------------------------------------------------------
+ -- 1GbE setup sequence normally performed by unb_os@NIOS
+ ----------------------------------------------------------------------------
+ p_eth_setup : PROCESS
+ BEGIN
+ sim_eth_mm_bus_switch <= '1';
+
+ eth1g_tse_mosi.wr <= '0';
+ eth1g_tse_mosi.rd <= '0';
+ WAIT FOR 400 ns;
+ WAIT UNTIL rising_edge(i_mm_clk);
+ --proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+
+ -- Enable RX
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ sim_eth_mm_bus_switch <= '0';
+
+ WAIT;
+ END PROCESS;
+
+ p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
+ BEGIN
+ IF sim_eth_mm_bus_switch = '1' THEN
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ ELSE
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ END IF;
+ END PROCESS;
+
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index fcb53b1f5e822520584a7ce4e3fb1fbe23883592..b714809f23737c129c4c0117b568806e12ab3ab3 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -117,9 +117,9 @@ ARCHITECTURE str OF unb1_test IS
CONSTANT c_lpbk_data_w : NATURAL := 32; -- 128 c_eth_data_w, c_xgmii_data_w
-- Revision controlled constants
- CONSTANT c_use_lpbk : BOOLEAN := FALSE; --g_design_name = "unb_dp_offload";
- CONSTANT c_use_1GbE : BOOLEAN := FALSE; --g_design_name = "unb_dp_offload_1GbE";
- CONSTANT c_use_10GbE : BOOLEAN := TRUE; --g_design_name = "fn_dp_offload_10GbE";
+ CONSTANT c_use_lpbk : BOOLEAN := g_design_name = "unb1_test_lpbk";
+ CONSTANT c_use_1GbE : BOOLEAN := g_design_name = "unb1_test_1GbE";
+ CONSTANT c_use_10GbE : BOOLEAN := g_design_name = "unb1_test_10GbE";
CONSTANT c_nof_streams : NATURAL := 3;
CONSTANT c_data_w : NATURAL := sel_a_b(c_use_lpbk, c_lpbk_data_w, -- Select correct c_data_w when one interface is used
sel_a_b(c_use_1GbE, c_eth_data_w,
@@ -580,7 +580,7 @@ BEGIN
g_nof_output_streams => c_nof_streams,
g_buf_dat_w => c_data_w,
g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => sel_a_b(g_sim, "../", "") & "counter_data_" & NATURAL'IMAGE(c_data_w),
+ g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(c_data_w),
g_diag_block_gen_rst => c_bg_ctrl
)
PORT MAP (
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index fd3a9bcf4756f1fd6f5e240575dded80fec13aa5..428e4e98c9934debf26d6a891cfa2d0090dbaca9 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -50,6 +50,9 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
ENTITY tb_unb1_test IS
+ GENERIC (
+ g_design_name : STRING := "unb1_test"
+ );
END tb_unb1_test;
ARCHITECTURE tb OF tb_unb1_test IS
@@ -144,7 +147,8 @@ BEGIN
GENERIC MAP (
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
+ g_sim_node_nr => c_node_nr,
+ g_design_name => g_design_name
)
PORT MAP (
-- GENERAL