From 84e3253cf8ed00973a61f72cd6b7aa5c0e7ef445 Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@jive.eu>
Date: Fri, 7 Feb 2020 14:45:22 +0100
Subject: [PATCH] Wrappers for the one_node and full revisions of the
lofar2_unb2b_adc design
---
.../lofar2_unb2b_adc_full/hdllib.cfg | 68 +++
.../lofar2_unb2b_adc_full.vhd | 136 ++++++
.../quartus/lofar2_unb2b_adc_full.sdc | 1 +
.../quartus/lofar2_unb2b_adc_full_pins.tcl | 23 +
.../lofar2_unb2b_adc_one_node.vhd | 133 +-----
.../lofar2_unb2b_adc_one_node_pins.tcl | 5 +-
.../src/vhdl/lofar2_unb2b_adc.vhd | 439 +++++++++++++++---
7 files changed, 627 insertions(+), 178 deletions(-)
create mode 100644 applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
create mode 100644 applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
create mode 100644 applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/quartus/lofar2_unb2b_adc_full.sdc
create mode 100644 applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/quartus/lofar2_unb2b_adc_full_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
new file mode 100644
index 0000000000..1cbac2db80
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
@@ -0,0 +1,68 @@
+hdl_lib_name = lofar2_unb2b_adc_full
+hdl_library_clause_name = lofar2_unb2b_adc_full_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_adc
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+ synth_files =
+ lofar2_unb2b_adc_full.vhd
+
+test_bench_files =
+
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+# Pinning design only intended for synthesis
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus .
+ ../../src/hex hex
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+quartus_sdc_pre_files =
+ quartus/lofar_unb2b_adc_full.sdc
+
+quartus_sdc_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ quartus/lofar_unb2b_adc_full_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar_unb2b_adc_full/qsys_lofar_unb2b_adc/qsys_lofar_unb2b_adc.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
new file mode 100644
index 0000000000..77466af45d
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -0,0 +1,136 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2b_adc_full IS
+ GENERIC (
+ g_design_name : STRING := "lofar2_unb2b_adc_full";
+ g_design_note : STRING := "Lofar2 adc with one node";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- back transceivers
+ BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0)
+ );
+END lofar2_unb2b_adc_full;
+
+
+ARCHITECTURE str OF lofar2_unb2b_adc_full IS
+
+BEGIN
+
+ u_revision : ENTITY unb2b_test_lib.unb2b_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+
+ -- back transceivers
+ BCK_RX => BCK_RX_INTERNAL,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC => JESD204B_SYNC
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/quartus/lofar2_unb2b_adc_full.sdc b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/quartus/lofar2_unb2b_adc_full.sdc
new file mode 100644
index 0000000000..e0a8d1b581
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/quartus/lofar2_unb2b_adc_full.sdc
@@ -0,0 +1 @@
+#Placeholder
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/quartus/lofar2_unb2b_adc_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/quartus/lofar2_unb2b_adc_full_pins.tcl
new file mode 100644
index 0000000000..da85c19f65
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/quartus/lofar2_unb2b_adc_full_pins.tcl
@@ -0,0 +1,23 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index 9cc06592a2..f7211d878f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -20,14 +20,15 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_test_lib, technology_lib, tech_ddr_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
-USE unb2b_board_lib.unb2b_board_pkg.ALL; -- use the original package
+USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-USE tech_ddr_lib.tech_ddr_pkg.ALL;
-
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
ENTITY lofar2_unb2b_adc_one_node IS
GENERIC (
@@ -57,79 +58,33 @@ ENTITY lofar2_unb2b_adc_one_node IS
SENS_SC : INOUT STD_LOGIC;
SENS_SD : INOUT STD_LOGIC;
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
- -- Transceiver clocks
- SA_CLK : IN STD_LOGIC; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : IN STD_LOGIC; -- Clock 10GbE back. From on-board XTAL
- BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- -- DDR reference clocks
- MB_I_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_I
- MB_II_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_II
-
- -- back transceivers
+ -- back transceivers
BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
- --BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
-- jesd204b syncronization signals
JESD204B_SYSREF : IN STD_LOGIC;
- JESD204B_SYNC : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
-
- -- ring transceivers
- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- -- pmbus
- PMBUS_SC : INOUT STD_LOGIC;
- PMBUS_SD : INOUT STD_LOGIC;
- PMBUS_ALERT : IN STD_LOGIC;
- -- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
-
- QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.i2c_w-1 downto 0);
- QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.i2c_w-1 downto 0);
-
- -- SO-DIMM Memory Bank I
- MB_I_IN : IN t_tech_ddr4_phy_in;
- MB_I_IO : INOUT t_tech_ddr4_phy_io;
- MB_I_OU : OUT t_tech_ddr4_phy_ou;
-
- -- SO-DIMM Memory Bank II
- MB_II_IN : IN t_tech_ddr4_phy_in;
- MB_II_IO : INOUT t_tech_ddr4_phy_io;
- MB_II_OU : OUT t_tech_ddr4_phy_ou;
-
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ JESD204B_SYNC : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0)
);
END lofar2_unb2b_adc_one_node;
ARCHITECTURE str OF lofar2_unb2b_adc_one_node IS
- SIGNAL BCK_RX_INTERNAL : STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0) := (others => '0');
-
BEGIN
- gen_bck_to_jesd204b : FOR i IN 0 TO (c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 GENERATE
- BCK_RX_INTERNAL(i) <= BCK_RX(0);
- END GENERATE;
-
u_revision : ENTITY unb2b_test_lib.unb2b_test
GENERIC MAP (
g_design_name => g_design_name,
@@ -158,66 +113,24 @@ BEGIN
SENS_SC => SENS_SC,
SENS_SD => SENS_SD,
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
+ -- LEDs
+ QSFP_LED => QSFP_LED
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
-- back transceivers
BCK_RX => BCK_RX_INTERNAL,
- BCK_TX => open,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
+ BCK_REF_CLK => BCK_REF_CLK,
+
-- jesd204b syncronization signals
JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC => JESD204B_SYNC,
-
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
+ JESD204B_SYNC => JESD204B_SYNC
);
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/quartus/lofar2_unb2b_adc_one_node_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/quartus/lofar2_unb2b_adc_one_node_pins.tcl
index 18a4560ef5..da85c19f65 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/quartus/lofar2_unb2b_adc_one_node_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/quartus/lofar2_unb2b_adc_one_node_pins.tcl
@@ -19,6 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index 57bfac6eca..48e1837197 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -20,21 +20,15 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE common_lib.common_interface_layers_pkg.ALL;
-USE common_lib.common_network_layers_pkg.ALL;
-USE common_lib.common_field_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
-USE eth_lib.eth_pkg.ALL;
-USE tech_ddr_lib.tech_ddr_pkg.ALL;
-USE work.unb2b_test_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
ENTITY lofar2_unb2b_adc IS
GENERIC (
@@ -49,6 +43,7 @@ ENTITY lofar2_unb2b_adc IS
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_revision_id : STRING := "" -- revision ID -- set by QSF
g_factory_image : BOOLEAN := FALSE
+ g_protect_addr_range: BOOLEAN := FALSE
);
PORT (
-- GENERAL
@@ -67,80 +62,394 @@ ENTITY lofar2_unb2b_adc IS
SENS_SC : INOUT STD_LOGIC;
SENS_SD : INOUT STD_LOGIC;
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
- -- Transceiver clocks
- SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE back upper 24 lines
- BCK_REF_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE back lower 24 lines
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- back transceivers
+ BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0)
+ );
+END lofar2_unb2b_adc;
- -- DDR reference clocks
- MB_I_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_I
- MB_II_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_II
- -- back transceivers
- --BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
- --BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
- --BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
- --BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
+ARCHITECTURE str OF lofar2_unb2b_adc IS
- BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 downto 0);
- BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 downto 0);
- BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_back.i2c_w-1 downto 0);
+ -- Firmware version x.y
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
+ CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
+ CONSTANT c_nof_streams_jesd204b : NATURAL := 12;
+ CONSTANT c_nof_streams_db : NATURAL := 2;
- -- ring transceivers
- --RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
- --RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- --RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
- --RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- System
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_ethclk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL st_rst : STD_LOGIC;
+ SIGNAL st_clk : STD_LOGIC;
+ SIGNAL st_pps : STD_LOGIC;
- -- pmbus
- PMBUS_SC : INOUT STD_LOGIC;
- PMBUS_SD : INOUT STD_LOGIC;
- PMBUS_ALERT : IN STD_LOGIC := '0';
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
- -- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
-
- QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.i2c_w-1 downto 0);
- QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.i2c_w-1 downto 0);
- QSFP_RST : INOUT STD_LOGIC;
-
- -- SO-DIMM Memory Bank I
- MB_I_IN : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
- MB_I_IO : INOUT t_tech_ddr4_phy_io;
- MB_I_OU : OUT t_tech_ddr4_phy_ou;
-
- -- SO-DIMM Memory Bank II
- MB_II_IN : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
- MB_II_IO : INOUT t_tech_ddr4_phy_io;
- MB_II_OU : OUT t_tech_ddr4_phy_ou;
-
- -- Leds
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
- );
-END lofar2_unb2b_adc;
+ -- WDI override
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+ -- PPSH
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ -- UniBoard system info
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
-ARCHITECTURE str OF lofar2_unb2b_adc IS
+ -- UniBoard I2C sens
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+ -- pm bus
+ SIGNAL reg_unb_pmbus_mosi : t_mem_mosi;
+ SIGNAL reg_unb_pmbus_miso : t_mem_miso;
+
+ -- FPGA sensors
+ SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi;
+ SIGNAL reg_fpga_temp_sens_miso : t_mem_miso;
+ SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi;
+ SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
+
+ -- eth1g
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+
+ -- EPCS read
+ SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_data_miso : t_mem_miso;
+ SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
+
+ -- EPCS write
+ SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_data_miso : t_mem_miso;
+ SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
+
+ -- EPCS status/control
+ SIGNAL reg_epcs_mosi : t_mem_mosi;
+ SIGNAL reg_epcs_miso : t_mem_miso;
+
+ -- Remote Update
+ SIGNAL reg_remu_mosi : t_mem_mosi;
+ SIGNAL reg_remu_miso : t_mem_miso;
+
+ -- JESD
+ SIGNAL jesd204b_mosi : t_mem_mosi;
+ SIGNAL jesd204b_miso : t_mem_miso;
+
+ -- QSFP leds
+ SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+
+ -- JESD signals
+ SIGNAL ram_diag_data_buf_jesd_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_jesd_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_jesd_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_jesd_miso : t_mem_miso;
+ SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_streams_db-1 DOWNTO 0);
+ SIGNAL jesd204b_rx_src_out_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL jesd204b_frame_clk : STD_LOGIC;
BEGIN
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_use_pll => FALSE
+ )
+ PORT MAP (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => jesd204b_frame_clk,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+ -----------------------------------------------------------------------------
+ -- MM master
+ -----------------------------------------------------------------------------
+ u_mmm : ENTITY work.mmm_unb2b_jesd_simple
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ --
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso
+ );
+
+ u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_channels => c_nof_streams_jesd204b
+ )
+ PORT MAP(
+ jesd204b_refclk => BCK_REF_CLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => JESD204B_SYNC,
+
+ rx_src_out_arr => jesd204b_rx_src_out_arr,
+ jesd204b_frame_clk => jesd204b_frame_clk,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => BCK_RX(c_nof_streams_jesd204b-1 downto 0)
+ );
+
+
+ gen_jesd_mon_in : FOR i IN 0 TO c_nof_streams_db-1 GENERATE
+ diag_data_buf_snk_in_arr(i).data(15 downto 0) <= jesd204b_rx_src_out_arr(i).data(15 downto 0);
+ diag_data_buf_snk_in_arr(i).valid <= jesd204b_rx_src_out_arr(i).valid;
+ diag_data_buf_snk_in_arr(i).sop <= '0';
+ diag_data_buf_snk_in_arr(i).eop <= '0';
+ diag_data_buf_snk_in_arr(i).err <= (OTHERS=>'0');
+ END GENERATE;
+
+
+ u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_db,
+ g_data_w => 16,
+ g_buf_nof_data => 8192, --8192,
+ g_buf_use_sync => TRUE, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_use_rx_seq => FALSE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => st_rst,
+ dp_clk => jesd204b_frame_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
+
+ in_sosi_arr => diag_data_buf_snk_in_arr,
+ in_sync => st_pps
+ );
END str;
--
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