From 84b725744b0a3cdad84cff6817abc3095863d13b Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 8 Feb 2024 07:22:24 +0100
Subject: [PATCH] tb_tech_jesd204_v2.vhd was used.
---
.../jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd | 12 ++++++------
.../jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd | 12 ++++++------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
index 996baefa17..fdfbf65178 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
@@ -519,12 +519,12 @@ begin
-- there can occur once a one dp_clk cycle disturbance in the toggling, in case
-- rxlink_clk and dp_clk almost coincide.
--
- -- Simulation with tb_tech_jesd204b.vhd reveals that the double data word is always
- -- read high part first and low part next, independent of the phase of dp_index.
- -- This is because reading ab, cd, ef, ... is equivalent to reading bc, de, fg, ...
- -- However the phase of dp_ready with respect to dp_index is important for reading
- -- the sync, because if dp_ready has the wrong phase, then the sync is missed at
- -- the FIFO output.
+ -- Simulation with tb_tech_jesd204b_v2.vhd reveals that the double data word is
+ -- always read high part first and low part next, independent of the phase of
+ -- dp_index. This is because reading ab, cd, ef, ... is equivalent to reading
+ -- bc, de, fg, ... However the phase of dp_ready with respect to dp_index is
+ -- important for reading the sync, because if dp_ready has the wrong phase,
+ -- then the sync is missed at the FIFO output.
-- . If dp_index = '0' or '1' initialy, then in both cases use dp_ready <= not
-- dp_index, and then in both cases the latency dp_sosi.sync and data = 1000 is
-- then 340 ns
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
index 36ec9f44c6..fcc8ee1a65 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
@@ -519,12 +519,12 @@ begin
-- there can occur once a one dp_clk cycle disturbance in the toggling, in case
-- rxlink_clk and dp_clk almost coincide.
--
- -- Simulation with tb_tech_jesd204b.vhd reveals that the double data word is always
- -- read high part first and low part next, independent of the phase of dp_index.
- -- This is because reading ab, cd, ef, ... is equivalent to reading bc, de, fg, ...
- -- However the phase of dp_ready with respect to dp_index is important for reading
- -- the sync, because if dp_ready has the wrong phase, then the sync is missed at
- -- the FIFO output.
+ -- Simulation with tb_tech_jesd204b_v2.vhd reveals that the double data word is
+ -- always read high part first and low part next, independent of the phase of
+ -- dp_index. This is because reading ab, cd, ef, ... is equivalent to reading
+ -- bc, de, fg, ... However the phase of dp_ready with respect to dp_index is
+ -- important for reading the sync, because if dp_ready has the wrong phase,
+ -- then the sync is missed at the FIFO output.
-- . If dp_index = '0' or '1' initialy, then in both cases use dp_ready <= not
-- dp_index, and then in both cases the latency dp_sosi.sync and data = 1000 is
-- then 340 ns
--
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