diff --git a/libraries/io/node_unb_tr_10GbE/src/vhdl/node_unb_tr_10GbE.vhd b/libraries/io/node_unb_tr_10GbE/src/vhdl/node_unb_tr_10GbE.vhd deleted file mode 100644 index f6afa0fccc73c72d6f530968562dea2e75d5a314..0000000000000000000000000000000000000000 --- a/libraries/io/node_unb_tr_10GbE/src/vhdl/node_unb_tr_10GbE.vhd +++ /dev/null @@ -1,192 +0,0 @@ -------------------------------------------------------------------------------- --- --- Copyright (C) 2013 --- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> --- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see <http://www.gnu.org/licenses/>. --- -------------------------------------------------------------------------------- - -LIBRARY IEEE, common_lib, unb_common_lib, dp_lib, tr_nonbonded_lib, tr_xaui_lib, diagnostics_lib, tr_10GbE_lib, technology_lib, tech_memory_lib; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE common_lib.common_pkg.ALL; -USE common_lib.common_mem_pkg.ALL; -USE unb_common_lib.unb_common_pkg.ALL; -USE dp_lib.dp_stream_pkg.ALL; -USE tr_xaui_lib.tr_xaui_pkg.ALL; -USE technology_lib.technology_select_pkg.ALL; - -ENTITY node_unb_tr_10GbE IS - GENERIC ( - g_technology : NATURAL := c_tech_select_default; - g_sim : BOOLEAN; - g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model - g_nof_macs : NATURAL; - g_use_mdio : BOOLEAN; - g_mdio_epcs_dis : BOOLEAN := FALSE; -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it - g_lpbk_sosi : BOOLEAN := FALSE; -- i/o pins <-> )( <-> tr_xaui <-> )( <-> tr_10GbE <-> )( <-> user - g_lpbk_xgmii : BOOLEAN := FALSE; -- ^^ ^^ ^^ - g_lpbk_xaui : BOOLEAN := FALSE -- g_lpbk_xaui| g_lpbk_xgmii| g_lpbk_sosi| - ); - PORT ( - -- System - mm_rst : IN STD_LOGIC; - mm_clk : IN STD_LOGIC; - - dp_rst : IN STD_LOGIC; - dp_clk : IN STD_LOGIC; - - tr_clk : IN STD_LOGIC; - cal_rec_clk : IN STD_LOGIC; - - -- MM registers - reg_diagnostics_mosi : IN t_mem_mosi; - reg_diagnostics_miso : OUT t_mem_miso; - - reg_hdr_insert_mosi : IN t_mem_mosi; - ram_hdr_insert_mosi : IN t_mem_mosi; - - ram_hdr_remove_mosi : IN t_mem_mosi; - ram_hdr_remove_miso : OUT t_mem_miso; - - reg_mac_mosi : IN t_mem_mosi; - reg_mac_miso : OUT t_mem_miso; - - -- Serial I/O - xaui_tx_arr : OUT t_unb_xaui_sl_2arr(g_nof_macs-1 DOWNTO 0); - xaui_rx_arr : IN t_unb_xaui_sl_2arr(g_nof_macs-1 DOWNTO 0); - - -- Serial IO for Arria - tx_serial_data : out std_logic_vector(g_nof_macs-1 downto 0); - rx_serial_data : in std_logic_vector(g_nof_macs-1 downto 0); - - mdio_mdc_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0); - mdio_mdat_in_arr : IN STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0) := (OTHERS=>'0'); - mdio_mdat_oen_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0) - ); -END node_unb_tr_10GbE; - - -ARCHITECTURE str OF node_unb_tr_10GbE IS - ---CONSTANT c_block_len : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes. - CONSTANT c_block_len : NATURAL := 1118;-- = 8944 user bytes. Including packetizing: 9012 bytes. - - SIGNAL tr_rst : STD_LOGIC; - - SIGNAL i_xaui_tx_arr : t_xaui_arr(g_nof_macs-1 DOWNTO 0); - SIGNAL i_xaui_rx_arr : t_xaui_arr(g_nof_macs-1 DOWNTO 0); - - SIGNAL diagnostics_snk_in_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0); - SIGNAL diagnostics_snk_out_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0); - - SIGNAL diagnostics_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0); - SIGNAL diagnostics_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0); - -BEGIN - - -- Wire together different types - gen_wires: FOR i IN 0 TO g_nof_macs-1 GENERATE - xaui_tx_arr(i) <= i_xaui_tx_arr(i); - i_xaui_rx_arr(i) <= xaui_rx_arr(i); - END GENERATE; - - u_async : ENTITY common_lib.common_async - GENERIC MAP ( - g_rst_level => '1' - ) - PORT MAP ( - rst => dp_rst, - clk => dp_clk, - din => dp_rst, - dout => tr_rst - ); - - u_mms_diagnostics: ENTITY diagnostics_lib.mms_diagnostics - GENERIC MAP( - g_data_w => c_xgmii_data_w, - g_block_len => c_block_len, - g_nof_streams => g_nof_macs, - g_separate_clk => FALSE - ) - PORT MAP ( - mm_rst => mm_rst, - mm_clk => mm_clk, - - st_rst => dp_rst, - st_clk => dp_clk, - - mm_mosi => reg_diagnostics_mosi, - mm_miso => reg_diagnostics_miso, - - src_out_arr => diagnostics_src_out_arr, - src_in_arr => diagnostics_src_in_arr, - - snk_out_arr => diagnostics_snk_out_arr, - snk_in_arr => diagnostics_snk_in_arr - ); - - u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE - GENERIC MAP( - g_technology => g_technology, - g_sim => g_sim, - g_sim_level => g_sim_level, - g_nof_macs => g_nof_macs, - g_use_mdio => g_use_mdio, - g_mdio_epcs_dis => g_mdio_epcs_dis, - g_lpbk_sosi => g_lpbk_sosi, - g_lpbk_xgmii => g_lpbk_xgmii, - g_lpbk_xaui => g_lpbk_xaui, - g_use_hdr_ram => TRUE - ) - PORT MAP ( - mm_rst => mm_rst, - mm_clk => mm_clk, - - tr_clk => tr_clk, - - cal_rec_clk => cal_rec_clk, - - dp_rst => dp_rst, - dp_clk => dp_clk, - - reg_mac_mosi => reg_mac_mosi, - reg_mac_miso => reg_mac_miso, - - reg_hdr_insert_mosi => reg_hdr_insert_mosi, - ram_hdr_insert_mosi => ram_hdr_insert_mosi, - - ram_hdr_remove_mosi => ram_hdr_remove_mosi, - ram_hdr_remove_miso => ram_hdr_remove_miso, - - src_out_arr => diagnostics_snk_in_arr, - src_in_arr => diagnostics_snk_out_arr, - - snk_out_arr => diagnostics_src_in_arr, - snk_in_arr => diagnostics_src_out_arr, - - xaui_tx_out_arr => i_xaui_tx_arr, - xaui_rx_in_arr => i_xaui_rx_arr, - - tx_serial_data => tx_serial_data, - rx_serial_data => rx_serial_data, - - mdio_mdc_arr => mdio_mdc_arr, - mdio_mdat_in_arr => mdio_mdat_in_arr, - mdio_mdat_oen_arr => mdio_mdat_oen_arr - ); - -END str; diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd index 6f054543f295675eed63ae0127bdcde10205d0c1..872b092ef14999888ef878137805abc343dc43e3 100644 --- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd +++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd @@ -202,6 +202,67 @@ ARCHITECTURE str OF tr_10GbE IS SIGNAL tx_data_valid : std_logic_vector(g_nof_macs-1 DOWNTO 0); SIGNAL rx_data_valid : std_logic_vector(g_nof_macs-1 DOWNTO 0); + + --------------------------------------------------------------------------------------- + -- Component declarations to prevent synthesis of unused technologies + --------------------------------------------------------------------------------------- + + component tech_transceiver_arria10_48 is + generic ( + g_nof_channels : natural := 48 + ); + port ( + clk : in std_logic; + reset_p : in std_logic; + refclk : in std_logic; + tx_serial_data : out std_logic_vector(g_nof_macs-1 downto 0); + rx_serial_data : in std_logic_vector(g_nof_macs-1 downto 0); + tx_parallel_data : in std_logic_vector(64*g_nof_macs-1 downto 0); + rx_parallel_data : out std_logic_vector(64*g_nof_macs-1 downto 0); + tx_control : in std_logic_vector(8*g_nof_macs-1 downto 0); + rx_control : out std_logic_vector(8*g_nof_macs-1 downto 0) + ); + end component; + + component tr_xaui is + generic ( + g_technology : NATURAL := c_tech_select_default; + g_sim : BOOLEAN := FALSE; + g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model + g_use_xgmii : BOOLEAN := FALSE; -- Don't use streaming I/O but XGMII (e.g. conenct to 10GbE MAC) + g_nof_xaui : NATURAL := 1; -- Up to 3 (hard XAUI only) supported + g_mdio : BOOLEAN := FALSE; + g_mdio_epcs_dis : BOOLEAN := FALSE -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it + ); + port ( + tr_clk : IN STD_LOGIC; + cal_rec_clk : IN STD_LOGIC; + mm_clk : IN STD_LOGIC := '0'; + mm_rst : IN STD_LOGIC := '0'; + rx_clk : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0); + rx_rst : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0); + rx_sosi_arr : OUT t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0); + rx_siso_arr : IN t_dp_siso_arr(g_nof_macs-1 DOWNTO 0); + tx_clk : IN STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0); + tx_rst : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0); + tx_sosi_arr : IN t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0); + tx_siso_arr : OUT t_dp_siso_arr(g_nof_macs-1 DOWNTO 0); + xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0); + xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0); + xaui_rx : IN t_xaui_arr(g_nof_macs-1 DOWNTO 0); + xaui_tx : OUT t_xaui_arr(g_nof_macs-1 DOWNTO 0); + xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst; + xaui_miso : OUT t_mem_miso; + mdio_mosi_arr : IN t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0); + mdio_miso_arr : OUT t_mem_miso_arr(g_nof_macs-1 DOWNTO 0); + mdio_rst : OUT STD_LOGIC; + mdio_mdc : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0); + mdio_mdat_in : IN STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0); + mdio_mdat_oen : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0) + ); + end component; + + BEGIN --------------------------------------------------------------------------------------- @@ -558,7 +619,7 @@ BEGIN end generate; - u_transceiver: entity tech_transceiver_lib.tech_transceiver_arria10_48 + u_transceiver: tech_transceiver_arria10_48 generic map ( g_nof_channels => g_nof_macs )