From 839ea367efcce64533be7cfd75ac1594129ef859 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 13 Dec 2021 16:45:42 +0100
Subject: [PATCH] processed review comments
---
.../ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd | 5 +++--
.../ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 97648debd2..a887efbab7 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -116,7 +116,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL rxframe_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL f2_div1_cnt_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL core_pll_locked : STD_LOGIC;
- SIGNAL mm_core_pll_locked_reg : STD_LOGIC;
+ SIGNAL mm_core_pll_locked_reg : STD_LOGIC;
SIGNAL jesd204b_sysref_1 : STD_LOGIC;
SIGNAL jesd204b_sysref_2 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;
@@ -330,12 +330,13 @@ BEGIN
reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
reset5_dsrt_qual => mm_rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst,
+ -- reset_out* signals are in mm_clk domain
reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
reset_out2 => open,
reset_out3 => open,
reset_out4 => open,
- reset_out5 => rx_avs_rst_arr(i), -- in mm_clk domain
+ reset_out5 => rx_avs_rst_arr(i),
reset_out6 => rxlink_rst_async_arr(i),
reset_out7 => rxframe_rst_async_arr(i)
);
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index bce5d67e64..71124917e5 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -116,7 +116,7 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
SIGNAL rxframe_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL f2_div1_cnt_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL core_pll_locked : STD_LOGIC;
- SIGNAL mm_core_pll_locked_reg : STD_LOGIC;
+ SIGNAL mm_core_pll_locked_reg : STD_LOGIC;
SIGNAL jesd204b_sysref_1 : STD_LOGIC;
SIGNAL jesd204b_sysref_2 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;
@@ -330,12 +330,13 @@ BEGIN
reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
reset5_dsrt_qual => mm_rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst,
+ -- reset_out* signals are in mm_clk domain
reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
reset_out2 => open,
reset_out3 => open,
reset_out4 => open,
- reset_out5 => rx_avs_rst_arr(i), -- in mm_clk domain
+ reset_out5 => rx_avs_rst_arr(i),
reset_out6 => rxlink_rst_async_arr(i),
reset_out7 => rxframe_rst_async_arr(i)
);
--
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