diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys
index 2978d28bdc56496f5d45c83afb98260eb57d5f9a..fef79242898ecf145b7b6af8543ec4736bfb309e 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys
@@ -217,7 +217,7 @@
type = "String";
}
}
- element ram_bg_data
+ element ram_diag_bg_ring
{
datum _sortIndex
{
@@ -225,7 +225,7 @@
type = "int";
}
}
- element ram_bg_data.mem
+ element ram_diag_bg_ring.mem
{
datum baseAddress
{
@@ -249,7 +249,7 @@
type = "String";
}
}
- element reg_bg_ctrl
+ element reg_diag_bg_ring
{
datum _sortIndex
{
@@ -257,7 +257,7 @@
type = "int";
}
}
- element reg_bg_ctrl.mem
+ element reg_diag_bg_ring.mem
{
datum baseAddress
{
@@ -799,38 +799,38 @@
type="conduit"
dir="end" />
<interface
- name="ram_bg_data_address"
- internal="ram_bg_data.address"
+ name="ram_diag_bg_ring_address"
+ internal="ram_diag_bg_ring.address"
type="conduit"
dir="end" />
<interface
- name="ram_bg_data_clk"
- internal="ram_bg_data.clk"
+ name="ram_diag_bg_ring_clk"
+ internal="ram_diag_bg_ring.clk"
type="conduit"
dir="end" />
<interface
- name="ram_bg_data_read"
- internal="ram_bg_data.read"
+ name="ram_diag_bg_ring_read"
+ internal="ram_diag_bg_ring.read"
type="conduit"
dir="end" />
<interface
- name="ram_bg_data_readdata"
- internal="ram_bg_data.readdata"
+ name="ram_diag_bg_ring_readdata"
+ internal="ram_diag_bg_ring.readdata"
type="conduit"
dir="end" />
<interface
- name="ram_bg_data_reset"
- internal="ram_bg_data.reset"
+ name="ram_diag_bg_ring_reset"
+ internal="ram_diag_bg_ring.reset"
type="conduit"
dir="end" />
<interface
- name="ram_bg_data_write"
- internal="ram_bg_data.write"
+ name="ram_diag_bg_ring_write"
+ internal="ram_diag_bg_ring.write"
type="conduit"
dir="end" />
<interface
- name="ram_bg_data_writedata"
- internal="ram_bg_data.writedata"
+ name="ram_diag_bg_ring_writedata"
+ internal="ram_diag_bg_ring.writedata"
type="conduit"
dir="end" />
<interface
@@ -869,38 +869,38 @@
type="conduit"
dir="end" />
<interface
- name="reg_bg_ctrl_address"
- internal="reg_bg_ctrl.address"
+ name="reg_diag_bg_ring_address"
+ internal="reg_diag_bg_ring.address"
type="conduit"
dir="end" />
<interface
- name="reg_bg_ctrl_clk"
- internal="reg_bg_ctrl.clk"
+ name="reg_diag_bg_ring_clk"
+ internal="reg_diag_bg_ring.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bg_ctrl_read"
- internal="reg_bg_ctrl.read"
+ name="reg_diag_bg_ring_read"
+ internal="reg_diag_bg_ring.read"
type="conduit"
dir="end" />
<interface
- name="reg_bg_ctrl_readdata"
- internal="reg_bg_ctrl.readdata"
+ name="reg_diag_bg_ring_readdata"
+ internal="reg_diag_bg_ring.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bg_ctrl_reset"
- internal="reg_bg_ctrl.reset"
+ name="reg_diag_bg_ring_reset"
+ internal="reg_diag_bg_ring.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bg_ctrl_write"
- internal="reg_bg_ctrl.write"
+ name="reg_diag_bg_ring_write"
+ internal="reg_diag_bg_ring.write"
type="conduit"
dir="end" />
<interface
- name="reg_bg_ctrl_writedata"
- internal="reg_bg_ctrl.writedata"
+ name="reg_diag_bg_ring_writedata"
+ internal="reg_diag_bg_ring.writedata"
type="conduit"
dir="end" />
<interface
@@ -5899,7 +5899,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_bg_data.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_bg_ctrl.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='timer_0.s1' start='0x3040' end='0x3060' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /><slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x30C0' end='0x30C8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x30C8' end='0x30D0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x30D0' end='0x30D8' datawidth='32' /><slave name='pio_pps.mem' start='0x30D8' end='0x30E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x30E0' end='0x30E8' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg_ring.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_diag_bg_ring.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='timer_0.s1' start='0x3040' end='0x3060' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /><slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x30C0' end='0x30C8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x30C8' end='0x30D0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x30D0' end='0x30D8' datawidth='32' /><slave name='pio_pps.mem' start='0x30D8' end='0x30E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x30E0' end='0x30E8' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -15823,7 +15823,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_bg_data"
+ name="ram_diag_bg_ring"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16521,21 +16521,17 @@
</ports>
<assignments>
<assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -16575,7 +16571,6 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
- <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -16934,30 +16929,30 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_ram_bg_data</hdlLibraryName>
+ <hdlLibraryName>board_ram_diag_bg_ring</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_ram_bg_data</fileSetName>
- <fileSetFixedName>board_ram_bg_data</fileSetFixedName>
+ <fileSetName>board_ram_diag_bg_ring</fileSetName>
+ <fileSetFixedName>board_ram_diag_bg_ring</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_ram_bg_data</fileSetName>
- <fileSetFixedName>board_ram_bg_data</fileSetFixedName>
+ <fileSetName>board_ram_diag_bg_ring</fileSetName>
+ <fileSetFixedName>board_ram_diag_bg_ring</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_ram_bg_data</fileSetName>
- <fileSetFixedName>board_ram_bg_data</fileSetFixedName>
+ <fileSetName>board_ram_diag_bg_ring</fileSetName>
+ <fileSetFixedName>board_ram_diag_bg_ring</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_ram_bg_data.ip</parameter>
+ <parameter name="logicalView">ip/board/board_ram_diag_bg_ring.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -18105,7 +18100,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bg_ctrl"
+ name="reg_diag_bg_ring"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19216,30 +19211,30 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_bg_ctrl</hdlLibraryName>
+ <hdlLibraryName>board_reg_diag_bg_ring</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_bg_ctrl</fileSetName>
- <fileSetFixedName>board_reg_bg_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_diag_bg_ring</fileSetName>
+ <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_bg_ctrl</fileSetName>
- <fileSetFixedName>board_reg_bg_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_diag_bg_ring</fileSetName>
+ <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_bg_ctrl</fileSetName>
- <fileSetFixedName>board_reg_bg_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_diag_bg_ring</fileSetName>
+ <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_bg_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_diag_bg_ring.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -35846,7 +35841,7 @@
kind="avalon"
version="19.2"
start="cpu_0.data_master"
- end="reg_bg_ctrl.mem">
+ end="reg_diag_bg_ring.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3020" />
<parameter name="defaultConnection" value="false" />
@@ -35866,7 +35861,7 @@
kind="avalon"
version="19.2"
start="cpu_0.data_master"
- end="ram_bg_data.mem">
+ end="ram_diag_bg_ring.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0200" />
<parameter name="defaultConnection" value="false" />
@@ -36150,12 +36145,12 @@
kind="clock"
version="19.2"
start="clk_0.clk"
- end="reg_bg_ctrl.system" />
+ end="reg_diag_bg_ring.system" />
<connection
kind="clock"
version="19.2"
start="clk_0.clk"
- end="ram_bg_data.system" />
+ end="ram_diag_bg_ring.system" />
<connection kind="clock" version="19.2" start="clk_0.clk" end="ram_scrap.system" />
<connection
kind="clock"
@@ -36304,12 +36299,12 @@
kind="reset"
version="19.2"
start="clk_0.clk_reset"
- end="reg_bg_ctrl.system_reset" />
+ end="reg_diag_bg_ring.system_reset" />
<connection
kind="reset"
version="19.2"
start="clk_0.clk_reset"
- end="ram_bg_data.system_reset" />
+ end="ram_diag_bg_ring.system_reset" />
<connection
kind="reset"
version="19.2"
@@ -36434,12 +36429,12 @@
kind="reset"
version="19.2"
start="cpu_0.debug_reset_request"
- end="reg_bg_ctrl.system_reset" />
+ end="reg_diag_bg_ring.system_reset" />
<connection
kind="reset"
version="19.2"
start="cpu_0.debug_reset_request"
- end="ram_bg_data.system_reset" />
+ end="ram_diag_bg_ring.system_reset" />
<connection
kind="reset"
version="19.2"
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf
index cc0d5c1e26ce10fe2169e6a44d742783219d3365..25b087e01eaff5071b23e268b6457f1732f25d50 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf
@@ -334,27 +334,27 @@ set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0] -entity top
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0] -entity top
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0] -entity top
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0] -entity top
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0] -entity top
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0] -entity top
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0] -entity top
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0] -entity top
#### LANE 2, 3
@@ -594,4 +594,3 @@ set_location_assignment PIN_J42 -to RING_1_TX[1]
set_location_assignment PIN_G42 -to RING_1_TX[2]
set_location_assignment PIN_F44 -to RING_1_TX[3]
-
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_bg_data.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_diag_bg_ring.ip
similarity index 98%
rename from applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_bg_data.ip
rename to applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_diag_bg_ring.ip
index 45c5d91623b1432196d6fa1c5ee0163ef9d2298f..4574de872512e8035dc3ba1d97b12b77a781b852 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_bg_data.ip
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_diag_bg_ring.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>board_ram_bg_data</ipxact:library>
- <ipxact:name>board_ram_bg_data</ipxact:name>
+ <ipxact:library>board_ram_diag_bg_ring</ipxact:library>
+ <ipxact:name>board_ram_diag_bg_ring</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>board_ram_bg_data</ipxact:library>
+ <ipxact:library>board_ram_diag_bg_ring</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="board_ram_bg_data.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="board_ram_diag_bg_ring.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="board_ram_bg_data.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="board_ram_diag_bg_ring.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="board_ram_bg_data.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="board_ram_diag_bg_ring.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="board_ram_bg_data.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="board_ram_diag_bg_ring.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="board_ram_bg_data.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="board_ram_diag_bg_ring.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="board_ram_bg_data.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="board_ram_diag_bg_ring.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="board_ram_bg_data.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="board_ram_diag_bg_ring.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="board_ram_bg_data.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="board_ram_diag_bg_ring.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="board_ram_bg_data.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="board_ram_diag_bg_ring.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="board_ram_bg_data.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="board_ram_diag_bg_ring.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bg_ctrl.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_diag_bg_ring.ip
similarity index 98%
rename from applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bg_ctrl.ip
rename to applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_diag_bg_ring.ip
index 2f828fe1b16d544d45fcf6dc863675021446d1c2..0abc1ad4a0529da24ba60b3460b884fddbedd5c5 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bg_ctrl.ip
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_diag_bg_ring.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>board_reg_bg_ctrl</ipxact:library>
- <ipxact:name>board_reg_bg_ctrl</ipxact:name>
+ <ipxact:library>board_reg_diag_bg_ring</ipxact:library>
+ <ipxact:name>board_reg_diag_bg_ring</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>board_reg_bg_ctrl</ipxact:library>
+ <ipxact:library>board_reg_diag_bg_ring</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="board_reg_bg_ctrl.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="board_reg_diag_bg_ring.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="board_reg_bg_ctrl.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="board_reg_diag_bg_ring.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="board_reg_bg_ctrl.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="board_reg_diag_bg_ring.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="board_reg_bg_ctrl.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="board_reg_diag_bg_ring.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_bg_ctrl.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_diag_bg_ring.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="board_reg_bg_ctrl.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="board_reg_diag_bg_ring.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="board_reg_bg_ctrl.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="board_reg_diag_bg_ring.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_bg_ctrl.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_diag_bg_ring.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="board_reg_bg_ctrl.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="board_reg_diag_bg_ring.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_bg_ctrl.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_diag_bg_ring.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf
index 5bcf8942d90679ff650c629d5d3e09ff1345b178..dd4da688b7142a5fdab7b917d3c933505163710c 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf
@@ -66,6 +66,7 @@ set_global_assignment -name IP_FILE ip/board/board_reg_remu.ip
set_global_assignment -name IP_FILE ip/board/board_jtag_uart_0.ip
set_global_assignment -name IP_FILE ip/board/board_kernel_clk.ip
set_global_assignment -name IP_FILE ip/board/board_reg_ta2_unb2b_mm_io.ip
-set_global_assignment -name IP_FILE ip/board/board_reg_bg_ctrl.ip
-set_global_assignment -name IP_FILE ip/board/board_ram_bg_data.ip
set_global_assignment -name IP_FILE ip/board/board_ram_scrap.ip
+set_global_assignment -name IP_FILE ip/board/board_kclk_global.ip
+set_global_assignment -name IP_FILE ip/board/board_ram_diag_bg_ring.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_diag_bg_ring.ip
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index c079af5e23601ca5d282b22dce0b105cb599f5a0..0703a62044c55866498e9e2c846bfe5ee76b604a 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -921,17 +921,17 @@ BEGIN
ram_scrap_write_export => ram_scrap_mosi.wr,
ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_bg_data_address_export => ram_bg_data_mosi.address(6 DOWNTO 0),
- ram_bg_data_read_export => ram_bg_data_mosi.rd,
- ram_bg_data_readdata_export => ram_bg_data_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_bg_data_write_export => ram_bg_data_mosi.wr,
- ram_bg_data_writedata_export => ram_bg_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- reg_bg_ctrl_address_export => reg_bg_ctrl_mosi.address(2 DOWNTO 0),
- reg_bg_ctrl_read_export => reg_bg_ctrl_mosi.rd,
- reg_bg_ctrl_readdata_export => reg_bg_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bg_ctrl_write_export => reg_bg_ctrl_mosi.wr,
- reg_bg_ctrl_writedata_export => reg_bg_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_ring_address_export => ram_bg_data_mosi.address(6 DOWNTO 0),
+ ram_diag_bg_ring_read_export => ram_bg_data_mosi.rd,
+ ram_diag_bg_ring_readdata_export => ram_bg_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_ring_write_export => ram_bg_data_mosi.wr,
+ ram_diag_bg_ring_writedata_export => ram_bg_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_bg_ring_address_export => reg_bg_ctrl_mosi.address(2 DOWNTO 0),
+ reg_diag_bg_ring_read_export => reg_bg_ctrl_mosi.rd,
+ reg_diag_bg_ring_readdata_export => reg_bg_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_ring_write_export => reg_bg_ctrl_mosi.wr,
+ reg_diag_bg_ring_writedata_export => reg_bg_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
kernel_cra_waitrequest => board_kernel_cra_waitrequest,
kernel_cra_readdata => board_kernel_cra_readdata,
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
index cb8399ce9e2f7928a3b74a70b920d253618b57d4..b278ee0e6d25094d175ae0de17993c1a7114999e 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
@@ -83,13 +83,13 @@ PACKAGE top_components_pkg IS
pio_system_info_write_export : out std_logic; -- export
pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
pio_wdi_external_connection_export : out std_logic; -- export
- ram_bg_data_reset_export : out std_logic; -- export
- ram_bg_data_clk_export : out std_logic; -- export
- ram_bg_data_address_export : out std_logic_vector(6 downto 0); -- export
- ram_bg_data_write_export : out std_logic; -- export
- ram_bg_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bg_data_read_export : out std_logic; -- export
- ram_bg_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_ring_reset_export : out std_logic; -- export
+ ram_diag_bg_ring_clk_export : out std_logic; -- export
+ ram_diag_bg_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ ram_diag_bg_ring_write_export : out std_logic; -- export
+ ram_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_ring_read_export : out std_logic; -- export
+ ram_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_scrap_reset_export : out std_logic; -- export
ram_scrap_clk_export : out std_logic; -- export
ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
@@ -97,13 +97,13 @@ PACKAGE top_components_pkg IS
ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_scrap_read_export : out std_logic; -- export
ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bg_ctrl_reset_export : out std_logic; -- export
- reg_bg_ctrl_clk_export : out std_logic; -- export
- reg_bg_ctrl_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bg_ctrl_write_export : out std_logic; -- export
- reg_bg_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bg_ctrl_read_export : out std_logic; -- export
- reg_bg_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_ring_reset_export : out std_logic; -- export
+ reg_diag_bg_ring_clk_export : out std_logic; -- export
+ reg_diag_bg_ring_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_ring_write_export : out std_logic; -- export
+ reg_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_ring_read_export : out std_logic; -- export
+ reg_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
reg_dpmm_ctrl_clk_export : out std_logic; -- export
reg_dpmm_ctrl_read_export : out std_logic; -- export