diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/const_connector/1/const_connector.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/common/const_connector/1/const_connector.vhd
deleted file mode 100644
index 0bcbf3ecc6ace7d13aa14222cb5af91d9ccace99..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/const_connector/1/const_connector.vhd
+++ /dev/null
@@ -1,70 +0,0 @@
-
-------------------------------------------------------------------------------
--- Filename: fsl_const
--- Version: 1.00.a
--- Description: Example FSL core (VHDL).
--- Date: Mon May 24 13:16:55 2010 (by Create and Import Peripheral Wizard)
--- VHDL Standard: VHDL'93
-------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port: "*_i"
--- device pins: "*_pin"
--- ports: "- Names begin with Uppercase"
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>"
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-------------------------------------------------------------------------------
--- Entity Section
-------------------------------------------------------------------------------
-
-------------------------------------------------------------------------------
--- Entity Section
-------------------------------------------------------------------------------
-
-entity common_const_connector is
- generic (
- C_FSL_CONST : integer := 0;
- C_FSL_DWIDTH : integer := 31
- );
- port
- (
- FSL_M_CLK : out std_logic;
- FSL_M_Wr : out std_logic;
- FSL_M_Dout : out std_logic_vector(C_FSL_DWIDTH downto 0);
- FSL_M_CTRL : out std_logic;
- FSL_M_Full : in std_logic;
- RST : in std_logic;
- CLK : in std_logic
-
- );
-end common_const_connector;
-
-------------------------------------------------------------------------------
--- Architecture Section
-------------------------------------------------------------------------------
-
-architecture RTL of common_const_connector is
-begin
- FSL_M_CLK <= '0';
- FSL_M_Dout <= STD_LOGIC_VECTOR(TO_SIGNED(C_FSL_CONST,C_FSL_DWIDTH+1));
- FSL_M_CTRL <= '0';
- FSL_M_Wr <= '1';
-end architecture RTL;
-
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/counter.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/counter.vhd
deleted file mode 100644
index c5fdca2e402f10363d018607b27278ca3201114a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/counter.vhd
+++ /dev/null
@@ -1,88 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity counter is
- generic(
- C_STEP : natural := 1;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
-end counter;
-
-architecture RTL of counter is
-
- signal sl_counter : unsigned(C_WIDTH-1 downto 0);
- signal sl_register : unsigned(C_WIDTH-1 downto 0);
- signal sl_LOWER_BND : unsigned(C_WIDTH-1 downto 0);
- signal sl_UPPER_BND : unsigned(C_WIDTH-1 downto 0);
- signal sl_last_count : std_logic;
- signal sl_done : std_logic;
-
-begin
-
- ITERATOR(C_WIDTH-1 downto 0) <= STD_LOGIC_VECTOR(sl_counter);
- REG_CNTR(C_WIDTH-1 downto 0) <= STD_LOGIC_VECTOR(sl_register);
-
- sl_LOWER_BND <= UNSIGNED(LOWER_BND(C_WIDTH-1 downto 0));
- sl_UPPER_BND <= UNSIGNED(UPPER_BND(C_WIDTH-1 downto 0));
-
-
- sl_counter <= sl_LOWER_BND when (sl_done='1' or RST='1' or LOAD='1') else (sl_register + C_STEP);
- --sl_last_count <= '1' when (sl_counter >= sl_UPPER_BND) else '0';
- sl_last_count <= '1' when (sl_register >= sl_UPPER_BND) else '0';
- sl_done <= sl_last_count;
- --
- DONE <= sl_done;
-
- REG_PRCS : process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST='1' or LOAD ='1' ) then
- sl_register <= sl_LOWER_BND;
- --sl_done <= sl_last_count; -- special case: (sl_LOWER_BND == sl_UPPER_BND)
- elsif( ENABLE='1' ) then
- sl_register <= sl_counter;
- --sl_done <= sl_last_count;
- end if;
- end if;
- end process;
-
-end RTL;
\ No newline at end of file
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/parameters.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/parameters.vhd
deleted file mode 100644
index 1f000535e451cd10044ffcbcac2ee714a35bb07a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/parameters.vhd
+++ /dev/null
@@ -1,166 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity PARAMETERS is
- generic (
- PAR_WIDTH : natural;
- PAR_BITWIDTH : natural;
- PAR_VECTOR : t_par_vector;
- N_PAR : natural
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
- PARAMETERS : out std_logic_vector(PAR_BITWIDTH-1 downto 0)
- );
-end PARAMETERS;
-
-architecture RTL of PARAMETERS is
-
- --constant N_PAR : natural := PAR_VECTOR'Length-2; -- The last two elements in PAR_VECTOR are always a dummy component
- -- we will always read all the paramerets in parallel
- --constant N_PAR : natural := 1;
-
- signal sl_tmp_parameters : std_logic_vector(N_PAR*PAR_WIDTH-1 downto 0);
- signal sl_update : std_logic;
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_det_0, sl_det_1, sl_PARAM_LD : std_logic;
-
- type state_type is (s_idle, s_load, s_halt, s_update);
- signal state : state_type;
-
-begin
-
- HALT <= sl_halt;
- sl_halted <= sl_halt and HALTED;
-
- GenLabel1 : if N_PAR > 0 generate
- -- Rising_edge detection of PARAM_LD signal --------------------
- Edge_det_prcss : process(CLK)
- begin
- if falling_edge( CLK ) then
- sl_det_0 <= PARAM_LD;
- sl_det_1 <= sl_det_0;
- end if;
- end process;
-
- sl_PARAM_LD <= sl_det_0 and not(sl_det_1);
-
- -- Load the parameters into a temp buffer ----------------------
- GenLabel2 : if( N_PAR > 1) generate
- shift_reg: process (CLK, RST)
- begin
- if rising_edge(CLK) then -- shift LEFT register
- if( sl_PARAM_LD='1' ) then
-
- sl_tmp_parameters(PAR_WIDTH-1 downto 0) <= PARAM_DT;
- sl_tmp_parameters(N_PAR*PAR_WIDTH-1 downto PAR_WIDTH) <= sl_tmp_parameters((N_PAR-1)*PAR_WIDTH-1 downto 0);
-
- end if;
- end if;
- end process;
- end generate;
-
- GenLable3 : if( N_PAR = 1) generate
- shift_reg: process (CLK, RST)
- begin
- if rising_edge(CLK) then
- if( sl_PARAM_LD='1' ) then
- sl_tmp_parameters(PAR_WIDTH-1 downto 0) <= PARAM_DT;
- end if;
- end if;
- end process;
- end generate;
-
- -- Update the parameters (from the temp buffer) ----------------
- Ld_ctrl_prcss : process(CLK, RST)
- variable b : integer := 0;
- begin
- if rising_edge(CLK) then
- b := 0;
- for i in 0 to N_PAR-1 loop
- if( RST='1' ) then
- --PARAMETERS(i*PAR_WIDTH-1 downto (i-1)*PAR_WIDTH) <= CONV_STD_LOGIC_VECTOR(PAR_VALUES(i-1),PAR_WIDTH);
- --PARAMETERS(PAR_VECTOR(i).bitwidth+b-1 downto b) <= CONV_STD_LOGIC_VECTOR(PAR_VECTOR(i).val_def,PAR_VECTOR(i).bitwidth);
- PARAMETERS(PAR_VECTOR(i).bitwidth+b-1 downto b) <= STD_LOGIC_VECTOR(to_signed(PAR_VECTOR(i).val_def,PAR_VECTOR(i).bitwidth));
- else
- if( sl_update='1' ) then
- PARAMETERS <= sl_tmp_parameters;
- --PARAMETERS(PAR_VECTOR(i).bitwidth+b-1 downto b) <= sl_tmp_parameters(i*PAR_WIDTH+PAR_VECTOR(i).bitwidth-1 downto i*PAR_WIDTH);
- end if;
- end if;
- b := b + PAR_VECTOR(i).bitwidth;
- end loop;
- end if;
- end process;
-
-
-
-
- FSM: process(CLK, RST)
- variable cntr : natural;
- begin
- if rising_edge(CLK) then
- if( RST='1' ) then
- state <= s_idle;
- cntr := 0;
- else
- case (state) is
- when s_idle => if (sl_PARAM_LD='1') then
- if (cntr>=N_PAR-1) then
- cntr := 0;
- state <= s_load;
- else
- cntr := cntr + 1;
- end if;
- end if;
- when s_load => if (sl_PARAM_LD='0') then state <= s_halt; end if;
- when s_halt => if (sl_halted='1' ) then state <= s_update; end if;
- when s_update => state <= s_idle;
- when others => state <= s_idle;
- end case;
- end if;
- end if;
- end process;
-
- sl_halt <= '1' when (state = s_halt ) else '0';
- sl_update <= '1' when (state = s_update) else '0';
-
-
- end generate; -- GenLabel1
-
-end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/control_if/1/control_if.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/control_if/1/control_if.vhd
deleted file mode 100644
index da9db70dd741abff1dd7c4c85399be892977ccb7..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/control_if/1/control_if.vhd
+++ /dev/null
@@ -1,62 +0,0 @@
--- File automatically generated by KpnMapper
--- For control_if
-
-library ieee;
-use ieee.std_logic_1164.all;
-
---
--- ============================================
--- = PAMETER CONTROLLER =
--- ============================================
---
-
-entity control_if is
- generic (
- RESET_HIGH : natural := 1;
- QUANT : natural := 32
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAM_LD : out std_logic;
- PARAM_DT : out std_logic_vector((32-1) downto 0);
- --
- PARAMETERS_IN_LD : in std_logic;
- PARAMETERS_IN : in std_logic_vector((QUANT-1) downto 0)
-
- );
-end control_if;
-
-architecture fsl_test of control_if is
-
- signal sl_RST : std_logic;
- signal sl_load : std_logic;
- signal sl_data : std_logic_vector((32-1) downto 0);
-
-begin
-
- sl_RST <= RST when (RESET_HIGH=1) else not RST;
-
- process(CLK)
- begin
- if (rising_edge(CLK)) then
- if (sl_RST='1') then
- sl_load <= '0';
- sl_data <= (others=>'0');
- else
- if (sl_load = '1') then
- sl_load <= '0';
- else
- if (PARAMETERS_IN_LD='1') then
- sl_load <= '1';
- sl_data <= PARAMETERS_IN((32-1) downto 0);
- end if;
- end if;
- end if;
- end if;
- end process;
-
- PARAM_LD <= sl_load;
- PARAM_DT <= sl_DATA;
-
-end architecture fsl_test;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0.vhd.bak b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0.vhd.bak
deleted file mode 100644
index 6680385205995f29a45ec0b670b64bc4a079183a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0.vhd.bak
+++ /dev/null
@@ -1,158 +0,0 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-
-
-entity compaan_outlinedproc0 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end compaan_outlinedproc0;
-
-architecture RTL of compaan_outlinedproc0 is
-
- component compaan_outlinedproc0_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : compaan_outlinedproc0_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_tmp1 => ip_tmp1,
- -- Iterators
- it_i => it_i,
- -- Outputs
- op_tmp0 => op_tmp0,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0_pipeline.vhd.bak b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0_pipeline.vhd.bak
deleted file mode 100644
index c0a6cebe5edd074d032703beff9d2c92e2cb43b7..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0_pipeline.vhd.bak
+++ /dev/null
@@ -1,90 +0,0 @@
--- File automatically generated by KpnMapper
--- This file defines a template for pipelined function implementation
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-
-entity compaan_outlinedproc0_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end compaan_outlinedproc0_pipeline;
-
-architecture RTL of compaan_outlinedproc0_pipeline is
---
- constant error_int : integer := -1;
- constant reset_int : std_logic_vector(0 downto 0) := b"0";
- -- Input registers
- signal ipr_tmp1 : std_logic_vector(31 downto 0);
-
- -- Iterator registers
- signal itr_i : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- --
-
- --
- -- Your pipeline signals
- --
- -- STAGE_0
- signal s0_tmp1 : std_logic_vector(31 downto 0);
- signal r0_tmp1 : std_logic_vector(31 downto 0);
-
-begin
-
- PIPE_REGS : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_tmp1 <= ip_tmp1;
- -- Iterator Registers
- itr_i <= it_i;
- end if;
- -- Pipeline Depth: 1 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- r0_tmp1 <= s0_tmp1;
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
- --
- -- PIPE_COMB:
- s0_tmp1 <= ipr_tmp1;
- --
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
- ERROR <= '0';
-end RTL;
-
-
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1.vhd.bak b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1.vhd.bak
deleted file mode 100644
index 57283e65fecadb1cee8e5635d19dd0db41fba006..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1.vhd.bak
+++ /dev/null
@@ -1,158 +0,0 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-
-
-entity compaan_outlinedproc1 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end compaan_outlinedproc1;
-
-architecture RTL of compaan_outlinedproc1 is
-
- component compaan_outlinedproc1_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : compaan_outlinedproc1_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_tmp1 => ip_tmp1,
- -- Iterators
- it_x => it_x,
- -- Outputs
- op_tmp0 => op_tmp0,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1_pipeline.vhd.bak b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1_pipeline.vhd.bak
deleted file mode 100644
index 2efef98e001a9d0fd887b0a6c8c6bfc76025d48d..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1_pipeline.vhd.bak
+++ /dev/null
@@ -1,90 +0,0 @@
--- File automatically generated by KpnMapper
--- This file defines a template for pipelined function implementation
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-
-entity compaan_outlinedproc1_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end compaan_outlinedproc1_pipeline;
-
-architecture RTL of compaan_outlinedproc1_pipeline is
---
- constant error_int : integer := -1;
- constant reset_int : std_logic_vector(0 downto 0) := b"0";
- -- Input registers
- signal ipr_tmp1 : std_logic_vector(31 downto 0);
-
- -- Iterator registers
- signal itr_x : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- --
-
- --
- -- Your pipeline signals
- --
- -- STAGE_0
- signal s0_tmp1 : std_logic_vector(31 downto 0);
- signal r0_tmp1 : std_logic_vector(31 downto 0);
-
-begin
-
- PIPE_REGS : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_tmp1 <= ip_tmp1;
- -- Iterator Registers
- itr_x <= it_x;
- end if;
- -- Pipeline Depth: 1 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- r0_tmp1 <= s0_tmp1;
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
- --
- -- PIPE_COMB:
- s0_tmp1 <= ipr_tmp1;
- --
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
- ERROR <= '0';
-end RTL;
-
-
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer.vhd.bak b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer.vhd.bak
deleted file mode 100644
index e3c981c0783f80b0a2327e6e369bdbf67e6e002f..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer.vhd.bak
+++ /dev/null
@@ -1,158 +0,0 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-
-
-entity transformer is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end transformer;
-
-architecture RTL of transformer is
-
- component transformer_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : transformer_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_a => ip_a,
- -- Iterators
- it_j => it_j,
- -- Outputs
- op_b => op_b,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer_pipeline.vhd.bak b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer_pipeline.vhd.bak
deleted file mode 100644
index 2b89f2b3d49cf83889d0ec7a4b5b1f31ddcfbb41..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer_pipeline.vhd.bak
+++ /dev/null
@@ -1,90 +0,0 @@
--- File automatically generated by KpnMapper
--- This file defines a template for pipelined function implementation
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-
-entity transformer_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end transformer_pipeline;
-
-architecture RTL of transformer_pipeline is
---
- constant error_int : integer := -1;
- constant reset_int : std_logic_vector(0 downto 0) := b"0";
- -- Input registers
- signal ipr_a : std_logic_vector(31 downto 0);
-
- -- Iterator registers
- signal itr_j : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- --
-
- --
- -- Your pipeline signals
- --
- -- STAGE_0
- signal s0_a : std_logic_vector(31 downto 0);
- signal r0_a : std_logic_vector(31 downto 0);
-
-begin
-
- PIPE_REGS : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_a <= ip_a;
- -- Iterator Registers
- itr_j <= it_j;
- end if;
- -- Pipeline Depth: 1 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- r0_a <= s0_a;
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_b <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_a), op_b'Length));
- --
- -- PIPE_COMB:
- s0_a <= ipr_a;
- --
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
- ERROR <= '0';
-end RTL;
-
-
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd
deleted file mode 100644
index b6b3e6533a8afb47ba7a7c84e2b99bf97f52d43b..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd
+++ /dev/null
@@ -1,452 +0,0 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_hwn_nd_1 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 32;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- data_in_Rd : out std_logic;
- data_in_Din : in std_logic_vector(31 downto 0);
- data_in_Exist : in std_logic;
- data_in_CLK : out std_logic;
- data_in_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- -- ED_1 : out_0
- ND_1OP_1_Wr : out std_logic;
- ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_Full : in std_logic;
- ND_1OP_1_CLK : out std_logic;
- ND_1OP_1_CTRL : out std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_hwn_nd_1 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 1; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 1; -- number of global parameters
- constant c_N_PAR : natural := 1; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 32; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- tmp1
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- tmp0
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(31 downto 0)
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(1*32-1 downto 0); -- tmp1
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- tmp1
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- tmp0
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(31 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- data_in_CLK <= CLK;
- ND_1OP_1_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "tmp1"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 1,
- PORT_WIDTH => 32
- )
- port map (
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(0 downto 0),
- READS => sl_READS(0 downto 0),
- SOFS => sl_CTRLS(0 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(0 downto 0),
- OBTAIN => sl_obtain_rd(0 downto 0),
- RELEASE => sl_release_rd(0 downto 0)
- );
-
- data_in_Rd <= sl_READS(0);
-
- sl_IN_PORTS_0 <= data_in_Din;
-
- sl_EXISTS(0) <= data_in_Exist ;
- sl_CTRLS(0) <= data_in_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "tmp0"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 1
- )
- port map (
- WRITES => sl_WRITES(0 downto 0),
- FULLS => sl_FULLS(0 downto 0),
- CONTROL => sl_lortnoc_wr(0 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- ND_1OP_1_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
- ND_1OP_1_CTRL <= sl_sof_wr ;
- ND_1OP_1_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= ND_1OP_1_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_1
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- PARAMETERS => sl_parameters
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) ) );
-
-end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd
deleted file mode 100644
index 9ffe6c0a5e1b98cfa97c0ae9c203337b6330d418..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd
+++ /dev/null
@@ -1,263 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(0 downto 0);
- READ_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_i, sl_high_i : integer;
- signal sl_loop_i, sl_loop_i_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_sof : std_logic;
- signal sl_eof : std_logic;
-
- -- alias signals
- alias update_i : std_logic is sl_cntr_en(0);
- alias load_i : std_logic is sl_load(0);
-
- -- Trigger signals
- signal sl_trigger_i : std_logic;
-
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function input parameter "data_in[i]", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
-
- signal e0, e1 : boolean;
-
- signal sl_obtain0 : std_logic;
- signal sl_release0 : std_logic;
-
- -- define control variables
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments
-
- sl_loop_i <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_i <= 0;
- sl_high_i <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
- -- Special definitions
-
- -- Entity and control variables
- -- Release matrix expressions
- e0 <= sl_loop_i_rg>=0;
- e1 <= -sl_loop_i_rg + 9>=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Read Port in_1 : EXTERNAL
- sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
- sl_release0 <= ('1');
-
- sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
- OBTAIN(0) <= sl_obtain0;
- RELEASE(0) <= sl_release0;
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function input parameter "data_in[i]", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= READ_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
- CNTR_RD : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or HALT='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and HALT='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- REG_CNTRS <= sl_reg_cntrs;
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
- SOF <= sl_sof; -- Start-of-frame
- --
-end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd
deleted file mode 100644
index 9b4dc4d69b77c81f7ff0350d5ee984e21ccfb271..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd
+++ /dev/null
@@ -1,249 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- WRITE_EN : out std_logic_vector(0 downto 0);
- WRITE_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function output parameter "out_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_i, sl_high_i : integer;
- signal sl_loop_i, sl_loop_i_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_eof : std_logic;
- signal sl_sof : std_logic;
- --
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- alias signals
- alias update_i : std_logic is sl_cntr_en(0);
- --
- alias load_i : std_logic is sl_load(0);
- -- Trigger signals
- signal sl_trigger_i : std_logic;
-
-
- -- define control variables
- -- MOD related signals
-
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments
-
- sl_loop_i <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_i <= 0;
- sl_high_i <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
-
- -- Special definitions
-
- -- Entity and control variables
-
- sl_fire <= ('1');
-
- -- Convert FIFO Write Port out_1 : ED_1
- sl_CONTROL(0) <= sl_fire and ('1');
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function output parameter "out_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
- CNTR_WR : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or HALT='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and HALT='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
- SOF <= sl_sof; -- Start-of-frame (FF)
- --
-end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_execution_unit.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_execution_unit.vhd
deleted file mode 100644
index 3e6b0e063fa7ac1a19469aa891404b18631cf97d..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_execution_unit.vhd
+++ /dev/null
@@ -1,102 +0,0 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "tmp1"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "tmp0"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
-
- component compaan_outlinedproc0 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : compaan_outlinedproc0
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_tmp1 => IN_PORT_0,
- -- Iterators
- it_i => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_tmp0 => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd
deleted file mode 100644
index 9b2433bab9e4ba7b8e9630895897c75d4f99505e..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd
+++ /dev/null
@@ -1,453 +0,0 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_hwn_nd_2 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 16;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- -- ED_1 : in_0
- ND_2IP_1_Rd : out std_logic;
- ND_2IP_1_Din : in std_logic_vector(31 downto 0);
- ND_2IP_1_Exist : in std_logic;
- ND_2IP_1_CLK : out std_logic;
- ND_2IP_1_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- -- ED_2 : out_0
- ND_2OP_1_Wr : out std_logic;
- ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_Full : in std_logic;
- ND_2OP_1_CLK : out std_logic;
- ND_2OP_1_CTRL : out std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_2;
-
-architecture RTL of ipcore2RTL_hwn_nd_2 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 1; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 1; -- number of global parameters
- constant c_N_PAR : natural := 1; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 32; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- a
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- b
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(31 downto 0)
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(1*32-1 downto 0); -- a
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- a
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- b
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(31 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- ND_2IP_1_CLK <= CLK;
- ND_2OP_1_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "a"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 1,
- PORT_WIDTH => 32
- )
- port map (
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(0 downto 0),
- READS => sl_READS(0 downto 0),
- SOFS => sl_CTRLS(0 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(0 downto 0),
- OBTAIN => sl_obtain_rd(0 downto 0),
- RELEASE => sl_release_rd(0 downto 0)
- );
-
- ND_2IP_1_Rd <= sl_READS(0);
-
- sl_IN_PORTS_0 <= ND_2IP_1_Din;
-
- sl_EXISTS(0) <= ND_2IP_1_Exist ;
- sl_CTRLS(0) <= ND_2IP_1_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "b"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 1
- )
- port map (
- WRITES => sl_WRITES(0 downto 0),
- FULLS => sl_FULLS(0 downto 0),
- CONTROL => sl_lortnoc_wr(0 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- ND_2OP_1_Dout <= sl_out_port_0; -- Func. Output param. "b"
- ND_2OP_1_CTRL <= sl_sof_wr ;
- ND_2OP_1_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= ND_2OP_1_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_2
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- PARAMETERS => sl_parameters
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) ) );
-
-end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_execution_unit.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_execution_unit.vhd
deleted file mode 100644
index b4223d0c043323cd4c4b2f154e3d63722a04b1cf..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_execution_unit.vhd
+++ /dev/null
@@ -1,102 +0,0 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "a"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "b"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
-
- component transformer is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : transformer
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_a => IN_PORT_0,
- -- Iterators
- it_j => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_b => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd
deleted file mode 100644
index 1d9ddb1c1d1eb3288c172fd31f57cef95f7d0099..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd
+++ /dev/null
@@ -1,454 +0,0 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_hwn_nd_3 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 16;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- -- ED_2 : in_0
- ND_3IP_2_Rd : out std_logic;
- ND_3IP_2_Din : in std_logic_vector(31 downto 0);
- ND_3IP_2_Exist : in std_logic;
- ND_3IP_2_CLK : out std_logic;
- ND_3IP_2_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_hwn_nd_3 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 1; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 1; -- number of global parameters
- constant c_N_PAR : natural := 1; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 32; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- tmp1
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- tmp0
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(31 downto 0)
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(1*32-1 downto 0); -- tmp1
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- tmp1
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- tmp0
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(31 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- ND_3IP_2_CLK <= CLK;
- data_out_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "tmp1"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 1,
- PORT_WIDTH => 32
- )
- port map (
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(0 downto 0),
- READS => sl_READS(0 downto 0),
- SOFS => sl_CTRLS(0 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(0 downto 0),
- OBTAIN => sl_obtain_rd(0 downto 0),
- RELEASE => sl_release_rd(0 downto 0)
- );
-
- ND_3IP_2_Rd <= sl_READS(0);
-
- sl_IN_PORTS_0 <= ND_3IP_2_Din;
-
- sl_EXISTS(0) <= ND_3IP_2_Exist ;
- sl_CTRLS(0) <= ND_3IP_2_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "tmp0"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 1
- )
- port map (
- WRITES => sl_WRITES(0 downto 0),
- FULLS => sl_FULLS(0 downto 0),
- CONTROL => sl_lortnoc_wr(0 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- --data_out_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
- data_out_Dout <= PARAM_DT; -- Func. Output param. "tmp0"
- data_out_CTRL <= sl_sof_wr ;
- data_out_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= data_out_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
-
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_3
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- PARAMETERS => sl_parameters
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) ) );
-
-end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd
deleted file mode 100644
index 25092b29e46c7c0b463714bbab4382bc68c9288a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd
+++ /dev/null
@@ -1,260 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(0 downto 0);
- READ_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_x, sl_high_x : integer;
- signal sl_loop_x, sl_loop_x_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_sof : std_logic;
- signal sl_eof : std_logic;
-
- -- alias signals
- alias update_x : std_logic is sl_cntr_en(0);
- alias load_x : std_logic is sl_load(0);
-
- -- Trigger signals
- signal sl_trigger_x : std_logic;
-
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function input parameter "in_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
-
-
- signal sl_obtain0 : std_logic;
- signal sl_release0 : std_logic;
-
- -- define control variables
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments
-
- sl_loop_x <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_x_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_x <= 0;
- sl_high_x <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
- -- Special definitions
-
- -- Entity and control variables
- -- Release matrix expressions
-
- sl_fire <= ('1');
-
- -- Convert FIFO Read Port ND_3IP_2 Argument in_1 : ED_2 : 0 of type IOMM
- sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
- sl_release0 <= ('1');
-
- sl_CONTROL(0) <= sl_fire and ('1');
- OBTAIN(0) <= sl_obtain0;
- RELEASE(0) <= sl_release0;
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function input parameter "in_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= READ_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
- CNTR_RD : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or HALT='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and HALT='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- REG_CNTRS <= sl_reg_cntrs;
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
- SOF <= sl_sof; -- Start-of-frame
- --
-end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd
deleted file mode 100644
index 9247ea5b07c2b052d50751353c9490ee8827900c..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd
+++ /dev/null
@@ -1,252 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- WRITE_EN : out std_logic_vector(0 downto 0);
- WRITE_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function output parameter "data_out[x]", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_x, sl_high_x : integer;
- signal sl_loop_x, sl_loop_x_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_eof : std_logic;
- signal sl_sof : std_logic;
- --
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- alias signals
- alias update_x : std_logic is sl_cntr_en(0);
- --
- alias load_x : std_logic is sl_load(0);
- -- Trigger signals
- signal sl_trigger_x : std_logic;
-
- signal e0, e1 : boolean;
-
- -- define control variables
- -- MOD related signals
-
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments
-
- sl_loop_x <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_x_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_x <= 0;
- sl_high_x <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
-
- -- Special definitions
-
- -- Entity and control variables
- e0 <= sl_loop_x_rg>=0;
- e1 <= -sl_loop_x_rg + 9>=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Write Port out_1 : EXTERNAL
- sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function output parameter "data_out[x]", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
- CNTR_WR : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or HALT='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and HALT='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
- SOF <= sl_sof; -- Start-of-frame (FF)
- --
-end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_execution_unit.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_execution_unit.vhd
deleted file mode 100644
index 55cd6c920c117de8a69e587dbc709408c9aac39c..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_execution_unit.vhd
+++ /dev/null
@@ -1,102 +0,0 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "tmp1"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "tmp0"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
-
- component compaan_outlinedproc1 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : compaan_outlinedproc1
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_tmp1 => IN_PORT_0,
- -- Iterators
- it_x => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_tmp0 => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/register_rf/1/register_rf.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/register_rf/1/register_rf.vhd
deleted file mode 100644
index e09729b6ed853b977fb9cc22ee936b33a7b6e995..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/register_rf/1/register_rf.vhd
+++ /dev/null
@@ -1,80 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity register_rf is
-generic (
- C_reg_rf_address : std_logic_vector(18 downto 0) := B"0000000000000000000" -- 0
-);
-port (
- rst : in std_logic;
- clk : in std_logic;
-
- -- Interface to PCIe
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0);
-
- -- Interface to reg reg
- reg_rf_read_data : in std_logic_vector(32-1 downto 0);
- reg_rf_read_en : out std_logic;
- reg_rf_write_en : out std_logic;
- reg_rf_write_data : out std_logic_vector(32-1 downto 0)
-);
-end register_rf;
-
-architecture RTL of register_rf is
-
-signal sl_read_data : std_logic_vector(32-1 downto 0) := (others=>'0');
-
-signal mm_clk : std_logic;
-signal mm_rst : std_logic;
-
-begin
-
-mm_clk <= clk;
-mm_rst <= rst;
-
-process (mm_clk, mm_rst)
- begin
- if (rising_edge(mm_clk)) then
- if (mm_rst = '1') then
- reg_rf_write_en <= '0';
- reg_rf_read_en <= '0';
- else
- if ( (address(18 downto 2) = C_reg_rf_address(18 downto 2)) and write_en = '1') then
- reg_rf_write_data <= write_data(32-1 downto 0);
- reg_rf_write_en <= '1';
- else
- reg_rf_write_en <= '0';
- end if;
-
- if( (address(18 downto 2) = C_reg_rf_address(18 downto 2)) and read_en= '1') then
- reg_rf_read_en <= '1';
- else
- reg_rf_read_en <= '0';
- end if;
- end if;
- end if;
-end process;
-
-process (mm_clk, mm_rst)
-begin
- if (rising_edge(mm_clk)) then
- if (mm_rst = '1') then
- else
- case address(18 downto 2) is
- when (C_reg_rf_address(18 downto 2) ) =>
- sl_read_data(32-1 downto 0) <= reg_rf_read_data;
- when others =>
- sl_read_data <= (others => '0');
- end case;
- end if;
- end if;
-end process;
-
-read_data <= sl_read_data;
-
-end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_control_if_ip_wrapper.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_control_if_ip_wrapper.vhd
deleted file mode 100644
index 46f96b1a213fd244f221b2d13462f18f340333ad..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_control_if_ip_wrapper.vhd
+++ /dev/null
@@ -1,53 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_control_if_ip_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity ipcore2RTL_control_if_ip_wrapper is
- port (
- PARAM_DT : out std_logic_vector(31 downto 0);
- PARAM_LD : out std_logic;
- PARAMETERS_IN : in std_logic_vector(31 downto 0);
- PARAMETERS_IN_LD : in std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-
-
-end ipcore2RTL_control_if_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_control_if_ip_wrapper is
-
- component control_if is
- generic (
- RESET_HIGH : NATURAL := 1;
- QUANT : NATURAL := 32
- );
- port (
- PARAM_DT : out std_logic_vector(31 downto 0);
- PARAM_LD : out std_logic;
- PARAMETERS_IN : in std_logic_vector(31 downto 0);
- PARAMETERS_IN_LD : in std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-end component;
-
-begin
-
-ipcore2RTL_control_if_ip_wrapper_ip : control_if
- generic map (
- RESET_HIGH => 1,
- QUANT => 32
- )
- port map (
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- PARAMETERS_IN => PARAMETERS_IN,
- PARAMETERS_IN_LD => PARAMETERS_IN_LD,
- RST => RST,
- CLK => CLK
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/pkg_signals.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/pkg_signals.vhd
deleted file mode 100644
index e84603a434a31af29edf55ed8e95e08e283aff4b..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/pkg_signals.vhd
+++ /dev/null
@@ -1,76 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_ed_1_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-entity pkg_signals is
- generic (
- BLOCKS_PER_SYNC : natural := 10
- );
- port (
- write_in : in std_logic;
- data_in : in std_logic_vector(31 downto 0);
- control_in : in std_logic;
- write_out : out std_logic;
- data_out : out std_logic_vector(31 downto 0);
- control_out : out std_logic;
- eop_out : out std_logic;
- sop_out : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-end pkg_signals;
-
-architecture BEHAVIOURAL of pkg_signals is
-
- signal sync_count : natural;
- signal sl_eop : std_logic;
- signal sl_sop : std_logic;
-
- type state_type is (s_idle, s_count);
- signal sync_state : state_type;
-
-begin
-
- sop_out <= sl_sop;
- eop_out <= sl_eop;
-
- pkg_signals_gen : PROCESS(CLK)
- begin
- if rising_edge(CLK) then
- if RST = '1' then
- sl_sop <= '0';
- sl_eop <= '0';
- sync_state <= s_idle;
- sync_count <= 0;
- else
- write_out <= write_in;
- data_out <= data_in;
- control_out <= control_in;
- sync: case sync_state is
- when s_idle =>
- sl_sop <= write_in;
- sl_eop <= '0';
- if write_in = '1' then
- sync_state <= s_count;
- sync_count <= 0;
- end if;
- when s_count =>
- sl_sop <= '0';
- if sync_count < BLOCKS_PER_SYNC - 2 then
- sync_count <= sync_count + 1;
- else
- sl_eop <= '1';
- sync_state <= s_idle;
- end if;
- when others =>
- sync_state <= s_idle;
- end case;
- end if;
- end if;
- end process;
-
-end architecture;
-
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/altera/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/altera/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..42fe0e0764cc98cf28e4e7092396789f8a613d29
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/altera/hdllib.cfg
@@ -0,0 +1,15 @@
+hdl_lib_name = compaandesign_com_common_altera_1
+hdl_library_clause_name = compaandesign_com_common_altera_1_lib
+hdl_lib_uses_synth = common dp
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/fsl_v20.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/altera/1/fsl_v20.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/altera/src/vhdl/fsl_v20.vhd
similarity index 96%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/altera/1/fsl_v20.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/altera/src/vhdl/fsl_v20.vhd
index 096f7ef40195318da53d7267cc9750a4129784d5..eba84b460a27920e412dbb066887d91a73ff06a8 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/altera/1/fsl_v20.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/altera/src/vhdl/fsl_v20.vhd
@@ -165,7 +165,7 @@ begin
g_use_ctrl => FALSE, -- sop & eop
g_use_complex => FALSE, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
g_fifo_size => C_FSL_DEPTH, -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin => 1, -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin => 4, -- >=4, Nof words below max (full) at which fifo is considered almost full
g_fifo_rl => 0
)
PORT MAP (
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/common/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/common/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..f2be4df5fd77c6368f30c19e360bbf75532c9998
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/common/hdllib.cfg
@@ -0,0 +1,15 @@
+hdl_lib_name = compaandesign_com_common_common_1
+hdl_library_clause_name = compaandesign_com_common_common_1_lib
+hdl_lib_uses_synth =
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/hw_node_pkg.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/common/1/hw_node_pkg.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/common/src/vhdl/hw_node_pkg.vhd
similarity index 100%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/common/1/hw_node_pkg.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/common/src/vhdl/hw_node_pkg.vhd
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/const_connector/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/const_connector/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..b0677c9a95e5cee494314c618b795e0d4713fa01
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/const_connector/hdllib.cfg
@@ -0,0 +1,15 @@
+hdl_lib_name = compaandesign_com_common_const_connector_1
+hdl_library_clause_name = compaandesign_com_common_const_connector_1_lib
+hdl_lib_uses_synth =
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/const_connector.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/const_connector/src/vhdl/const_connector.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/const_connector/src/vhdl/const_connector.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cc0efa40a6eb2230096e10222bc9230d2903b671
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/const_connector/src/vhdl/const_connector.vhd
@@ -0,0 +1,68 @@
+-- COPYRIGHT NOTICE (NOT TO BE REMOVED):
+--
+-- This file, or parts of it, or modified versions of it, may not be
+-- copied, reproduced or transmitted in any form, including
+-- reprinting, translation, photocopying or microfilming, or by any
+-- means, electronic, mechanical or otherwise, or stored in a
+-- retrieval system, or used for any purpose, without the prior
+-- written permission of all Owners unless it is explicitly marked as
+-- having Classification `Public'.
+--
+-- Classification: Restricted.
+--
+-- Owners of this file give notice:
+-- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
+-- All rights, including copyrights, reserved.
+--
+-- This file contains or may contain restricted information and is
+-- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
+-- Notice(s) above do not evidence any actual or intended publication
+-- of such source code. This file is additionally subject to the
+-- conditions listed in the RESTRICTIONS file and is with NOWARRANTY.
+--
+-- END OF COPYRIGHT NOTICE
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+------------------------------------------------------------------------------
+-- Entity Section
+------------------------------------------------------------------------------
+
+------------------------------------------------------------------------------
+-- Entity Section
+------------------------------------------------------------------------------
+
+entity common_const_connector is
+ generic (
+ C_FSL_CONST : integer := 0;
+ C_FSL_DWIDTH : integer := 31
+ );
+ port
+ (
+ FSL_M_CLK : out std_logic;
+ FSL_M_Wr : out std_logic;
+ FSL_M_Dout : out std_logic_vector(C_FSL_DWIDTH downto 0);
+ FSL_M_CTRL : out std_logic;
+ FSL_M_Full : in std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+
+ );
+end common_const_connector;
+
+------------------------------------------------------------------------------
+-- Architecture Section
+------------------------------------------------------------------------------
+
+architecture RTL of common_const_connector is
+begin
+ FSL_M_CLK <= '0';
+ FSL_M_Dout <= STD_LOGIC_VECTOR(TO_SIGNED(C_FSL_CONST,C_FSL_DWIDTH+1));
+ FSL_M_CTRL <= '0';
+ FSL_M_Wr <= '1';
+end architecture RTL;
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/extern_connector/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/extern_connector/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..1e07fc0d1a6bf57592bac686707bc1d193e92e9a
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/extern_connector/hdllib.cfg
@@ -0,0 +1,15 @@
+hdl_lib_name = compaandesign_com_common_extern_connector_1
+hdl_library_clause_name = compaandesign_com_common_extern_connector_1_lib
+hdl_lib_uses_synth =
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/extern_connector.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/extern_connector/1/extern_connector.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/extern_connector/src/vhdl/extern_connector.vhd
similarity index 100%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/extern_connector/1/extern_connector.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/extern_connector/src/vhdl/extern_connector.vhd
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..b72c7f121fb7b58492eca41fb1091c79a40c0d7e
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/hdllib.cfg
@@ -0,0 +1,21 @@
+hdl_lib_name = compaandesign_com_common_fifo_1
+hdl_library_clause_name = compaandesign_com_common_fifo_1_lib
+hdl_lib_uses_synth = compaandesign_com_common_altera_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/async_fifo_bram.vhd
+ src/vhdl/async_fifo.vhd
+ src/vhdl/fsl_v20.vhd
+ src/vhdl/gen_srlfifo.vhd
+ src/vhdl/gen_sync_bram.vhd
+ src/vhdl/gen_sync_dpram.vhd
+ src/vhdl/sync_fifo.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/async_fifo.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/async_fifo.vhd
similarity index 97%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/async_fifo.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/async_fifo.vhd
index 5a06a0806d756e8b7d41435b93c880dc9fa96b07..b24bdb7814319255cf045ca608208ad591d05abc 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/async_fifo.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/async_fifo.vhd
@@ -1,573 +1,573 @@
--------------------------------------------------------------------------------
--- $Id: async_fifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- Async_FIFO.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: Async_FIFO.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- Async_FIFO.vhd
---
--------------------------------------------------------------------------------
--- Author: goran
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- goran 2003-10-27 First Version
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.Std_Logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Async_FIFO is
- generic (
- WordSize : Integer := 8;
- MemSize : Integer := 16;
- Protect : Boolean := False
- );
- port (
- Reset : in Std_Logic;
- -- Clock region WrClk
- WrClk : in Std_Logic;
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- -- Clock region RdClk
- RdClk : in Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic
- );
-end Async_FIFO;
-
-architecture VHDL_RTL of ASync_FIFO is
-
- -----------------------------------------------------------------------------
- -- A function which tries to calculate the best Mem_Size and by that the best
- -- counting scheme
- -----------------------------------------------------------------------------
- function Calculate_Right_Mem_Size (Mem_Size : in Natural) return Integer is
- begin -- Calculate_Right_Mem_Size
- case Mem_Size is
- when 0 to 3 =>
- assert false report "To small FIFO" severity failure;
- return 0;
- when 4 to 16 => return 16;
- when 17 to 32 => return 32;
- when 33 to 64 => return 64;
- when 65 to 128 =>
- -- Do not yet need to check if to use the up/down counting scheme since
- -- there is not true 7-bit counter implemented yet
- return ((MemSize+15)/16)*16;
- when others =>
- assert false
- report "Unsupported FIFO Depth (Not yet implemented)"
- severity failure;
- return 0;
- end case;
- end Calculate_Right_Mem_Size;
-
- -----------------------------------------------------------------------------
- -- Create a resolved Boolean type (rboolean)
- -----------------------------------------------------------------------------
-
- -- Create a Boolean array type
- type boolean_array is array (natural range <>) of boolean;
-
- -- Function for resolved boolean
- -- If any boolean in the array is false, then the result is false
- function resolve_boolean( values: in boolean_array ) return boolean is
- variable result: boolean := TRUE;
- begin
- if (values'length = 1) then
- result := values(values'low);
- else
- -- coverage off
- for index in values'range loop
- if values(index) = FALSE then
- result := FALSE;
- end if;
- end loop;
- -- coverage on
- end if;
- return result;
- end function resolve_boolean;
-
- subtype rboolean is resolve_boolean boolean;
-
-
- -- Convert the FIFO memsize to memsizes in steps of 16
- constant True_Mem_Size : Integer := Calculate_Right_Mem_Size(MemSize);
-
--- component Gen_DpRAM
--- generic (
--- Use_Muxes : Boolean := False;
--- Mem_Size : Integer := 36;
--- Addr_Size : Integer := 6;
--- Data_Size : Integer := 16
--- );
--- port (
--- Reset : in Std_Logic;
--- -- Read/Write port 1
--- Addr1 : in Std_Logic_Vector(Addr_Size-1 downto 0);
--- WrClk : in Std_Logic;
--- WE : in Std_Logic;
--- DataIn : in Std_Logic_Vector(Data_Size-1 downto 0);
--- DataOut1 : out Std_Logic_Vector(Data_Size-1 downto 0);
--- -- Read port 2
--- Addr2 : in Std_Logic_Vector(Addr_Size-1 downto 0);
--- DataOut2 : out Std_Logic_Vector(Data_Size-1 downto 0)
--- );
--- end component;
-
- ----------------------------------------------------------------------
- -- Returns the vector size needed to represent the X
- -- The result is > 0
- ----------------------------------------------------------------------
- function Vec_Size( X : in Natural) return Natural is
- variable I : Natural := 1;
- begin
- while (2**I) < X loop
- I := I + 1;
- end loop;
- return I;
- end function Vec_Size;
-
- -- Declare the types and constant counting schemes
- subtype Count_Word is Std_Logic_Vector(3 downto 0);
- type Count_Array_Type is array (integer range <>) of Count_Word;
-
- -- Even if there is four bits for the Cnt8, the fourth bit will never be used
- constant Cnt8 : Count_Array_Type(0 to 7) := ( "0000","0001","0011","0010",
- "0110","0111","0101","0100");
- constant Cnt10 : Count_Array_Type(0 to 9) := ( "0000","1000","1001","0001",
- "0011","0010","0110","0111",
- "0101","0100" );
- constant Cnt12 : Count_Array_Type(0 to 11) := ( "0000","1000","1001","1011",
- "1010","0010","0011","0001",
- "0101","0111","0110","0100" );
- constant Cnt14 : Count_Array_Type(0 to 13) := ( "0000","1000","1100","1101",
- "1001","1011","1010","0010",
- "0011","0001","0101","0111",
- "0110","0100");
- constant Cnt16 : Count_Array_Type(0 to 15) := ( "0000","0001","0011","0010",
- "0110","0100","0101","0111",
- "1111","1110","1100","1101",
- "1001","1011","1010","1000");
-
- -----------------------------------------------------------------------------
- -- A function that do all the boolean equations for a counting scheme
- -- given as a parameter
- -- The synthesis tool will unroll the loops and then do the boolean equation
- -- minimization (hopefully the optimimal).
- -- At present it only handles counting scheme with 4 bits due to the
- -- Count_Array_Type definition
- -----------------------------------------------------------------------------
- function Gen_Counter(Count_Scheme : in Count_Array_Type;
- Up : in Boolean;
- Count : in Std_Logic_Vector)
- return Std_Logic_Vector is
- variable Temp : Std_Logic;
- variable L : Integer range Count_Scheme'Range;
- variable Q : Std_Logic_Vector(Count'Length-1 downto 0);
- variable Q_Temp : Std_Logic_Vector(Count'Length-1 downto 0);
- begin -- Gen_Counter
- Q := Count;
- for G in Q'Range loop
- Q_Temp(G) := '0';
- for I in Count_Scheme'range loop
- if Count_Scheme(I)(G) = '1' then
- if Up then
- L := I - 1;
- else
- if I /= Count_Scheme'High then
- L := I + 1;
- else
- L := Count_Scheme'Low;
- end if;
- end if;
- Temp := '1';
- for J in Q'Range loop
- if Count_Scheme(L)(J) = '1' then
- Temp := Temp and Q(J);
- else
- Temp := Temp and not Q(J);
- end if;
- end loop;
- Q_Temp(G) := Q_Temp(G) or Temp;
- end if;
- end loop; -- I
- end loop; -- G
- return Q_Temp;
- end Gen_Counter;
-
- ----------------------------------------------------------------------
- -- Generate the Address counter for FIFO handling
- -- generates different counters depending of the counter size
- ----------------------------------------------------------------------
- Procedure FIFO_Count( Count : inout Std_Logic_Vector;
- Incr : in Boolean;
- Up : inout Boolean;
- Change : inout Boolean) is
- variable Cnt : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
- variable Res : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
- begin
- if True_Mem_Size = 16 then
- if Incr then
- Res := Gen_Counter(Cnt16,True,Cnt);
- end if;
- elsif True_Mem_Size = 32 then
- if Incr then
- if not Change and
- (( (Cnt(2 downto 0) = "100") and Up) or
- ( (Cnt(2 downto 0) = "000") and not Up)) then
- Res(4) := Cnt(3);
- Res(3) := not Cnt(4);
- Res(2 downto 0) := Cnt(2 downto 0);
- Up := not Up;
- Change := True;
- else
- Change := False;
- Res(4 downto 3) := Cnt(4 downto 3);
- Res(2 downto 0) := Gen_Counter(Cnt8,Up,Cnt(2 downto 0));
- end if;
- end if;
- elsif True_Mem_Size = 64 then
- if Incr then
- if not Change and
- (( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
- ( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
- Res(5) := Cnt(4);
- Res(4) := not Cnt(5);
- Res(3 downto 0) := Cnt(3 downto 0);
- Up := not Up;
- Change := True;
- else
- Change := False;
- Res(5 downto 4) := Cnt(5 downto 4);
- Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
- end if;
- end if;
- elsif True_Mem_Size = 128 then
- -- Do a 3-bit grey counter + a 4-bit grey counter
- if Incr then
- if not Change and
- (( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
- ( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
- Res(6 downto 4) := Gen_Counter(Cnt8,True,Cnt(6 downto 4));
- Res(3 downto 0) := Cnt(3 downto 0);
- Up := not Up;
- Change := True;
- else
- Change := False;
- Res(6 downto 4) := Cnt(6 downto 4);
- Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
- end if;
- end if;
- else
- assert false
- report "To BIG FIFO (not yet supported)"
- severity failure;
- end if;
- Count := Res;
- end FIFO_Count;
-
- Procedure FIFO_Counter( signal Count : inout Std_Logic_Vector;
- Incr : in Boolean;
- Up : inout Boolean;
- Change : inout Boolean) is
- variable Res : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
- begin
- FIFO_Count(Res,Incr,Up,Change);
- Count <= Res;
- end FIFO_Counter;
-
- constant Log2_Mem_Size : Integer := Vec_Size(True_Mem_Size);
-
- -- The read and write pointers
- subtype Pointer_Type is Std_Logic_Vector(Log2_Mem_Size-1 downto 0);
- signal Write_Ptr : Pointer_Type;
- signal Read_Ptr : Pointer_Type;
- signal Write_Addr : Pointer_Type;
- signal Read_Addr : Pointer_Type;
-
- signal DataOut1 : Std_Logic_Vector(WordSize-1 downto 0); -- NOT USED
-
- signal Dir_Latched : Boolean;
- signal Direction : Boolean;
- signal Equal : Boolean;
- signal Full_I : Boolean;
- signal Empty_I : Boolean;
- signal Full_Out : Boolean;
- signal Empty_Out : Boolean;
-
- signal Read : rboolean;
- signal Write : rboolean;
-
- -----------------------------------------------------------------------------
- -- Implement the RAM with pure RTL
- -----------------------------------------------------------------------------
- type RAM_TYPE is array (natural range 0 to MemSize-1) of std_logic_vector(WordSize-1 downto 0);
- signal Memory : RAM_TYPE := (others => (others => '0'));
-
-begin
-
- -----------------------------------------------------------------------------
- -- Change the Read and Write pointer to get the FIFO addresses
- -- This will get the four lowest bits from the Read/Write pointers to be the
- -- higest bits in FIFO addresses. This assures that when the FIFO depth is
- -- not a power of 2, that the FIFO addresses is within the FIFO depth range
- -----------------------------------------------------------------------------
- Do_FIFO_Addr : process (Write_Ptr, Read_Ptr)
- begin -- process Do_FIFO_Addr
- Write_Addr(Write_Addr'High downto Write_Addr'High-3) <=
- Write_Ptr(3 downto 0);
- if Write_Ptr'Length > 4 then
- Write_Addr(Write_Addr'High-4 downto Write_Addr'Low) <=
- Write_Ptr(Write_Ptr'High downto 4);
- end if;
- Read_Addr(Read_Addr'High downto Read_Addr'High-3) <=
- Read_Ptr(3 downto 0);
- if Read_Ptr'Length > 4 then
- Read_Addr(Read_Addr'High-4 downto Read_Addr'Low) <=
- Read_Ptr(Read_Ptr'High downto 4);
- end if;
- end process Do_FIFO_Addr;
-
- ----------------------------------------------------------------------
- -- Instansiate the Dual Port memory
- ----------------------------------------------------------------------
- Write_To_Memory: process (WrClk) is
- begin -- process Write_To_Memory
- if WrClk'event and WrClk = '1' then -- rising clock edge
- if WE = '1' then
- Memory(to_integer(unsigned(Write_Addr))) <= DataIn;
- end if;
- end if;
- end process Write_To_Memory;
-
- DataOut1 <= Memory(to_integer(unsigned(Write_Addr)));
- DataOut <= Memory(to_integer(unsigned(Read_Addr)));
-
--- FIFO_MEM : Gen_DpRAM
--- generic map(
--- Use_Muxes => true,
--- Mem_Size => MemSize,
--- Addr_Size => Log2_Mem_Size,
--- Data_Size => WordSize
--- )
--- port map (
--- Reset => Reset,
--- Addr1 => Write_Addr,
--- WrClk => WrClk,
--- WE => WE,
--- DataIn => DataIn,
--- DataOut1 => DataOut1,
--- Addr2 => Read_Addr,
--- DataOut2 => DataOut
--- );
-
- Protect_FIFO : if Protect generate
- Read <= (Rd = '1') and not Empty_Out;
- Write <= (We = '1') and not Full_Out;
- end generate Protect_FIFO;
-
- Non_Protect_FIFO : if not Protect generate
- Read <= (Rd = '1');
- Write <= (We = '1');
- end generate Non_Protect_FIFO;
- ----------------------------------------------------------------------
- -- Read Pointer
- ----------------------------------------------------------------------
- Read_Ptr_Counter : process(Reset,RdClk)
- variable Up : Boolean;
- variable Change : Boolean;
- begin
- if (Reset = '1') then
- Read_Ptr <= (others => '0');
- Up := True;
- Change := False;
- elsif RdClk'Event and RdClk = '1' then
- FIFO_Counter(Read_Ptr,Read,Up,Change);
- end if;
- end process Read_Ptr_Counter;
-
- ----------------------------------------------------------------------
- -- Write Pointer
- ----------------------------------------------------------------------
- Write_Ptr_Counter : process(Reset,WrClk)
- variable Up : Boolean;
- variable Change : Boolean;
- begin
- if (Reset = '1') then
- Write_Ptr <= (others => '0');
- Up := True;
- Change := False;
- elsif WrClk'Event and WrClk = '1' then
- FIFO_Counter(Write_Ptr,Write,Up,Change);
- end if;
- end process Write_Ptr_Counter;
-
- ----------------------------------------------------------------------
- -- Flag handling
- ----------------------------------------------------------------------
-
- -------------------------------------------------------------------------
- -- Dir_Latched is false after reset and then true after the first write
- ---------------------------------------------------------------------------
- Direction_Latch : process(Reset,WE,WrClk)
- begin
- if (Reset = '1') then
- Dir_Latched <= False;
- elsif WrClk'Event and WrClk = '1' then
- Dir_Latched <= Dir_Latched or (WE = '1');
- end if;
- end process Direction_Latch;
-
- -----------------------------------------------------------------------------
- -- Trying to see if the read pointer is catching up the write pointer or
- -- vice verse
- -- The top two bits of the pointers always counts as follows
- -- 00
- -- 01
- -- 11
- -- 10
- -- 00
- -- ..
- -- So if read pointer is one step behind the write pointer => Reset = True
- -- And if write pointer is one step behind the read pointer => Set = True
- -----------------------------------------------------------------------------
- Direction_Proc : process(Read_Ptr, Write_Ptr, Dir_Latched, Direction)
- variable Set : Boolean;
- variable Clear : Boolean;
- variable Read_MSB : Std_Logic_Vector(1 downto 0);
- variable Write_MSB : Std_Logic_Vector(1 downto 0);
- begin
- Read_MSB := Read_Ptr(Read_Ptr'Left) & Read_Ptr(Read_Ptr'Left-1);
- Write_MSB := Write_Ptr(Write_Ptr'Left) & Write_Ptr(Write_Ptr'Left-1);
- if (Read_MSB = "00" and Write_MSB = "01") or
- (Read_MSB = "01" and Write_MSB = "11") or
- (Read_MSB = "11" and Write_MSB = "10") or
- (Read_MSB = "10" and Write_MSB = "00") then
- Clear := True;
- else
- Clear := False;
- end if;
- if (Write_MSB = "00" and Read_MSB = "01") or
- (Write_MSB = "01" and Read_MSB = "11") or
- (Write_MSB = "11" and Read_MSB = "10") or
- (Write_MSB = "10" and Read_MSB = "00") then
- Set := True;
- else
- Set := False;
- end if;
- Direction <= not ((not Dir_Latched) or Clear or not(Set or Direction));
- end process Direction_Proc;
-
- Equal <= (Read_Ptr = Write_Ptr);
- Full_I <= Equal and Direction;
- Empty_I <= Equal and not Direction;
-
- -- Allow Empty to go active directly since the change is due to a read
- -- which means that the Empty_I is synchronized with RdClk.
- -- But is only allow to go inactive when RdClk is High since the transaction
- -- is due to a Write and Empty_I is NOT synchronized with RdClk.
- -- By this way the Empty is not changed state just before rising edge of RdClk
- Empty_DFF : process(Empty_I,RdClk)
- begin
- if Empty_I then
- Empty_Out <= True;
- elsif RdClk'Event and RdClk = '1' then
- Empty_Out <= Empty_I;
- end if;
- end process Empty_DFF;
-
- Exists <= '0' when Empty_Out else '1';
-
- -- See above but for Full and WrClk
- Full_DFF : process(Full_I,WrClk)
- begin
- if Full_I then
- Full_Out <= True;
- elsif WrClk'Event and WrClk = '1' then
- Full_Out <= Full_I;
- end if;
- end process Full_DFF;
-
- Full <= '1' when Full_Out else '0';
-
-end VHDL_RTL;
-
-
+-------------------------------------------------------------------------------
+-- $Id: async_fifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
+-------------------------------------------------------------------------------
+-- Async_FIFO.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+-------------------------------------------------------------------------------
+-- Filename: Async_FIFO.vhd
+--
+-- Description:
+--
+-- VHDL-Standard: VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:
+-- Async_FIFO.vhd
+--
+-------------------------------------------------------------------------------
+-- Author: goran
+-- Revision: $Revision: 1.1.2.1 $
+-- Date: $Date: 2010/10/28 11:17:56 $
+--
+-- History:
+-- goran 2003-10-27 First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port "*_i"
+-- device pins: "*_pin"
+-- ports: - Names begin with Uppercase
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Async_FIFO is
+ generic (
+ WordSize : Integer := 8;
+ MemSize : Integer := 16;
+ Protect : Boolean := False
+ );
+ port (
+ Reset : in Std_Logic;
+ -- Clock region WrClk
+ WrClk : in Std_Logic;
+ WE : in Std_Logic;
+ DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
+ Full : out Std_Logic;
+ -- Clock region RdClk
+ RdClk : in Std_Logic;
+ RD : in Std_Logic;
+ DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
+ Exists : out Std_Logic
+ );
+end Async_FIFO;
+
+architecture VHDL_RTL of ASync_FIFO is
+
+ -----------------------------------------------------------------------------
+ -- A function which tries to calculate the best Mem_Size and by that the best
+ -- counting scheme
+ -----------------------------------------------------------------------------
+ function Calculate_Right_Mem_Size (Mem_Size : in Natural) return Integer is
+ begin -- Calculate_Right_Mem_Size
+ case Mem_Size is
+ when 0 to 3 =>
+ assert false report "To small FIFO" severity failure;
+ return 0;
+ when 4 to 16 => return 16;
+ when 17 to 32 => return 32;
+ when 33 to 64 => return 64;
+ when 65 to 128 =>
+ -- Do not yet need to check if to use the up/down counting scheme since
+ -- there is not true 7-bit counter implemented yet
+ return ((MemSize+15)/16)*16;
+ when others =>
+ assert false
+ report "Unsupported FIFO Depth (Not yet implemented)"
+ severity failure;
+ return 0;
+ end case;
+ end Calculate_Right_Mem_Size;
+
+ -----------------------------------------------------------------------------
+ -- Create a resolved Boolean type (rboolean)
+ -----------------------------------------------------------------------------
+
+ -- Create a Boolean array type
+ type boolean_array is array (natural range <>) of boolean;
+
+ -- Function for resolved boolean
+ -- If any boolean in the array is false, then the result is false
+ function resolve_boolean( values: in boolean_array ) return boolean is
+ variable result: boolean := TRUE;
+ begin
+ if (values'length = 1) then
+ result := values(values'low);
+ else
+ -- coverage off
+ for index in values'range loop
+ if values(index) = FALSE then
+ result := FALSE;
+ end if;
+ end loop;
+ -- coverage on
+ end if;
+ return result;
+ end function resolve_boolean;
+
+ subtype rboolean is resolve_boolean boolean;
+
+
+ -- Convert the FIFO memsize to memsizes in steps of 16
+ constant True_Mem_Size : Integer := Calculate_Right_Mem_Size(MemSize);
+
+-- component Gen_DpRAM
+-- generic (
+-- Use_Muxes : Boolean := False;
+-- Mem_Size : Integer := 36;
+-- Addr_Size : Integer := 6;
+-- Data_Size : Integer := 16
+-- );
+-- port (
+-- Reset : in Std_Logic;
+-- -- Read/Write port 1
+-- Addr1 : in Std_Logic_Vector(Addr_Size-1 downto 0);
+-- WrClk : in Std_Logic;
+-- WE : in Std_Logic;
+-- DataIn : in Std_Logic_Vector(Data_Size-1 downto 0);
+-- DataOut1 : out Std_Logic_Vector(Data_Size-1 downto 0);
+-- -- Read port 2
+-- Addr2 : in Std_Logic_Vector(Addr_Size-1 downto 0);
+-- DataOut2 : out Std_Logic_Vector(Data_Size-1 downto 0)
+-- );
+-- end component;
+
+ ----------------------------------------------------------------------
+ -- Returns the vector size needed to represent the X
+ -- The result is > 0
+ ----------------------------------------------------------------------
+ function Vec_Size( X : in Natural) return Natural is
+ variable I : Natural := 1;
+ begin
+ while (2**I) < X loop
+ I := I + 1;
+ end loop;
+ return I;
+ end function Vec_Size;
+
+ -- Declare the types and constant counting schemes
+ subtype Count_Word is Std_Logic_Vector(3 downto 0);
+ type Count_Array_Type is array (integer range <>) of Count_Word;
+
+ -- Even if there is four bits for the Cnt8, the fourth bit will never be used
+ constant Cnt8 : Count_Array_Type(0 to 7) := ( "0000","0001","0011","0010",
+ "0110","0111","0101","0100");
+ constant Cnt10 : Count_Array_Type(0 to 9) := ( "0000","1000","1001","0001",
+ "0011","0010","0110","0111",
+ "0101","0100" );
+ constant Cnt12 : Count_Array_Type(0 to 11) := ( "0000","1000","1001","1011",
+ "1010","0010","0011","0001",
+ "0101","0111","0110","0100" );
+ constant Cnt14 : Count_Array_Type(0 to 13) := ( "0000","1000","1100","1101",
+ "1001","1011","1010","0010",
+ "0011","0001","0101","0111",
+ "0110","0100");
+ constant Cnt16 : Count_Array_Type(0 to 15) := ( "0000","0001","0011","0010",
+ "0110","0100","0101","0111",
+ "1111","1110","1100","1101",
+ "1001","1011","1010","1000");
+
+ -----------------------------------------------------------------------------
+ -- A function that do all the boolean equations for a counting scheme
+ -- given as a parameter
+ -- The synthesis tool will unroll the loops and then do the boolean equation
+ -- minimization (hopefully the optimimal).
+ -- At present it only handles counting scheme with 4 bits due to the
+ -- Count_Array_Type definition
+ -----------------------------------------------------------------------------
+ function Gen_Counter(Count_Scheme : in Count_Array_Type;
+ Up : in Boolean;
+ Count : in Std_Logic_Vector)
+ return Std_Logic_Vector is
+ variable Temp : Std_Logic;
+ variable L : Integer range Count_Scheme'Range;
+ variable Q : Std_Logic_Vector(Count'Length-1 downto 0);
+ variable Q_Temp : Std_Logic_Vector(Count'Length-1 downto 0);
+ begin -- Gen_Counter
+ Q := Count;
+ for G in Q'Range loop
+ Q_Temp(G) := '0';
+ for I in Count_Scheme'range loop
+ if Count_Scheme(I)(G) = '1' then
+ if Up then
+ L := I - 1;
+ else
+ if I /= Count_Scheme'High then
+ L := I + 1;
+ else
+ L := Count_Scheme'Low;
+ end if;
+ end if;
+ Temp := '1';
+ for J in Q'Range loop
+ if Count_Scheme(L)(J) = '1' then
+ Temp := Temp and Q(J);
+ else
+ Temp := Temp and not Q(J);
+ end if;
+ end loop;
+ Q_Temp(G) := Q_Temp(G) or Temp;
+ end if;
+ end loop; -- I
+ end loop; -- G
+ return Q_Temp;
+ end Gen_Counter;
+
+ ----------------------------------------------------------------------
+ -- Generate the Address counter for FIFO handling
+ -- generates different counters depending of the counter size
+ ----------------------------------------------------------------------
+ Procedure FIFO_Count( Count : inout Std_Logic_Vector;
+ Incr : in Boolean;
+ Up : inout Boolean;
+ Change : inout Boolean) is
+ variable Cnt : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
+ variable Res : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
+ begin
+ if True_Mem_Size = 16 then
+ if Incr then
+ Res := Gen_Counter(Cnt16,True,Cnt);
+ end if;
+ elsif True_Mem_Size = 32 then
+ if Incr then
+ if not Change and
+ (( (Cnt(2 downto 0) = "100") and Up) or
+ ( (Cnt(2 downto 0) = "000") and not Up)) then
+ Res(4) := Cnt(3);
+ Res(3) := not Cnt(4);
+ Res(2 downto 0) := Cnt(2 downto 0);
+ Up := not Up;
+ Change := True;
+ else
+ Change := False;
+ Res(4 downto 3) := Cnt(4 downto 3);
+ Res(2 downto 0) := Gen_Counter(Cnt8,Up,Cnt(2 downto 0));
+ end if;
+ end if;
+ elsif True_Mem_Size = 64 then
+ if Incr then
+ if not Change and
+ (( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
+ ( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
+ Res(5) := Cnt(4);
+ Res(4) := not Cnt(5);
+ Res(3 downto 0) := Cnt(3 downto 0);
+ Up := not Up;
+ Change := True;
+ else
+ Change := False;
+ Res(5 downto 4) := Cnt(5 downto 4);
+ Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
+ end if;
+ end if;
+ elsif True_Mem_Size = 128 then
+ -- Do a 3-bit grey counter + a 4-bit grey counter
+ if Incr then
+ if not Change and
+ (( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
+ ( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
+ Res(6 downto 4) := Gen_Counter(Cnt8,True,Cnt(6 downto 4));
+ Res(3 downto 0) := Cnt(3 downto 0);
+ Up := not Up;
+ Change := True;
+ else
+ Change := False;
+ Res(6 downto 4) := Cnt(6 downto 4);
+ Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
+ end if;
+ end if;
+ else
+ assert false
+ report "To BIG FIFO (not yet supported)"
+ severity failure;
+ end if;
+ Count := Res;
+ end FIFO_Count;
+
+ Procedure FIFO_Counter( signal Count : inout Std_Logic_Vector;
+ Incr : in Boolean;
+ Up : inout Boolean;
+ Change : inout Boolean) is
+ variable Res : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
+ begin
+ FIFO_Count(Res,Incr,Up,Change);
+ Count <= Res;
+ end FIFO_Counter;
+
+ constant Log2_Mem_Size : Integer := Vec_Size(True_Mem_Size);
+
+ -- The read and write pointers
+ subtype Pointer_Type is Std_Logic_Vector(Log2_Mem_Size-1 downto 0);
+ signal Write_Ptr : Pointer_Type;
+ signal Read_Ptr : Pointer_Type;
+ signal Write_Addr : Pointer_Type;
+ signal Read_Addr : Pointer_Type;
+
+ signal DataOut1 : Std_Logic_Vector(WordSize-1 downto 0); -- NOT USED
+
+ signal Dir_Latched : Boolean;
+ signal Direction : Boolean;
+ signal Equal : Boolean;
+ signal Full_I : Boolean;
+ signal Empty_I : Boolean;
+ signal Full_Out : Boolean;
+ signal Empty_Out : Boolean;
+
+ signal Read : rboolean;
+ signal Write : rboolean;
+
+ -----------------------------------------------------------------------------
+ -- Implement the RAM with pure RTL
+ -----------------------------------------------------------------------------
+ type RAM_TYPE is array (natural range 0 to MemSize-1) of std_logic_vector(WordSize-1 downto 0);
+ signal Memory : RAM_TYPE := (others => (others => '0'));
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Change the Read and Write pointer to get the FIFO addresses
+ -- This will get the four lowest bits from the Read/Write pointers to be the
+ -- higest bits in FIFO addresses. This assures that when the FIFO depth is
+ -- not a power of 2, that the FIFO addresses is within the FIFO depth range
+ -----------------------------------------------------------------------------
+ Do_FIFO_Addr : process (Write_Ptr, Read_Ptr)
+ begin -- process Do_FIFO_Addr
+ Write_Addr(Write_Addr'High downto Write_Addr'High-3) <=
+ Write_Ptr(3 downto 0);
+ if Write_Ptr'Length > 4 then
+ Write_Addr(Write_Addr'High-4 downto Write_Addr'Low) <=
+ Write_Ptr(Write_Ptr'High downto 4);
+ end if;
+ Read_Addr(Read_Addr'High downto Read_Addr'High-3) <=
+ Read_Ptr(3 downto 0);
+ if Read_Ptr'Length > 4 then
+ Read_Addr(Read_Addr'High-4 downto Read_Addr'Low) <=
+ Read_Ptr(Read_Ptr'High downto 4);
+ end if;
+ end process Do_FIFO_Addr;
+
+ ----------------------------------------------------------------------
+ -- Instansiate the Dual Port memory
+ ----------------------------------------------------------------------
+ Write_To_Memory: process (WrClk) is
+ begin -- process Write_To_Memory
+ if WrClk'event and WrClk = '1' then -- rising clock edge
+ if WE = '1' then
+ Memory(to_integer(unsigned(Write_Addr))) <= DataIn;
+ end if;
+ end if;
+ end process Write_To_Memory;
+
+ DataOut1 <= Memory(to_integer(unsigned(Write_Addr)));
+ DataOut <= Memory(to_integer(unsigned(Read_Addr)));
+
+-- FIFO_MEM : Gen_DpRAM
+-- generic map(
+-- Use_Muxes => true,
+-- Mem_Size => MemSize,
+-- Addr_Size => Log2_Mem_Size,
+-- Data_Size => WordSize
+-- )
+-- port map (
+-- Reset => Reset,
+-- Addr1 => Write_Addr,
+-- WrClk => WrClk,
+-- WE => WE,
+-- DataIn => DataIn,
+-- DataOut1 => DataOut1,
+-- Addr2 => Read_Addr,
+-- DataOut2 => DataOut
+-- );
+
+ Protect_FIFO : if Protect generate
+ Read <= (Rd = '1') and not Empty_Out;
+ Write <= (We = '1') and not Full_Out;
+ end generate Protect_FIFO;
+
+ Non_Protect_FIFO : if not Protect generate
+ Read <= (Rd = '1');
+ Write <= (We = '1');
+ end generate Non_Protect_FIFO;
+ ----------------------------------------------------------------------
+ -- Read Pointer
+ ----------------------------------------------------------------------
+ Read_Ptr_Counter : process(Reset,RdClk)
+ variable Up : Boolean;
+ variable Change : Boolean;
+ begin
+ if (Reset = '1') then
+ Read_Ptr <= (others => '0');
+ Up := True;
+ Change := False;
+ elsif RdClk'Event and RdClk = '1' then
+ FIFO_Counter(Read_Ptr,Read,Up,Change);
+ end if;
+ end process Read_Ptr_Counter;
+
+ ----------------------------------------------------------------------
+ -- Write Pointer
+ ----------------------------------------------------------------------
+ Write_Ptr_Counter : process(Reset,WrClk)
+ variable Up : Boolean;
+ variable Change : Boolean;
+ begin
+ if (Reset = '1') then
+ Write_Ptr <= (others => '0');
+ Up := True;
+ Change := False;
+ elsif WrClk'Event and WrClk = '1' then
+ FIFO_Counter(Write_Ptr,Write,Up,Change);
+ end if;
+ end process Write_Ptr_Counter;
+
+ ----------------------------------------------------------------------
+ -- Flag handling
+ ----------------------------------------------------------------------
+
+ -------------------------------------------------------------------------
+ -- Dir_Latched is false after reset and then true after the first write
+ ---------------------------------------------------------------------------
+ Direction_Latch : process(Reset,WE,WrClk)
+ begin
+ if (Reset = '1') then
+ Dir_Latched <= False;
+ elsif WrClk'Event and WrClk = '1' then
+ Dir_Latched <= Dir_Latched or (WE = '1');
+ end if;
+ end process Direction_Latch;
+
+ -----------------------------------------------------------------------------
+ -- Trying to see if the read pointer is catching up the write pointer or
+ -- vice verse
+ -- The top two bits of the pointers always counts as follows
+ -- 00
+ -- 01
+ -- 11
+ -- 10
+ -- 00
+ -- ..
+ -- So if read pointer is one step behind the write pointer => Reset = True
+ -- And if write pointer is one step behind the read pointer => Set = True
+ -----------------------------------------------------------------------------
+ Direction_Proc : process(Read_Ptr, Write_Ptr, Dir_Latched, Direction)
+ variable Set : Boolean;
+ variable Clear : Boolean;
+ variable Read_MSB : Std_Logic_Vector(1 downto 0);
+ variable Write_MSB : Std_Logic_Vector(1 downto 0);
+ begin
+ Read_MSB := Read_Ptr(Read_Ptr'Left) & Read_Ptr(Read_Ptr'Left-1);
+ Write_MSB := Write_Ptr(Write_Ptr'Left) & Write_Ptr(Write_Ptr'Left-1);
+ if (Read_MSB = "00" and Write_MSB = "01") or
+ (Read_MSB = "01" and Write_MSB = "11") or
+ (Read_MSB = "11" and Write_MSB = "10") or
+ (Read_MSB = "10" and Write_MSB = "00") then
+ Clear := True;
+ else
+ Clear := False;
+ end if;
+ if (Write_MSB = "00" and Read_MSB = "01") or
+ (Write_MSB = "01" and Read_MSB = "11") or
+ (Write_MSB = "11" and Read_MSB = "10") or
+ (Write_MSB = "10" and Read_MSB = "00") then
+ Set := True;
+ else
+ Set := False;
+ end if;
+ Direction <= not ((not Dir_Latched) or Clear or not(Set or Direction));
+ end process Direction_Proc;
+
+ Equal <= (Read_Ptr = Write_Ptr);
+ Full_I <= Equal and Direction;
+ Empty_I <= Equal and not Direction;
+
+ -- Allow Empty to go active directly since the change is due to a read
+ -- which means that the Empty_I is synchronized with RdClk.
+ -- But is only allow to go inactive when RdClk is High since the transaction
+ -- is due to a Write and Empty_I is NOT synchronized with RdClk.
+ -- By this way the Empty is not changed state just before rising edge of RdClk
+ Empty_DFF : process(Empty_I,RdClk)
+ begin
+ if Empty_I then
+ Empty_Out <= True;
+ elsif RdClk'Event and RdClk = '1' then
+ Empty_Out <= Empty_I;
+ end if;
+ end process Empty_DFF;
+
+ Exists <= '0' when Empty_Out else '1';
+
+ -- See above but for Full and WrClk
+ Full_DFF : process(Full_I,WrClk)
+ begin
+ if Full_I then
+ Full_Out <= True;
+ elsif WrClk'Event and WrClk = '1' then
+ Full_Out <= Full_I;
+ end if;
+ end process Full_DFF;
+
+ Full <= '1' when Full_Out else '0';
+
+end VHDL_RTL;
+
+
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/async_fifo_bram.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/async_fifo_bram.vhd
similarity index 97%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/async_fifo_bram.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/async_fifo_bram.vhd
index 3a35d050e89c5a144e34909262fa1338354b53f5..3d6d982460490214dbe6aa09350994d7144ad803 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/async_fifo_bram.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/async_fifo_bram.vhd
@@ -1,429 +1,429 @@
--------------------------------------------------------------------------------
--- $Id: async_fifo_bram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- gen_sync_bram.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: rolandp
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- rolandp 2006 New Versionuse IEEE.std_logic_unsigned.all;
-
---
--- Description:
--- Code to infer asynchronous dual port bram
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity Async_FIFO_BRAM is
- generic (
- WordSize : integer := 8;
- MemSize : integer := 16;
- Protect : boolean := false
- );
- port (
- Reset : in std_logic;
- -- Clock region WrClk
- WrClk : in std_logic;
- WE : in std_logic;
- DataIn : in std_logic_vector(WordSize-1 downto 0);
- Full : out std_logic;
- -- Clock region RdClk
- RdClk : in std_logic;
- RD : in std_logic;
- DataOut : out std_logic_vector(WordSize-1 downto 0);
- Exists : out std_logic
- );
-end entity Async_FIFO_BRAM;
-
-architecture IMP of Async_FIFO_BRAM is
-
- attribute ram_style : string;
-
- function Bin2Gray(constant bin : std_logic_vector)
- return std_logic_vector is
- variable gray : std_logic_vector(bin'range);
- begin
- gray(bin'high) := bin(bin'high);
- for I in bin'high - 1 downto bin'low loop
- gray(I) := bin(I + 1) xor bin(I);
- end loop;
- return gray;
- end function Bin2Gray;
-
- function Log2(x : integer) return integer is
- variable i : integer := 0;
- begin
- -- coverage off
- if x = 0 then return 0;
- -- coverage on
- else
- while 2**i < x loop
- i := i+1;
- end loop;
- return i;
- end if;
- end function Log2;
-
- type ram_type is array (2**Log2(MemSize)-1 downto 0) of std_logic_vector(WordSize-1 downto 0);
-
- signal ram_mem : ram_type;
- attribute ram_style of ram_mem : signal is "block";
-
- signal read_enable : std_logic;
- signal write_enable : std_logic;
-
- signal read_allow : std_logic;
- signal write_allow : std_logic;
-
- signal empty_allow : std_logic;
- signal full_allow : std_logic;
-
- signal full_i : std_logic;
- signal empty : std_logic;
-
- signal emptyg : std_logic;
- signal fullg : std_logic;
-
- signal read_addr_next : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_lastgray : std_logic_vector(Log2(MemSize)-1 downto 0);
-
- signal write_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal write_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal write_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
-
- signal ecomp : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal fcomp : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal emuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
- signal fmuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
-
-begin
-
- -- Assign local signals from ports
- read_enable <= RD;
- write_enable <= WE;
-
- -- Memory array
- WritePort : process (WrClk)
- begin
- if (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- ram_mem(To_integer(unsigned(write_addr))) <= DataIn;
- end if;
- end if;
- end process WritePort;
-
- ReadPort : process (RdClk)
- begin
- if (RdClk'event and RdClk = '1') then
- DataOut <= ram_mem(To_integer(unsigned(read_addr_next)));
- end if;
- end process ReadPort;
-
- ----------------------------------------------------------------
- -- Allow flags determine whether FIFO control logic can --
- -- operate. If read_enable is driven high, and the FIFO is --
- -- not Empty, then Reads are allowed. Similarly, if the --
- -- write_enable signal is high, and the FIFO is not Full, --
- -- then Writes are allowed. --
- ----------------------------------------------------------------
-
- read_allow <= (read_enable and not empty);
- write_allow <= (write_enable and not full_i);
-
- ---------------------------------------------------------------
- -- Empty flag is set on Reset (initial), or when gray --
- -- code counters are equal, or when there is one word in --
- -- the FIFO, and a Read operation is about to be performed. --
- ---------------------------------------------------------------
-
- empty_allow <= (empty or read_enable); -- Is empty or possibly going to be empty
-
- EmptyFlag : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- empty <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (empty_allow = '1') then
- empty <= emptyg;
- end if;
- end if;
- end process EmptyFlag;
-
- Exists <= not empty;
-
- ---------------------------------------------------------------
- -- Full flag is set on Reset (initial, but it is cleared --
- -- on the first valid write_clock edge after Reset is --
- -- de-asserted), or when Gray-code counters are one away --
- -- from being equal (the Write Gray-code address is equal --
- -- to the Last Read Gray-code address), or when the Next --
- -- Write Gray-code address is equal to the Last Read Gray- --
- -- code address, and a Write operation is about to be --
- -- performed. --
- ---------------------------------------------------------------
-
- full_allow <= (full_i or write_enable); -- Is full or possibly going to be full
-
- FullFlag : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- full_i <= '1';
- elsif (WrClk'event and WrClk = '1') then
- if (full_allow = '1') then
- full_i <= fullg;
- end if;
- end if;
- end process FullFlag;
-
- Full <= full_i;
-
- ----------------------------------------------------------------
- -- Generation of Read address pointers. The primary one is --
- -- binary (read_addr), and the Gray-code derivatives are --
- -- generated via pipelining the binary-to-Gray-code result. --
- -- The initial values are important, so they're in sequence. --
- -- --
- -- Grey-code addresses are used so that the registered --
- -- Full and Empty flags are always clean, and never in an --
- -- unknown state due to the asynchonous relationship of the --
- -- Read and Write clocks. In the worst case scenario, Full --
- -- and Empty would simply stay active one cycle longer, but --
- -- it would not generate an error or give false values. --
- ----------------------------------------------------------------
-
- read_addr_next <= std_logic_vector(unsigned(read_addr) + 1) when read_allow = '1' else read_addr;
-
- ReadAddrCnt : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_addr <= (others => '0');
- elsif (RdClk'event and RdClk = '1') then
- read_addr <= read_addr_next;
- end if;
- end process ReadAddrCnt;
-
- ReadNextGray : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_nextgray(read_nextgray'high-1 downto 0) <= (others => '0');
- read_nextgray(read_nextgray'high) <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (read_allow = '1') then
- read_nextgray <= Bin2Gray(read_addr);
- end if;
- end if;
- end process ReadNextGray;
-
- ReadAddrGray : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_addrgray(read_addrgray'high-1 downto 1) <= (others => '0');
- read_addrgray(0) <= '1';
- read_addrgray(read_addrgray'high) <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (read_allow = '1') then
- read_addrgray <= read_nextgray;
- end if;
- end if;
- end process ReadAddrGray;
-
- ReadLastGrey : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_lastgray(read_lastgray'high-1 downto 2) <= (others => '0');
- read_lastgray(0) <= '1';
- read_lastgray(1) <= '1';
- read_lastgray(read_lastgray'high) <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (read_allow = '1') then
- read_lastgray <= read_addrgray;
- end if;
- end if;
- end process ReadLastGrey;
-
- ----------------------------------------------------------------
- -- Generation of Write address pointers. Identical copy of --
- -- read pointer generation above, except for names. --
- ----------------------------------------------------------------
-
- WriteAddrCnt : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- write_addr <= (others => '0');
- elsif (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- write_addr <= std_logic_vector(unsigned(write_addr) + 1);
- end if;
- end if;
- end process WriteAddrCnt;
-
- WriteNextGray : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- write_nextgray(write_nextgray'high-1 downto 0) <= (others => '0');
- write_nextgray(write_nextgray'high) <= '1';
- elsif (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- write_nextgray <= Bin2Gray(write_addr);
- end if;
- end if;
- end process WriteNextGray;
-
- WriteAddrGray : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- write_addrgray(write_addrgray'high-1 downto 0) <= (others => '0');
- write_addrgray(0) <= '1';
- write_addrgray(write_addrgray'high) <= '1';
- elsif (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- write_addrgray <= write_nextgray;
- end if;
- end if;
- end process WriteAddrGray;
-
-----------------------------------------------------------------
--- The two conditions decoded with special carry logic are --
--- Empty and Full (gated versions). These are used to --
--- determine the next state of the Full/Empty flags. Carry --
--- logic is used for optimal speed. (The previous --
--- implementation of AlmostEmpty and AlmostFull have been --
--- wrapped into the corresponding carry chains for faster --
--- performance). --
--- --
--- When write_addrgray is equal to read_addrgray, the FIFO --
--- is Empty, and emptyg (combinatorial) is asserted. Or, --
--- when write_addrgray is equal to read_nextgray (1 word in --
--- the FIFO) then the FIFO potentially could be going Empty, --
--- so emptyg is asserted, and the Empty flip-flop enable is --
--- gated with empty_allow, which is conditioned with a valid --
--- read. --
--- --
--- Similarly, when read_lastgray is equal to write_addrgray, --
--- the FIFO is full (511 addresses). Or, when read_lastgray --
--- is equal to write_nextgray, then the FIFO potentially --
--- could be going Full, so fullg is asserted, and the Full --
--- flip-flop enable is gated with full_allow, which is --
--- conditioned with a valid write. --
--- --
--- Note: To have utilized the full address space (512) --
--- would have required extra logic to determine Full/Empty --
--- on equal addresses, and this would have slowed down the --
--- overall performance, which was the top priority. --
-----------------------------------------------------------------
-
- ECompare : process(write_addrgray, read_addrgray, read_nextgray, empty)
- begin
- for I in 0 to Log2(MemSize)-1 loop
- ecomp(I) <= (not (write_addrgray(I) xor read_addrgray(I)) and empty) or
- (not (write_addrgray(I) xor read_nextgray(I)) and not empty);
- end loop;
- end process ECompare;
-
- emuxcylow : MUXCY_L port map(DI => '0', CI => '1', S => ecomp(0), LO => emuxcyo(0));
-
- Gen_emuxcy : for I in 1 to Log2(MemSize)-2 generate
- begin
- emuxcy : MUXCY_L port map(DI => '0', CI => emuxcyo(I-1), S => ecomp(I), LO => emuxcyo(I));
- end generate Gen_emuxcy;
-
- emuxcyhigh : MUXCY_L port map(DI => '0', CI => emuxcyo(Log2(MemSize)-2), S => ecomp(Log2(MemSize)-1), LO => emptyg);
-
- FCompare : process(read_lastgray, write_addrgray, write_nextgray, full_i)
- begin
- for I in 0 to Log2(MemSize)-1 loop
- fcomp(I) <= (not (read_lastgray(I) xor write_addrgray(I)) and full_i) or
- (not (read_lastgray(I) xor write_nextgray(I)) and not full_i);
- end loop;
- end process FCompare;
-
- fmuxcylow : MUXCY_L port map (DI => '0', CI => '1', S => fcomp(0), LO => fmuxcyo(0));
-
- Gen_fmuxcy : for I in 1 to Log2(MemSize)-2 generate
- begin
- fmuxcy : MUXCY_L port map (DI => '0', CI => fmuxcyo(I-1), S => fcomp(I), LO => fmuxcyo(I));
- end generate Gen_fmuxcy;
-
- fmuxcyhigh : MUXCY_L port map (DI => '0', CI => fmuxcyo(Log2(MemSize)-2), S => fcomp(Log2(MemSize)-1), LO => fullg);
-
-end architecture IMP;
-
-
+-------------------------------------------------------------------------------
+-- $Id: async_fifo_bram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
+-------------------------------------------------------------------------------
+-- gen_sync_bram.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+-------------------------------------------------------------------------------
+-- Author: rolandp
+-- Revision: $Revision: 1.1.2.1 $
+-- Date: $Date: 2010/10/28 11:17:56 $
+--
+-- History:
+-- rolandp 2006 New Versionuse IEEE.std_logic_unsigned.all;
+
+--
+-- Description:
+-- Code to infer asynchronous dual port bram
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port "*_i"
+-- device pins: "*_pin"
+-- ports: - Names begin with Uppercase
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity Async_FIFO_BRAM is
+ generic (
+ WordSize : integer := 8;
+ MemSize : integer := 16;
+ Protect : boolean := false
+ );
+ port (
+ Reset : in std_logic;
+ -- Clock region WrClk
+ WrClk : in std_logic;
+ WE : in std_logic;
+ DataIn : in std_logic_vector(WordSize-1 downto 0);
+ Full : out std_logic;
+ -- Clock region RdClk
+ RdClk : in std_logic;
+ RD : in std_logic;
+ DataOut : out std_logic_vector(WordSize-1 downto 0);
+ Exists : out std_logic
+ );
+end entity Async_FIFO_BRAM;
+
+architecture IMP of Async_FIFO_BRAM is
+
+ attribute ram_style : string;
+
+ function Bin2Gray(constant bin : std_logic_vector)
+ return std_logic_vector is
+ variable gray : std_logic_vector(bin'range);
+ begin
+ gray(bin'high) := bin(bin'high);
+ for I in bin'high - 1 downto bin'low loop
+ gray(I) := bin(I + 1) xor bin(I);
+ end loop;
+ return gray;
+ end function Bin2Gray;
+
+ function Log2(x : integer) return integer is
+ variable i : integer := 0;
+ begin
+ -- coverage off
+ if x = 0 then return 0;
+ -- coverage on
+ else
+ while 2**i < x loop
+ i := i+1;
+ end loop;
+ return i;
+ end if;
+ end function Log2;
+
+ type ram_type is array (2**Log2(MemSize)-1 downto 0) of std_logic_vector(WordSize-1 downto 0);
+
+ signal ram_mem : ram_type;
+ attribute ram_style of ram_mem : signal is "block";
+
+ signal read_enable : std_logic;
+ signal write_enable : std_logic;
+
+ signal read_allow : std_logic;
+ signal write_allow : std_logic;
+
+ signal empty_allow : std_logic;
+ signal full_allow : std_logic;
+
+ signal full_i : std_logic;
+ signal empty : std_logic;
+
+ signal emptyg : std_logic;
+ signal fullg : std_logic;
+
+ signal read_addr_next : std_logic_vector(Log2(MemSize)-1 downto 0);
+ signal read_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
+ signal read_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
+ signal read_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
+ signal read_lastgray : std_logic_vector(Log2(MemSize)-1 downto 0);
+
+ signal write_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
+ signal write_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
+ signal write_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
+
+ signal ecomp : std_logic_vector(Log2(MemSize)-1 downto 0);
+ signal fcomp : std_logic_vector(Log2(MemSize)-1 downto 0);
+ signal emuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
+ signal fmuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
+
+begin
+
+ -- Assign local signals from ports
+ read_enable <= RD;
+ write_enable <= WE;
+
+ -- Memory array
+ WritePort : process (WrClk)
+ begin
+ if (WrClk'event and WrClk = '1') then
+ if (write_allow = '1') then
+ ram_mem(To_integer(unsigned(write_addr))) <= DataIn;
+ end if;
+ end if;
+ end process WritePort;
+
+ ReadPort : process (RdClk)
+ begin
+ if (RdClk'event and RdClk = '1') then
+ DataOut <= ram_mem(To_integer(unsigned(read_addr_next)));
+ end if;
+ end process ReadPort;
+
+ ----------------------------------------------------------------
+ -- Allow flags determine whether FIFO control logic can --
+ -- operate. If read_enable is driven high, and the FIFO is --
+ -- not Empty, then Reads are allowed. Similarly, if the --
+ -- write_enable signal is high, and the FIFO is not Full, --
+ -- then Writes are allowed. --
+ ----------------------------------------------------------------
+
+ read_allow <= (read_enable and not empty);
+ write_allow <= (write_enable and not full_i);
+
+ ---------------------------------------------------------------
+ -- Empty flag is set on Reset (initial), or when gray --
+ -- code counters are equal, or when there is one word in --
+ -- the FIFO, and a Read operation is about to be performed. --
+ ---------------------------------------------------------------
+
+ empty_allow <= (empty or read_enable); -- Is empty or possibly going to be empty
+
+ EmptyFlag : process (RdClk, Reset)
+ begin
+ if (Reset = '1') then
+ empty <= '1';
+ elsif (RdClk'event and RdClk = '1') then
+ if (empty_allow = '1') then
+ empty <= emptyg;
+ end if;
+ end if;
+ end process EmptyFlag;
+
+ Exists <= not empty;
+
+ ---------------------------------------------------------------
+ -- Full flag is set on Reset (initial, but it is cleared --
+ -- on the first valid write_clock edge after Reset is --
+ -- de-asserted), or when Gray-code counters are one away --
+ -- from being equal (the Write Gray-code address is equal --
+ -- to the Last Read Gray-code address), or when the Next --
+ -- Write Gray-code address is equal to the Last Read Gray- --
+ -- code address, and a Write operation is about to be --
+ -- performed. --
+ ---------------------------------------------------------------
+
+ full_allow <= (full_i or write_enable); -- Is full or possibly going to be full
+
+ FullFlag : process (WrClk, Reset)
+ begin
+ if (Reset = '1') then
+ full_i <= '1';
+ elsif (WrClk'event and WrClk = '1') then
+ if (full_allow = '1') then
+ full_i <= fullg;
+ end if;
+ end if;
+ end process FullFlag;
+
+ Full <= full_i;
+
+ ----------------------------------------------------------------
+ -- Generation of Read address pointers. The primary one is --
+ -- binary (read_addr), and the Gray-code derivatives are --
+ -- generated via pipelining the binary-to-Gray-code result. --
+ -- The initial values are important, so they're in sequence. --
+ -- --
+ -- Grey-code addresses are used so that the registered --
+ -- Full and Empty flags are always clean, and never in an --
+ -- unknown state due to the asynchonous relationship of the --
+ -- Read and Write clocks. In the worst case scenario, Full --
+ -- and Empty would simply stay active one cycle longer, but --
+ -- it would not generate an error or give false values. --
+ ----------------------------------------------------------------
+
+ read_addr_next <= std_logic_vector(unsigned(read_addr) + 1) when read_allow = '1' else read_addr;
+
+ ReadAddrCnt : process (RdClk, Reset)
+ begin
+ if (Reset = '1') then
+ read_addr <= (others => '0');
+ elsif (RdClk'event and RdClk = '1') then
+ read_addr <= read_addr_next;
+ end if;
+ end process ReadAddrCnt;
+
+ ReadNextGray : process (RdClk, Reset)
+ begin
+ if (Reset = '1') then
+ read_nextgray(read_nextgray'high-1 downto 0) <= (others => '0');
+ read_nextgray(read_nextgray'high) <= '1';
+ elsif (RdClk'event and RdClk = '1') then
+ if (read_allow = '1') then
+ read_nextgray <= Bin2Gray(read_addr);
+ end if;
+ end if;
+ end process ReadNextGray;
+
+ ReadAddrGray : process (RdClk, Reset)
+ begin
+ if (Reset = '1') then
+ read_addrgray(read_addrgray'high-1 downto 1) <= (others => '0');
+ read_addrgray(0) <= '1';
+ read_addrgray(read_addrgray'high) <= '1';
+ elsif (RdClk'event and RdClk = '1') then
+ if (read_allow = '1') then
+ read_addrgray <= read_nextgray;
+ end if;
+ end if;
+ end process ReadAddrGray;
+
+ ReadLastGrey : process (RdClk, Reset)
+ begin
+ if (Reset = '1') then
+ read_lastgray(read_lastgray'high-1 downto 2) <= (others => '0');
+ read_lastgray(0) <= '1';
+ read_lastgray(1) <= '1';
+ read_lastgray(read_lastgray'high) <= '1';
+ elsif (RdClk'event and RdClk = '1') then
+ if (read_allow = '1') then
+ read_lastgray <= read_addrgray;
+ end if;
+ end if;
+ end process ReadLastGrey;
+
+ ----------------------------------------------------------------
+ -- Generation of Write address pointers. Identical copy of --
+ -- read pointer generation above, except for names. --
+ ----------------------------------------------------------------
+
+ WriteAddrCnt : process (WrClk, Reset)
+ begin
+ if (Reset = '1') then
+ write_addr <= (others => '0');
+ elsif (WrClk'event and WrClk = '1') then
+ if (write_allow = '1') then
+ write_addr <= std_logic_vector(unsigned(write_addr) + 1);
+ end if;
+ end if;
+ end process WriteAddrCnt;
+
+ WriteNextGray : process (WrClk, Reset)
+ begin
+ if (Reset = '1') then
+ write_nextgray(write_nextgray'high-1 downto 0) <= (others => '0');
+ write_nextgray(write_nextgray'high) <= '1';
+ elsif (WrClk'event and WrClk = '1') then
+ if (write_allow = '1') then
+ write_nextgray <= Bin2Gray(write_addr);
+ end if;
+ end if;
+ end process WriteNextGray;
+
+ WriteAddrGray : process (WrClk, Reset)
+ begin
+ if (Reset = '1') then
+ write_addrgray(write_addrgray'high-1 downto 0) <= (others => '0');
+ write_addrgray(0) <= '1';
+ write_addrgray(write_addrgray'high) <= '1';
+ elsif (WrClk'event and WrClk = '1') then
+ if (write_allow = '1') then
+ write_addrgray <= write_nextgray;
+ end if;
+ end if;
+ end process WriteAddrGray;
+
+----------------------------------------------------------------
+-- The two conditions decoded with special carry logic are --
+-- Empty and Full (gated versions). These are used to --
+-- determine the next state of the Full/Empty flags. Carry --
+-- logic is used for optimal speed. (The previous --
+-- implementation of AlmostEmpty and AlmostFull have been --
+-- wrapped into the corresponding carry chains for faster --
+-- performance). --
+-- --
+-- When write_addrgray is equal to read_addrgray, the FIFO --
+-- is Empty, and emptyg (combinatorial) is asserted. Or, --
+-- when write_addrgray is equal to read_nextgray (1 word in --
+-- the FIFO) then the FIFO potentially could be going Empty, --
+-- so emptyg is asserted, and the Empty flip-flop enable is --
+-- gated with empty_allow, which is conditioned with a valid --
+-- read. --
+-- --
+-- Similarly, when read_lastgray is equal to write_addrgray, --
+-- the FIFO is full (511 addresses). Or, when read_lastgray --
+-- is equal to write_nextgray, then the FIFO potentially --
+-- could be going Full, so fullg is asserted, and the Full --
+-- flip-flop enable is gated with full_allow, which is --
+-- conditioned with a valid write. --
+-- --
+-- Note: To have utilized the full address space (512) --
+-- would have required extra logic to determine Full/Empty --
+-- on equal addresses, and this would have slowed down the --
+-- overall performance, which was the top priority. --
+----------------------------------------------------------------
+
+ ECompare : process(write_addrgray, read_addrgray, read_nextgray, empty)
+ begin
+ for I in 0 to Log2(MemSize)-1 loop
+ ecomp(I) <= (not (write_addrgray(I) xor read_addrgray(I)) and empty) or
+ (not (write_addrgray(I) xor read_nextgray(I)) and not empty);
+ end loop;
+ end process ECompare;
+
+ emuxcylow : MUXCY_L port map(DI => '0', CI => '1', S => ecomp(0), LO => emuxcyo(0));
+
+ Gen_emuxcy : for I in 1 to Log2(MemSize)-2 generate
+ begin
+ emuxcy : MUXCY_L port map(DI => '0', CI => emuxcyo(I-1), S => ecomp(I), LO => emuxcyo(I));
+ end generate Gen_emuxcy;
+
+ emuxcyhigh : MUXCY_L port map(DI => '0', CI => emuxcyo(Log2(MemSize)-2), S => ecomp(Log2(MemSize)-1), LO => emptyg);
+
+ FCompare : process(read_lastgray, write_addrgray, write_nextgray, full_i)
+ begin
+ for I in 0 to Log2(MemSize)-1 loop
+ fcomp(I) <= (not (read_lastgray(I) xor write_addrgray(I)) and full_i) or
+ (not (read_lastgray(I) xor write_nextgray(I)) and not full_i);
+ end loop;
+ end process FCompare;
+
+ fmuxcylow : MUXCY_L port map (DI => '0', CI => '1', S => fcomp(0), LO => fmuxcyo(0));
+
+ Gen_fmuxcy : for I in 1 to Log2(MemSize)-2 generate
+ begin
+ fmuxcy : MUXCY_L port map (DI => '0', CI => fmuxcyo(I-1), S => fcomp(I), LO => fmuxcyo(I));
+ end generate Gen_fmuxcy;
+
+ fmuxcyhigh : MUXCY_L port map (DI => '0', CI => fmuxcyo(Log2(MemSize)-2), S => fcomp(Log2(MemSize)-1), LO => fullg);
+
+end architecture IMP;
+
+
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/fsl_v20.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/fsl_v20.vhd
similarity index 96%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/fsl_v20.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/fsl_v20.vhd
index f003b6e0a311702e6040fbdde02bf9c6db608a56..6389753aa48540398d613bd1a80a7ff20f786982 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/fsl_v20.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/fsl_v20.vhd
@@ -1,469 +1,469 @@
--------------------------------------------------------------------------------
--- $Id: fsl_v20.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- fsl_v20.vhd - Entity and architecture
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: fsl_v20.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- fsl_v20.vhdenv\Databases\ip2\processor\hardware\doc\bram_block\bram_block_v1_00_a
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2003-02-13 First Version
--- satish 2004-03-03 New Version
--- rolandp 2006-08-20 BRAM in asynch mode
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-
-library Unisim;
-use Unisim.vcomponents.all;
-
-library compaandesign_com_common_fifo_1;
-use compaandesign_com_common_fifo_1.sync_fifo;
-use compaandesign_com_common_fifo_1.async_fifo;
-
-entity fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer := 1;
- C_ASYNC_CLKS : integer := 0;
- C_IMPL_STYLE : integer := 0;
- C_USE_CONTROL : integer := 1;
- C_FSL_DWIDTH : integer := 32;
- C_FSL_DEPTH : integer := 16;
- C_READ_CLOCK_PERIOD : integer := 0
- );
- port (
- -- Clock and reset signals
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
-
- -- FSL master signals
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
-
- -- FSL slave signals
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
-
- -- FIFO status signals
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-end entity fsl_v20;
-
-architecture IMP of fsl_v20 is
-
- component Sync_FIFO is
- generic (
- C_IMPL_STYLE : Integer;
- WordSize : Integer;
- MemSize : Integer);
- port (
- Reset : in Std_Logic;
- Clk : in Std_Logic;
-
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic);
- end component Sync_FIFO;
-
- component Async_FIFO is
- generic (
- WordSize : Integer;
- MemSize : Integer;
- Protect : Boolean);
- port (
- Reset : in Std_Logic;
- -- Clock region WrClk
- WrClk : in Std_Logic;
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- -- Clock region RdClk
- RdClk : in Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic);
- end component Async_FIFO;
-
- component Async_FIFO_BRAM is
- generic (
- WordSize : Integer;
- MemSize : Integer;
- Protect : Boolean);
- port (
- Reset : in Std_Logic;
- -- Clock region WrClk
- WrClk : in Std_Logic;
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- -- Clock region RdClk
- RdClk : in Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic);
- end component Async_FIFO_BRAM;
-
- signal sys_rst_i : std_logic;
- signal srl_time_out : std_logic;
- signal fsl_rst_i : std_logic;
- signal Data_In : std_logic_vector(0 to C_FSL_DWIDTH);
- signal Data_Out : std_logic_vector(0 to C_FSL_DWIDTH);
-
- signal fifo_full : std_logic;
- -- signal fifo_half_full : std_logic;
- -- signal fifo_half_empty : std_logic;
- signal fifo_has_data : std_logic;
-
- signal fsl_s_control_i : std_logic;
-
- signal srl_clk : std_logic;
-
-begin -- architecture IMP
-
- SYS_RST_PROC : process (SYS_Rst) is
- variable sys_rst_input : std_logic;
- begin
- if C_EXT_RESET_HIGH = 0 then
- sys_rst_i <= not SYS_Rst;
- else
- sys_rst_i <= SYS_Rst;
- end if;
- end process SYS_RST_PROC;
-
- Rst_Delay_Async: if (C_ASYNC_CLKS /= 0) generate
- srl_clk <= FSL_M_Clk;
-
- end generate Rst_Delay_Async;
-
- Rst_Delay_Sync: if (C_ASYNC_CLKS = 0) generate
- srl_clk <= FSL_Clk;
- end generate Rst_Delay_Sync;
-
- POR_SRL_I : SRL16
- generic map (
- INIT => X"FFFF")
- port map (
- D => '0',
- CLK => srl_Clk,
- A0 => '1',
- A1 => '1',
- A2 => '1',
- A3 => '1',
- Q => srl_time_out);
-
- POR_FF_I : FDS
- port map (
- Q => fsl_rst_i,
- D => srl_time_out,
- C => srl_Clk,
- S => sys_rst_i);
-
- FSL_Rst <= fsl_rst_i;
-
-
- -----------------------------------------------------------------------------
- -- Width is 1, so implement a registers
- -----------------------------------------------------------------------------
- Only_Register : if (C_FSL_DEPTH = 1) generate
- signal fsl_s_exists_i : std_logic;
- signal fsl_m_full_i : std_logic;
- begin
-
- -- FSL_S_Clk and FSL_M_Clk are the same
- Sync_Clocks: if (C_ASYNC_CLKS = 0) generate
-
- FIFO : process (FSL_Clk) is
- variable fifo_full : std_logic;
- begin -- process FIFO
- if FSL_Clk'event and FSL_Clk = '1' then -- rising clock edge
- if fsl_rst_i = '1' then -- synchronous reset (active high)
- fifo_full := '0';
- Fsl_m_full_i <= '1';
- Fsl_s_exists_i <= '0';
- else
- if (fifo_full = '0') then -- Empty
- if (FSL_M_Write = '1') then
- fifo_full := '1';
- FSL_S_Data <= FSL_M_Data;
- fsl_s_control_i <= FSL_M_Control;
- end if;
- end if;
- if (fifo_full = '1') then -- Has data
- if (FSL_S_Read = '1') then
- fifo_full := '0';
- end if;
- end if;
- Fsl_m_full_i <= fifo_full;
- Fsl_s_exists_i <= fifo_full;
- end if;
- end if;
- end process FIFO;
- end generate Sync_Clocks;
-
- FSL_S_Exists <= fsl_s_exists_i;
- FSL_Has_Data <= fsl_s_exists_i;
-
- FSL_M_Full <= fsl_m_full_i;
- FSL_Full <= fsl_m_full_i;
-
- FSL_S_Control <= fsl_s_control_i when C_USE_CONTROL /= 0 else '0';
- FSL_Control_IRQ <= fsl_s_control_i and fsl_s_exists_i when C_USE_CONTROL /= 0 else '0';
-
- end generate Only_Register;
-
- Using_FIFO: if (C_FSL_DEPTH > 1) generate
- begin
- -- Map Master Data/Control signal
- Data_In(0 to C_FSL_DWIDTH-1) <= FSL_M_Data;
-
- -- Map Slave Data/Control signal
- FSL_S_Data <= Data_Out(0 to C_FSL_DWIDTH-1);
-
- -- SRL FIFO BASED IMPLEMENTATION
- Sync_FIFO_Gen : if (C_ASYNC_CLKS = 0) generate
- Use_Control: if (C_USE_CONTROL /= 0) generate
-
- Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
- fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
-
- Sync_FIFO_I1 : Sync_FIFO
- generic map (
- C_IMPL_STYLE => C_IMPL_STYLE,
- WordSize => C_FSL_DWIDTH + 1,
- MemSize => C_FSL_DEPTH)
- port map (
- Reset => fsl_rst_i,
- Clk => FSL_Clk,
- WE => FSL_M_Write,
- DataIn => Data_In,
- Full => fifo_full,
- RD => FSL_S_Read,
- DataOut => Data_Out,
- Exists => fifo_has_data);
- end generate Use_Control;
-
- Use_Data: if (C_USE_CONTROL = 0) generate
-
- fsl_s_control_i <= '0';
-
- Sync_FIFO_I1 : Sync_FIFO
- generic map (
- C_IMPL_STYLE => C_IMPL_STYLE,
- WordSize => C_FSL_DWIDTH,
- MemSize => C_FSL_DEPTH)
- port map (
- Reset => fsl_rst_i,
- Clk => FSL_Clk,
- WE => FSL_M_Write,
- DataIn => Data_In(0 to C_FSL_DWIDTH-1),
- Full => fifo_full,
- RD => FSL_S_Read,
- DataOut => Data_Out(0 to C_FSL_DWIDTH-1),
- Exists => fifo_has_data);
-
- end generate Use_Data;
- end generate Sync_FIFO_Gen;
-
- Async_FIFO_Gen: if (C_ASYNC_CLKS /= 0) generate
-
- Use_Control: if (C_USE_CONTROL /= 0) generate
-
- Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
- fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
-
- Use_DPRAM1: if (C_IMPL_STYLE = 0) generate
- -- LUT RAM implementation
- Async_FIFO_I1: Async_FIFO
- generic map (
- WordSize => C_FSL_DWIDTH + 1, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_DPRAM1;
-
- Use_BRAM1: if (C_IMPL_STYLE /= 0) generate
- -- BRAM implementation
- Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
- generic map (
- WordSize => C_FSL_DWIDTH + 1, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_BRAM1;
-
- end generate Use_Control;
-
- Use_Data: if (C_USE_CONTROL = 0) generate
-
- fsl_s_control_i <= '0';
-
- Use_DPRAM0: if (C_IMPL_STYLE = 0) generate
- -- LUT RAM implementation
- Async_FIFO_I1 : Async_FIFO
- generic map (
- WordSize => C_FSL_DWIDTH, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_DPRAM0;
-
- Use_BRAM0: if (C_IMPL_STYLE /= 0) generate
- -- BRAM implementation
- Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
- generic map (
- WordSize => C_FSL_DWIDTH, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_BRAM0;
-
- end generate Use_Data;
-
- end generate Async_FIFO_Gen;
-
- FSL_M_Full <= fifo_full or fsl_rst_i; -- Inhibit writes during reset by
- -- forcing full to '1'
- FSL_S_Exists <= fifo_has_data;
-
- FSL_Full <= fifo_full;
- FSL_Has_Data <= fifo_has_data;
-
- FSL_S_Control <= fsl_s_control_i;
- FSL_Control_IRQ <= fsl_s_control_i and fifo_has_data;
-
- end generate Using_FIFO;
-
-end architecture IMP;
-
+-------------------------------------------------------------------------------
+-- $Id: fsl_v20.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
+-------------------------------------------------------------------------------
+-- fsl_v20.vhd - Entity and architecture
+--
+-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+-------------------------------------------------------------------------------
+-- Filename: fsl_v20.vhd
+--
+-- Description:
+--
+-- VHDL-Standard: VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:
+-- fsl_v20.vhdenv\Databases\ip2\processor\hardware\doc\bram_block\bram_block_v1_00_a
+--
+-------------------------------------------------------------------------------
+-- Author: satish
+-- Revision: $Revision: 1.1.2.1 $
+-- Date: $Date: 2010/10/28 11:17:56 $
+--
+-- History:
+-- satish 2003-02-13 First Version
+-- satish 2004-03-03 New Version
+-- rolandp 2006-08-20 BRAM in asynch mode
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port "*_i"
+-- device pins: "*_pin"
+-- ports: - Names begin with Uppercase
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+library Unisim;
+use Unisim.vcomponents.all;
+
+library compaandesign_com_common_altera_1_lib;
+use compaandesign_com_common_altera_1_lib.all;
+use compaandesign_com_common_altera_1_lib.all;
+
+entity fsl_v20 is
+ generic (
+ C_EXT_RESET_HIGH : integer := 1;
+ C_ASYNC_CLKS : integer := 0;
+ C_IMPL_STYLE : integer := 0;
+ C_USE_CONTROL : integer := 1;
+ C_FSL_DWIDTH : integer := 32;
+ C_FSL_DEPTH : integer := 16;
+ C_READ_CLOCK_PERIOD : integer := 0
+ );
+ port (
+ -- Clock and reset signals
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+
+ -- FSL master signals
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+
+ -- FSL slave signals
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+
+ -- FIFO status signals
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+end entity fsl_v20;
+
+architecture IMP of fsl_v20 is
+
+ component Sync_FIFO is
+ generic (
+ C_IMPL_STYLE : Integer;
+ WordSize : Integer;
+ MemSize : Integer);
+ port (
+ Reset : in Std_Logic;
+ Clk : in Std_Logic;
+
+ WE : in Std_Logic;
+ DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
+ Full : out Std_Logic;
+ RD : in Std_Logic;
+ DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
+ Exists : out Std_Logic);
+ end component Sync_FIFO;
+
+ component Async_FIFO is
+ generic (
+ WordSize : Integer;
+ MemSize : Integer;
+ Protect : Boolean);
+ port (
+ Reset : in Std_Logic;
+ -- Clock region WrClk
+ WrClk : in Std_Logic;
+ WE : in Std_Logic;
+ DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
+ Full : out Std_Logic;
+ -- Clock region RdClk
+ RdClk : in Std_Logic;
+ RD : in Std_Logic;
+ DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
+ Exists : out Std_Logic);
+ end component Async_FIFO;
+
+ component Async_FIFO_BRAM is
+ generic (
+ WordSize : Integer;
+ MemSize : Integer;
+ Protect : Boolean);
+ port (
+ Reset : in Std_Logic;
+ -- Clock region WrClk
+ WrClk : in Std_Logic;
+ WE : in Std_Logic;
+ DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
+ Full : out Std_Logic;
+ -- Clock region RdClk
+ RdClk : in Std_Logic;
+ RD : in Std_Logic;
+ DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
+ Exists : out Std_Logic);
+ end component Async_FIFO_BRAM;
+
+ signal sys_rst_i : std_logic;
+ signal srl_time_out : std_logic;
+ signal fsl_rst_i : std_logic;
+ signal Data_In : std_logic_vector(0 to C_FSL_DWIDTH);
+ signal Data_Out : std_logic_vector(0 to C_FSL_DWIDTH);
+
+ signal fifo_full : std_logic;
+ -- signal fifo_half_full : std_logic;
+ -- signal fifo_half_empty : std_logic;
+ signal fifo_has_data : std_logic;
+
+ signal fsl_s_control_i : std_logic;
+
+ signal srl_clk : std_logic;
+
+begin -- architecture IMP
+
+ SYS_RST_PROC : process (SYS_Rst) is
+ variable sys_rst_input : std_logic;
+ begin
+ if C_EXT_RESET_HIGH = 0 then
+ sys_rst_i <= not SYS_Rst;
+ else
+ sys_rst_i <= SYS_Rst;
+ end if;
+ end process SYS_RST_PROC;
+
+ Rst_Delay_Async: if (C_ASYNC_CLKS /= 0) generate
+ srl_clk <= FSL_M_Clk;
+
+ end generate Rst_Delay_Async;
+
+ Rst_Delay_Sync: if (C_ASYNC_CLKS = 0) generate
+ srl_clk <= FSL_Clk;
+ end generate Rst_Delay_Sync;
+
+ POR_SRL_I : SRL16
+ generic map (
+ INIT => X"FFFF")
+ port map (
+ D => '0',
+ CLK => srl_Clk,
+ A0 => '1',
+ A1 => '1',
+ A2 => '1',
+ A3 => '1',
+ Q => srl_time_out);
+
+ POR_FF_I : FDS
+ port map (
+ Q => fsl_rst_i,
+ D => srl_time_out,
+ C => srl_Clk,
+ S => sys_rst_i);
+
+ FSL_Rst <= fsl_rst_i;
+
+
+ -----------------------------------------------------------------------------
+ -- Width is 1, so implement a registers
+ -----------------------------------------------------------------------------
+ Only_Register : if (C_FSL_DEPTH = 1) generate
+ signal fsl_s_exists_i : std_logic;
+ signal fsl_m_full_i : std_logic;
+ begin
+
+ -- FSL_S_Clk and FSL_M_Clk are the same
+ Sync_Clocks: if (C_ASYNC_CLKS = 0) generate
+
+ FIFO : process (FSL_Clk) is
+ variable fifo_full : std_logic;
+ begin -- process FIFO
+ if FSL_Clk'event and FSL_Clk = '1' then -- rising clock edge
+ if fsl_rst_i = '1' then -- synchronous reset (active high)
+ fifo_full := '0';
+ Fsl_m_full_i <= '1';
+ Fsl_s_exists_i <= '0';
+ else
+ if (fifo_full = '0') then -- Empty
+ if (FSL_M_Write = '1') then
+ fifo_full := '1';
+ FSL_S_Data <= FSL_M_Data;
+ fsl_s_control_i <= FSL_M_Control;
+ end if;
+ end if;
+ if (fifo_full = '1') then -- Has data
+ if (FSL_S_Read = '1') then
+ fifo_full := '0';
+ end if;
+ end if;
+ Fsl_m_full_i <= fifo_full;
+ Fsl_s_exists_i <= fifo_full;
+ end if;
+ end if;
+ end process FIFO;
+ end generate Sync_Clocks;
+
+ FSL_S_Exists <= fsl_s_exists_i;
+ FSL_Has_Data <= fsl_s_exists_i;
+
+ FSL_M_Full <= fsl_m_full_i;
+ FSL_Full <= fsl_m_full_i;
+
+ FSL_S_Control <= fsl_s_control_i when C_USE_CONTROL /= 0 else '0';
+ FSL_Control_IRQ <= fsl_s_control_i and fsl_s_exists_i when C_USE_CONTROL /= 0 else '0';
+
+ end generate Only_Register;
+
+ Using_FIFO: if (C_FSL_DEPTH > 1) generate
+ begin
+ -- Map Master Data/Control signal
+ Data_In(0 to C_FSL_DWIDTH-1) <= FSL_M_Data;
+
+ -- Map Slave Data/Control signal
+ FSL_S_Data <= Data_Out(0 to C_FSL_DWIDTH-1);
+
+ -- SRL FIFO BASED IMPLEMENTATION
+ Sync_FIFO_Gen : if (C_ASYNC_CLKS = 0) generate
+ Use_Control: if (C_USE_CONTROL /= 0) generate
+
+ Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
+ fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
+
+ Sync_FIFO_I1 : Sync_FIFO
+ generic map (
+ C_IMPL_STYLE => C_IMPL_STYLE,
+ WordSize => C_FSL_DWIDTH + 1,
+ MemSize => C_FSL_DEPTH)
+ port map (
+ Reset => fsl_rst_i,
+ Clk => FSL_Clk,
+ WE => FSL_M_Write,
+ DataIn => Data_In,
+ Full => fifo_full,
+ RD => FSL_S_Read,
+ DataOut => Data_Out,
+ Exists => fifo_has_data);
+ end generate Use_Control;
+
+ Use_Data: if (C_USE_CONTROL = 0) generate
+
+ fsl_s_control_i <= '0';
+
+ Sync_FIFO_I1 : Sync_FIFO
+ generic map (
+ C_IMPL_STYLE => C_IMPL_STYLE,
+ WordSize => C_FSL_DWIDTH,
+ MemSize => C_FSL_DEPTH)
+ port map (
+ Reset => fsl_rst_i,
+ Clk => FSL_Clk,
+ WE => FSL_M_Write,
+ DataIn => Data_In(0 to C_FSL_DWIDTH-1),
+ Full => fifo_full,
+ RD => FSL_S_Read,
+ DataOut => Data_Out(0 to C_FSL_DWIDTH-1),
+ Exists => fifo_has_data);
+
+ end generate Use_Data;
+ end generate Sync_FIFO_Gen;
+
+ Async_FIFO_Gen: if (C_ASYNC_CLKS /= 0) generate
+
+ Use_Control: if (C_USE_CONTROL /= 0) generate
+
+ Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
+ fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
+
+ Use_DPRAM1: if (C_IMPL_STYLE = 0) generate
+ -- LUT RAM implementation
+ Async_FIFO_I1: Async_FIFO
+ generic map (
+ WordSize => C_FSL_DWIDTH + 1, -- [Integer]
+ MemSize => C_FSL_DEPTH, -- [Integer]
+ Protect => true) -- [Boolean]
+ port map (
+ Reset => fsl_rst_i, -- [in Std_Logic]
+ -- Clock region WrClk
+ WrClk => FSL_M_Clk, -- [in Std_Logic]
+ WE => FSL_M_Write, -- [in Std_Logic]
+ DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
+ Full => fifo_full, -- [out Std_Logic]
+ -- Clock region RdClk
+ RdClk => FSL_S_Clk, -- [in Std_Logic]
+ RD => FSL_S_Read, -- [in Std_Logic]
+ DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
+ Exists => fifo_has_data); -- [out Std_Logic]
+ end generate Use_DPRAM1;
+
+ Use_BRAM1: if (C_IMPL_STYLE /= 0) generate
+ -- BRAM implementation
+ Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
+ generic map (
+ WordSize => C_FSL_DWIDTH + 1, -- [Integer]
+ MemSize => C_FSL_DEPTH, -- [Integer]
+ Protect => true) -- [Boolean]
+ port map (
+ Reset => fsl_rst_i, -- [in Std_Logic]
+ -- Clock region WrClk
+ WrClk => FSL_M_Clk, -- [in Std_Logic]
+ WE => FSL_M_Write, -- [in Std_Logic]
+ DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
+ Full => fifo_full, -- [out Std_Logic]
+ -- Clock region RdClk
+ RdClk => FSL_S_Clk, -- [in Std_Logic]
+ RD => FSL_S_Read, -- [in Std_Logic]
+ DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
+ Exists => fifo_has_data); -- [out Std_Logic]
+ end generate Use_BRAM1;
+
+ end generate Use_Control;
+
+ Use_Data: if (C_USE_CONTROL = 0) generate
+
+ fsl_s_control_i <= '0';
+
+ Use_DPRAM0: if (C_IMPL_STYLE = 0) generate
+ -- LUT RAM implementation
+ Async_FIFO_I1 : Async_FIFO
+ generic map (
+ WordSize => C_FSL_DWIDTH, -- [Integer]
+ MemSize => C_FSL_DEPTH, -- [Integer]
+ Protect => true) -- [Boolean]
+ port map (
+ Reset => fsl_rst_i, -- [in Std_Logic]
+ -- Clock region WrClk
+ WrClk => FSL_M_Clk, -- [in Std_Logic]
+ WE => FSL_M_Write, -- [in Std_Logic]
+ DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
+ Full => fifo_full, -- [out Std_Logic]
+ -- Clock region RdClk
+ RdClk => FSL_S_Clk, -- [in Std_Logic]
+ RD => FSL_S_Read, -- [in Std_Logic]
+ DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
+ Exists => fifo_has_data); -- [out Std_Logic]
+ end generate Use_DPRAM0;
+
+ Use_BRAM0: if (C_IMPL_STYLE /= 0) generate
+ -- BRAM implementation
+ Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
+ generic map (
+ WordSize => C_FSL_DWIDTH, -- [Integer]
+ MemSize => C_FSL_DEPTH, -- [Integer]
+ Protect => true) -- [Boolean]
+ port map (
+ Reset => fsl_rst_i, -- [in Std_Logic]
+ -- Clock region WrClk
+ WrClk => FSL_M_Clk, -- [in Std_Logic]
+ WE => FSL_M_Write, -- [in Std_Logic]
+ DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
+ Full => fifo_full, -- [out Std_Logic]
+ -- Clock region RdClk
+ RdClk => FSL_S_Clk, -- [in Std_Logic]
+ RD => FSL_S_Read, -- [in Std_Logic]
+ DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
+ Exists => fifo_has_data); -- [out Std_Logic]
+ end generate Use_BRAM0;
+
+ end generate Use_Data;
+
+ end generate Async_FIFO_Gen;
+
+ FSL_M_Full <= fifo_full or fsl_rst_i; -- Inhibit writes during reset by
+ -- forcing full to '1'
+ FSL_S_Exists <= fifo_has_data;
+
+ FSL_Full <= fifo_full;
+ FSL_Has_Data <= fifo_has_data;
+
+ FSL_S_Control <= fsl_s_control_i;
+ FSL_Control_IRQ <= fsl_s_control_i and fifo_has_data;
+
+ end generate Using_FIFO;
+
+end architecture IMP;
+
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/gen_srlfifo.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/gen_srlfifo.vhd
similarity index 97%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/gen_srlfifo.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/gen_srlfifo.vhd
index 529f49e665de6b94a7fc034f25f710763a976576..2176259d1b8ea187e382749b990716e48490f819 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/gen_srlfifo.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/gen_srlfifo.vhd
@@ -1,220 +1,220 @@
--------------------------------------------------------------------------------
--- $Id: gen_srlfifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- srl_fifo.vhd - Entity and architecture
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: srl_fifo.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- srl_fifo.vhd
---
--------------------------------------------------------------------------------
--- Author: goran
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- goran 2003-02-13 First Version
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity SRL_FIFO is
- generic (
- C_DATA_BITS : integer := 8;
- C_DEPTH : integer := 16
- );
- port (
- Clk : in std_logic;
- Reset : in std_logic;
- FIFO_Write : in std_logic;
- Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Read : in std_logic;
- Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Full : out std_logic;
- -- FIFO_Half_Full : out std_logic;
- -- FIFO_Half_Empty : out std_logic;
- Data_Exists : out std_logic
- );
-
-end entity SRL_FIFO;
-
-library UNISIM;
-use UNISIM.VCOMPONENTS.all;
-
-architecture IMP of SRL_FIFO is
-
- signal Addr : std_logic_vector(0 to 3);
- signal buffer_Full : std_logic;
- signal buffer_Empty : std_logic;
-
- signal next_Data_Exists : std_logic;
- signal data_Exists_I : std_logic;
-
- signal valid_Write : std_logic;
-
- signal hsum_A : std_logic_vector(0 to 3);
- signal sum_A : std_logic_vector(0 to 3);
- signal addr_cy : std_logic_vector(0 to 3);
-
- signal buffer_full_early : std_logic;
-
-begin -- architecture IMP
-
--- buffer_Full <= '1' when (Addr = "1111") else '0';
-
- buffer_full_early <= '1' when (sum_A = "1111") else '0';
-
- FDRE_I1: FDRE
- port map (
- Q => buffer_Full, -- [out std_logic]
- C => Clk, -- [in std_logic]
- CE => data_Exists_I, -- [in std_logic]
- D => buffer_full_early, -- [in std_logic]
- R => Reset); -- [in std_logic]
-
- FIFO_Full <= buffer_Full;
-
- -- FIFO_Half_Full <= Addr(3);
- -- FIFO_Half_Empty <= not Addr(3);
-
- buffer_Empty <= '1' when (Addr = "0000") else '0';
-
- next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
- (buffer_Empty and FIFO_Write) or
- (data_Exists_I and not FIFO_Read);
-
- Data_Exists_DFF : process (Clk) is
- begin -- process Data_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if Reset = '1' then -- synchronous reset (active high)
- data_Exists_I <= '0';
- else
- data_Exists_I <= next_Data_Exists;
- end if;
- end if;
- end process Data_Exists_DFF;
-
- Data_Exists <= data_Exists_I;
-
- valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
-
- addr_cy(0) <= valid_Write;
-
- Addr_Counters : for I in 0 to 3 generate
-
- hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-
- -- Don't need the last muxcy, addr_cy(4) is not used anywhere
- Used_MuxCY: if I < 3 generate
- MUXCY_L_I : MUXCY_L
- port map (
- DI => addr(I), -- [in std_logic]
- CI => addr_cy(I), -- [in std_logic]
- S => hsum_A(I), -- [in std_logic]
- LO => addr_cy(I+1)); -- [out std_logic]
- end generate Used_MuxCY;
-
- XORCY_I : XORCY
- port map (
- LI => hsum_A(I), -- [in std_logic]
- CI => addr_cy(I), -- [in std_logic]
- O => sum_A(I)); -- [out std_logic]
-
- FDRE_I : FDRE
- port map (
- Q => addr(I), -- [out std_logic]
- C => Clk, -- [in std_logic]
- CE => data_Exists_I, -- [in std_logic]
- D => sum_A(I), -- [in std_logic]
- R => Reset); -- [in std_logic]
-
- end generate Addr_Counters;
-
- FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
- SRL16E_I : SRL16E
- generic map (
- INIT => x"0000")
- port map (
- CE => valid_Write, -- [in std_logic]
- D => Data_In(I), -- [in std_logic]
- Clk => Clk, -- [in std_logic]
- A0 => Addr(0), -- [in std_logic]
- A1 => Addr(1), -- [in std_logic]
- A2 => Addr(2), -- [in std_logic]
- A3 => Addr(3), -- [in std_logic]
- Q => Data_Out(I)); -- [out std_logic]
- end generate FIFO_RAM;
-
-end architecture IMP;
-
+-------------------------------------------------------------------------------
+-- $Id: gen_srlfifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
+-------------------------------------------------------------------------------
+-- srl_fifo.vhd - Entity and architecture
+--
+-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+-------------------------------------------------------------------------------
+-- Filename: srl_fifo.vhd
+--
+-- Description:
+--
+-- VHDL-Standard: VHDL'93
+-------------------------------------------------------------------------------
+-- Structure:
+-- srl_fifo.vhd
+--
+-------------------------------------------------------------------------------
+-- Author: goran
+-- Revision: $Revision: 1.1.2.1 $
+-- Date: $Date: 2010/10/28 11:17:56 $
+--
+-- History:
+-- goran 2003-02-13 First Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port "*_i"
+-- device pins: "*_pin"
+-- ports: - Names begin with Uppercase
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity SRL_FIFO is
+ generic (
+ C_DATA_BITS : integer := 8;
+ C_DEPTH : integer := 16
+ );
+ port (
+ Clk : in std_logic;
+ Reset : in std_logic;
+ FIFO_Write : in std_logic;
+ Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
+ FIFO_Read : in std_logic;
+ Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
+ FIFO_Full : out std_logic;
+ -- FIFO_Half_Full : out std_logic;
+ -- FIFO_Half_Empty : out std_logic;
+ Data_Exists : out std_logic
+ );
+
+end entity SRL_FIFO;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+
+architecture IMP of SRL_FIFO is
+
+ signal Addr : std_logic_vector(0 to 3);
+ signal buffer_Full : std_logic;
+ signal buffer_Empty : std_logic;
+
+ signal next_Data_Exists : std_logic;
+ signal data_Exists_I : std_logic;
+
+ signal valid_Write : std_logic;
+
+ signal hsum_A : std_logic_vector(0 to 3);
+ signal sum_A : std_logic_vector(0 to 3);
+ signal addr_cy : std_logic_vector(0 to 3);
+
+ signal buffer_full_early : std_logic;
+
+begin -- architecture IMP
+
+-- buffer_Full <= '1' when (Addr = "1111") else '0';
+
+ buffer_full_early <= '1' when (sum_A = "1111") else '0';
+
+ FDRE_I1: FDRE
+ port map (
+ Q => buffer_Full, -- [out std_logic]
+ C => Clk, -- [in std_logic]
+ CE => data_Exists_I, -- [in std_logic]
+ D => buffer_full_early, -- [in std_logic]
+ R => Reset); -- [in std_logic]
+
+ FIFO_Full <= buffer_Full;
+
+ -- FIFO_Half_Full <= Addr(3);
+ -- FIFO_Half_Empty <= not Addr(3);
+
+ buffer_Empty <= '1' when (Addr = "0000") else '0';
+
+ next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
+ (buffer_Empty and FIFO_Write) or
+ (data_Exists_I and not FIFO_Read);
+
+ Data_Exists_DFF : process (Clk) is
+ begin -- process Data_Exists_DFF
+ if Clk'event and Clk = '1' then -- rising clock edge
+ if Reset = '1' then -- synchronous reset (active high)
+ data_Exists_I <= '0';
+ else
+ data_Exists_I <= next_Data_Exists;
+ end if;
+ end if;
+ end process Data_Exists_DFF;
+
+ Data_Exists <= data_Exists_I;
+
+ valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
+
+ addr_cy(0) <= valid_Write;
+
+ Addr_Counters : for I in 0 to 3 generate
+
+ hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
+
+ -- Don't need the last muxcy, addr_cy(4) is not used anywhere
+ Used_MuxCY: if I < 3 generate
+ MUXCY_L_I : MUXCY_L
+ port map (
+ DI => addr(I), -- [in std_logic]
+ CI => addr_cy(I), -- [in std_logic]
+ S => hsum_A(I), -- [in std_logic]
+ LO => addr_cy(I+1)); -- [out std_logic]
+ end generate Used_MuxCY;
+
+ XORCY_I : XORCY
+ port map (
+ LI => hsum_A(I), -- [in std_logic]
+ CI => addr_cy(I), -- [in std_logic]
+ O => sum_A(I)); -- [out std_logic]
+
+ FDRE_I : FDRE
+ port map (
+ Q => addr(I), -- [out std_logic]
+ C => Clk, -- [in std_logic]
+ CE => data_Exists_I, -- [in std_logic]
+ D => sum_A(I), -- [in std_logic]
+ R => Reset); -- [in std_logic]
+
+ end generate Addr_Counters;
+
+ FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
+ SRL16E_I : SRL16E
+ generic map (
+ INIT => x"0000")
+ port map (
+ CE => valid_Write, -- [in std_logic]
+ D => Data_In(I), -- [in std_logic]
+ Clk => Clk, -- [in std_logic]
+ A0 => Addr(0), -- [in std_logic]
+ A1 => Addr(1), -- [in std_logic]
+ A2 => Addr(2), -- [in std_logic]
+ A3 => Addr(3), -- [in std_logic]
+ Q => Data_Out(I)); -- [out std_logic]
+ end generate FIFO_RAM;
+
+end architecture IMP;
+
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/gen_sync_bram.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/gen_sync_bram.vhd
similarity index 97%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/gen_sync_bram.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/gen_sync_bram.vhd
index 6b2a0690de0b64ac4dcf6273ff03e77274d96573..a962c754ee3330f63310cd227cd98dde5c672698 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/gen_sync_bram.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/gen_sync_bram.vhd
@@ -1,129 +1,129 @@
--------------------------------------------------------------------------------
--- $Id: gen_sync_bram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- gen_sync_bram.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2004-03-24 New Version
---
--- Description:
--- Code to infer synchronous dual port bram and separate read/write clock dual
--- port bram
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-entity Sync_BRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- -- Write port
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- -- Read port
- dpra_en : in std_logic;
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
-end Sync_BRAM;
-
-architecture syn of Sync_BRAM is
- type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
- -- signal ram_mem : ram_type := (others => (others => '0'));
- signal ram_mem : ram_type;
- signal read_a : std_logic_vector(C_AWIDTH-1 downto 0);
- signal read_dpra : std_logic_vector(C_AWIDTH-1 downto 0);
-begin
- process (clk)
- begin
- if (clk'event and clk = '1') then
- if (we = '1') then
- ram_mem(conv_integer(a)) <= di;
- end if;
- read_a <= a;
- if (dpra_en = '1') then
- read_dpra <= dpra;
- end if;
- end if;
- end process;
- dpo <= ram_mem(conv_integer(read_dpra));
-end syn;
-
-
-
+-------------------------------------------------------------------------------
+-- $Id: gen_sync_bram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
+-------------------------------------------------------------------------------
+-- gen_sync_bram.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+-------------------------------------------------------------------------------
+-- Author: satish
+-- Revision: $Revision: 1.1.2.1 $
+-- Date: $Date: 2010/10/28 11:17:56 $
+--
+-- History:
+-- satish 2004-03-24 New Version
+--
+-- Description:
+-- Code to infer synchronous dual port bram and separate read/write clock dual
+-- port bram
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port "*_i"
+-- device pins: "*_pin"
+-- ports: - Names begin with Uppercase
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+entity Sync_BRAM is
+ generic (
+ C_DWIDTH : integer := 32;
+ C_AWIDTH : integer := 16
+ );
+ port (
+ clk : in std_logic;
+ -- Write port
+ we : in std_logic;
+ a : in std_logic_vector(C_AWIDTH-1 downto 0);
+ di : in std_logic_vector(C_DWIDTH-1 downto 0);
+ -- Read port
+ dpra_en : in std_logic;
+ dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
+ dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
+ );
+end Sync_BRAM;
+
+architecture syn of Sync_BRAM is
+ type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
+ -- signal ram_mem : ram_type := (others => (others => '0'));
+ signal ram_mem : ram_type;
+ signal read_a : std_logic_vector(C_AWIDTH-1 downto 0);
+ signal read_dpra : std_logic_vector(C_AWIDTH-1 downto 0);
+begin
+ process (clk)
+ begin
+ if (clk'event and clk = '1') then
+ if (we = '1') then
+ ram_mem(conv_integer(a)) <= di;
+ end if;
+ read_a <= a;
+ if (dpra_en = '1') then
+ read_dpra <= dpra;
+ end if;
+ end if;
+ end process;
+ dpo <= ram_mem(conv_integer(read_dpra));
+end syn;
+
+
+
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/gen_sync_dpram.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/gen_sync_dpram.vhd
similarity index 97%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/gen_sync_dpram.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/gen_sync_dpram.vhd
index e967febf4a701ebe7417a8de3038e6726fbc7243..7a35506e9d7a79758f3f2b8b0f3dbb3a9672cc3e 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/gen_sync_dpram.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/gen_sync_dpram.vhd
@@ -1,117 +1,117 @@
--------------------------------------------------------------------------------
--- $Id: gen_sync_dpram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- gen_sync_dpram.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2004-03-24 New Version
---
--- Description:
--- Code to infer synchronous dual port lut ram
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity Sync_DPRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
-end Sync_DPRAM;
-
-architecture syn of Sync_DPRAM is
- type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
- -- signal RAM : ram_type := (others => (others => '0'));
- signal RAM : ram_type;
-begin
- process (clk)
- begin
- if (clk'event and clk = '1') then
- if (we = '1') then
- RAM(conv_integer(a)) <= di;
- end if;
- end if;
- end process;
- dpo <= RAM(conv_integer(dpra));
-end syn;
+-------------------------------------------------------------------------------
+-- $Id: gen_sync_dpram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
+-------------------------------------------------------------------------------
+-- gen_sync_dpram.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+-------------------------------------------------------------------------------
+-- Author: satish
+-- Revision: $Revision: 1.1.2.1 $
+-- Date: $Date: 2010/10/28 11:17:56 $
+--
+-- History:
+-- satish 2004-03-24 New Version
+--
+-- Description:
+-- Code to infer synchronous dual port lut ram
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port "*_i"
+-- device pins: "*_pin"
+-- ports: - Names begin with Uppercase
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity Sync_DPRAM is
+ generic (
+ C_DWIDTH : integer := 32;
+ C_AWIDTH : integer := 16
+ );
+ port (
+ clk : in std_logic;
+ we : in std_logic;
+ a : in std_logic_vector(C_AWIDTH-1 downto 0);
+ dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
+ di : in std_logic_vector(C_DWIDTH-1 downto 0);
+ dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
+ );
+end Sync_DPRAM;
+
+architecture syn of Sync_DPRAM is
+ type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
+ -- signal RAM : ram_type := (others => (others => '0'));
+ signal RAM : ram_type;
+begin
+ process (clk)
+ begin
+ if (clk'event and clk = '1') then
+ if (we = '1') then
+ RAM(conv_integer(a)) <= di;
+ end if;
+ end if;
+ end process;
+ dpo <= RAM(conv_integer(dpra));
+end syn;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/sync_fifo.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/sync_fifo.vhd
similarity index 96%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/sync_fifo.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/sync_fifo.vhd
index 6f23d89cd2238314efbe6b58b7751d6534e37976..d6e6204893de84cb9ecef1fce77a734ccf9b59c0 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/fifo/1/sync_fifo.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/src/vhdl/sync_fifo.vhd
@@ -1,397 +1,397 @@
--------------------------------------------------------------------------------
--- $Id: sync_fifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- sync_fifo.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2004-03-24 New Version
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.Std_Logic_1164.all;
-use IEEE.numeric_std.all;
-
-library compaandesign_com_common_fifo_1;
-use compaandesign_com_common_fifo_1.all;
-
-entity Sync_FIFO is
- generic (
- C_IMPL_STYLE : integer := 0;
- WordSize : integer := 8;
- MemSize : integer := 16
- );
- port (
- Reset : in std_logic;
- Clk : in std_logic;
-
- WE : in std_logic;
- DataIn : in std_logic_vector(WordSize-1 downto 0);
- Full : out std_logic;
- RD : in std_logic;
- DataOut : out std_logic_vector(WordSize-1 downto 0);
- Exists : out std_logic
- );
-end Sync_FIFO;
-
-architecture VHDL_RTL of Sync_FIFO is
-
- function log2(x : natural) return integer is
- variable i : integer := 0;
- begin
- -- coverage off
- if x = 0 then return 0;
- -- coverage on
- else
- while 2**i < x loop
- i := i+1;
- end loop;
- return i;
- end if;
- end function log2;
-
- constant AddrWidth : integer := log2(MemSize);
- signal Read_Address : std_logic_vector(0 to AddrWidth-1);
- signal Write_Address : std_logic_vector(0 to AddrWidth-1);
-
- component SRL_FIFO is
- generic (
- C_DATA_BITS : integer;
- C_DEPTH : integer);
- port (
- Clk : in std_logic;
- Reset : in std_logic;
- FIFO_Write : in std_logic;
- Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Read : in std_logic;
- Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Full : out std_logic;
- -- FIFO_Half_Full : out std_logic;
- -- FIFO_Half_Empty : out std_logic;
- Data_Exists : out std_logic);
- end component SRL_FIFO;
-
- component Sync_DPRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
- end component;
-
- component Sync_BRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- -- Write port
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- -- Read port
- dpra_en : in std_logic;
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
- end component;
-
- signal read_bram_enable : std_logic;
- signal DataOut_BRAM : std_logic_vector(WordSize-1 downto 0);
-
-
-begin
-
- FSL_Flag_Handle : if ((MemSize > 16) or (C_IMPL_STYLE /= 0)) generate
- signal read_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
- signal write_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
-
- signal full_i : std_logic;
- signal exists_i : std_logic;
- signal read_addr_incr : std_logic;
- signal first_write_on_empty_fifo : std_logic;
- signal last_word : std_logic;
-
- signal fifo_length : natural range 0 to MemSize;
- begin
-
- -- FIFO length handling
- Fifo_Length_Handle : process (Clk)
- begin
- if (Clk'event and Clk = '1') then
- if (Reset = '1') then
- fifo_length <= 0;
- else
- -- write and no read => increment length
- -- don't increment length when FULL
- if (WE = '1' and RD = '0' and full_i = '0') then
- fifo_length <= fifo_length + 1;
- -- read and no write => decrement length
- -- don't decrement length when EMPTY
- elsif (WE = '0' and RD = '1' and exists_i = '1') then
- fifo_length <= fifo_length - 1;
- end if;
- end if;
- end if;
- end process Fifo_Length_Handle;
-
- ---------------------------------------------------------------------------
- -- Need special handling for BRAM based fifo since there is one extra delay
- -- reading out data from it.
- -- We are pipelining the reading by making read_addr be one read ahead and
- -- are holding the data on the BRAM output by enabling/disabling the BRAM
- -- enable signal
- ---------------------------------------------------------------------------
- Rd_Delay_For_Bram : if (C_IMPL_STYLE /= 0) generate
- signal fall_through_data : std_logic_vector(WordSize-1 downto 0);
- signal use_fall_through : std_logic;
- begin
-
- -------------------------------------------------------------------------
- -- Need to detect when writing into an empty FIFO,
- -------------------------------------------------------------------------
- First_Write : process (Clk) is
- begin -- process First_Write
- if Clk'event and Clk = '1' then -- rising clock edge
- if Reset = '1' then -- synchronous reset (active high)
- first_write_on_empty_fifo <= '0';
- else
- first_write_on_empty_fifo <= WE and not exists_i;
- end if;
- end if;
- end process First_Write;
-
- -------------------------------------------------------------------------
- -- Read out BRAM contents on the first word written in an empty FIFO and
- -- all other FIFO read except when the last word is read since the "real"
- -- FIFO is actually empty at this time since the last word is on the
- -- output of the BRAM
- -------------------------------------------------------------------------
- last_word <= '1' when (fifo_length = 1) else '0';
- read_bram_enable <= first_write_on_empty_fifo or (RD and (not last_word or WE));
-
- read_addr_incr <= read_bram_enable;
-
- -------------------------------------------------------------------------
- -- The exists flag is now if the BRAM output has valid data and not the
- -- content of the FIFO
- -------------------------------------------------------------------------
- FIFO_Exists_DFF : process (Clk) is
- begin -- process FIFO_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if Reset = '1' then -- synchronous reset (active high)
- Exists <= '0';
- else
- if (first_write_on_empty_fifo = '1') then
- Exists <= '1';
- elsif ((RD = '1') and (WE = '0') and (last_word = '1')) then
- Exists <= '0';
- end if;
- end if;
- end if;
- end process FIFO_Exists_DFF;
-
- -------------------------------------------------------------------------
- -- Data output with fallthrough
- -------------------------------------------------------------------------
- use_fall_through_DFF : process (Clk) is
- begin -- process FIFO_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if ((RD and (not WE)) = '1') or (Reset = '1') then -- synchronous reset (active high)
- use_fall_through <= '0';
- elsif (RD and not last_word) = '1' then
- use_fall_through <= '0';
- elsif (RD = '1') then
--- The equation (RD and WE and last_word) = '1' can be reduced to (RD = '1')
- use_fall_through <= '1';
- end if;
- end if;
- end process use_fall_through_DFF;
-
- fall_through_data_DFF : process (Clk) is
- begin -- process FIFO_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if (RD and WE and last_word) = '1' then
- fall_through_data <= DataIn;
- end if;
- end if;
- end process fall_through_data_DFF;
-
- DataOut <= fall_through_data when (use_fall_through = '1') else DataOut_BRAM;
-
- end generate Rd_Delay_For_Bram;
-
- Rd_No_Delay : if (C_IMPL_STYLE = 0) generate
- read_addr_incr <= RD;
- Exists <= exists_i;
- end generate Rd_No_Delay;
-
- -- Set Full and empty flags
- full_i <= '1' when (fifo_length = MemSize) else '0';
- exists_i <= '1' when (fifo_length /= 0) else '0';
-
- Full <= full_i;
-
- -- Increment Read Address Pointer
- Read_Addr_Handle : process (Clk)
- begin
- if (Clk'event and Clk = '1') then
- if (Reset = '1') then
- read_addr_ptr <= 0;
- elsif (read_addr_incr = '1') then
- read_addr_ptr <= (read_addr_ptr + 1) mod (2 ** AddrWidth);
- end if;
- end if;
- end process Read_Addr_Handle;
-
- -- Increment Write Address Pointer
- Write_Addr_Handle : process (Clk)
- begin
- if (Clk'event and Clk = '1') then
- if (Reset = '1') then
- write_addr_ptr <= 0;
- elsif (WE = '1') then
- write_addr_ptr <= (write_addr_ptr + 1) mod (2 ** AddrWidth);
- end if;
- end if;
- end process Write_Addr_Handle;
-
- Write_Address <= std_logic_vector(to_unsigned(write_addr_ptr, AddrWidth));
- Read_Address <= std_logic_vector(to_unsigned(read_addr_ptr, AddrWidth));
-
- end generate FSL_Flag_Handle;
-
-
- Sync_FIFO_I : if (C_IMPL_STYLE = 0) generate
- srl_fifo_i : if (MemSize <= 16) generate
- FSL_FIFO : SRL_FIFO
- generic map (
- C_DATA_BITS => WordSize,
- C_DEPTH => MemSize)
- port map (
- Clk => Clk,
- Reset => Reset,
- FIFO_Write => WE, -- Master Write Signal
- Data_In => DataIn, -- Master Data
- FIFO_Read => RD, -- Slave Read Signal
- Data_Out => DataOut, -- Slave Data
- FIFO_Full => Full, -- FIFO full signal
- -- FIFO_Half_Full => open,
- -- FIFO_Half_Empty => open,
- Data_Exists => Exists); -- Slave Data exists
- end generate srl_fifo_i;
-
- dpram_fifo_i : if (MemSize > 16) generate
- DPRAM_FIFO : SYNC_DPRAM
- generic map (
- C_DWIDTH => WordSize,
- C_AWIDTH => AddrWidth)
- port map (
- clk => Clk,
- we => WE,
- a => Write_Address,
- dpra => Read_Address,
- di => DataIn,
- dpo => DataOut);
- end generate dpram_fifo_i;
-
- end generate Sync_FIFO_I;
-
- Sync_BRAM_FIFO : if (C_IMPL_STYLE /= 0) generate
- Sync_BRAM_I1 : Sync_BRAM
- generic map (
- C_DWIDTH => WordSize, -- [integer]
- C_AWIDTH => AddrWidth) -- [integer]
- port map (
- clk => Clk, -- [in std_logic]
-
- -- Write port
- we => WE, -- [in std_logic]
- a => Write_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
- di => DataIn, -- [in std_logic_vector(C_DWIDTH-1 downto 0)]
-
- -- Read port
- dpra_en => read_bram_enable, -- [in std_logic]
- dpra => Read_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
- dpo => DataOut_BRAM); -- [out std_logic_vector(C_DWIDTH-1 downto 0)]
- end generate Sync_BRAM_FIFO;
-
-end VHDL_RTL;
-
+-------------------------------------------------------------------------------
+-- $Id: sync_fifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
+-------------------------------------------------------------------------------
+-- sync_fifo.vhd - Entity and architecture
+-------------------------------------------------------------------------------
+--
+-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES
+--
+-------------------------------------------------------------------------------
+-- Author: satish
+-- Revision: $Revision: 1.1.2.1 $
+-- Date: $Date: 2010/10/28 11:17:56 $
+--
+-- History:
+-- satish 2004-03-24 New Version
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port "*_i"
+-- device pins: "*_pin"
+-- ports: - Names begin with Uppercase
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+use IEEE.numeric_std.all;
+
+library compaandesign_com_common_altera_1_lib;
+use compaandesign_com_common_altera_1_lib.all;
+
+entity Sync_FIFO is
+ generic (
+ C_IMPL_STYLE : integer := 0;
+ WordSize : integer := 8;
+ MemSize : integer := 16
+ );
+ port (
+ Reset : in std_logic;
+ Clk : in std_logic;
+
+ WE : in std_logic;
+ DataIn : in std_logic_vector(WordSize-1 downto 0);
+ Full : out std_logic;
+ RD : in std_logic;
+ DataOut : out std_logic_vector(WordSize-1 downto 0);
+ Exists : out std_logic
+ );
+end Sync_FIFO;
+
+architecture VHDL_RTL of Sync_FIFO is
+
+ function log2(x : natural) return integer is
+ variable i : integer := 0;
+ begin
+ -- coverage off
+ if x = 0 then return 0;
+ -- coverage on
+ else
+ while 2**i < x loop
+ i := i+1;
+ end loop;
+ return i;
+ end if;
+ end function log2;
+
+ constant AddrWidth : integer := log2(MemSize);
+ signal Read_Address : std_logic_vector(0 to AddrWidth-1);
+ signal Write_Address : std_logic_vector(0 to AddrWidth-1);
+
+ component SRL_FIFO is
+ generic (
+ C_DATA_BITS : integer;
+ C_DEPTH : integer);
+ port (
+ Clk : in std_logic;
+ Reset : in std_logic;
+ FIFO_Write : in std_logic;
+ Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
+ FIFO_Read : in std_logic;
+ Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
+ FIFO_Full : out std_logic;
+ -- FIFO_Half_Full : out std_logic;
+ -- FIFO_Half_Empty : out std_logic;
+ Data_Exists : out std_logic);
+ end component SRL_FIFO;
+
+ component Sync_DPRAM is
+ generic (
+ C_DWIDTH : integer := 32;
+ C_AWIDTH : integer := 16
+ );
+ port (
+ clk : in std_logic;
+ we : in std_logic;
+ a : in std_logic_vector(C_AWIDTH-1 downto 0);
+ dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
+ di : in std_logic_vector(C_DWIDTH-1 downto 0);
+ dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
+ );
+ end component;
+
+ component Sync_BRAM is
+ generic (
+ C_DWIDTH : integer := 32;
+ C_AWIDTH : integer := 16
+ );
+ port (
+ clk : in std_logic;
+ -- Write port
+ we : in std_logic;
+ a : in std_logic_vector(C_AWIDTH-1 downto 0);
+ di : in std_logic_vector(C_DWIDTH-1 downto 0);
+ -- Read port
+ dpra_en : in std_logic;
+ dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
+ dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
+ );
+ end component;
+
+ signal read_bram_enable : std_logic;
+ signal DataOut_BRAM : std_logic_vector(WordSize-1 downto 0);
+
+
+begin
+
+ FSL_Flag_Handle : if ((MemSize > 16) or (C_IMPL_STYLE /= 0)) generate
+ signal read_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
+ signal write_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
+
+ signal full_i : std_logic;
+ signal exists_i : std_logic;
+ signal read_addr_incr : std_logic;
+ signal first_write_on_empty_fifo : std_logic;
+ signal last_word : std_logic;
+
+ signal fifo_length : natural range 0 to MemSize;
+ begin
+
+ -- FIFO length handling
+ Fifo_Length_Handle : process (Clk)
+ begin
+ if (Clk'event and Clk = '1') then
+ if (Reset = '1') then
+ fifo_length <= 0;
+ else
+ -- write and no read => increment length
+ -- don't increment length when FULL
+ if (WE = '1' and RD = '0' and full_i = '0') then
+ fifo_length <= fifo_length + 1;
+ -- read and no write => decrement length
+ -- don't decrement length when EMPTY
+ elsif (WE = '0' and RD = '1' and exists_i = '1') then
+ fifo_length <= fifo_length - 1;
+ end if;
+ end if;
+ end if;
+ end process Fifo_Length_Handle;
+
+ ---------------------------------------------------------------------------
+ -- Need special handling for BRAM based fifo since there is one extra delay
+ -- reading out data from it.
+ -- We are pipelining the reading by making read_addr be one read ahead and
+ -- are holding the data on the BRAM output by enabling/disabling the BRAM
+ -- enable signal
+ ---------------------------------------------------------------------------
+ Rd_Delay_For_Bram : if (C_IMPL_STYLE /= 0) generate
+ signal fall_through_data : std_logic_vector(WordSize-1 downto 0);
+ signal use_fall_through : std_logic;
+ begin
+
+ -------------------------------------------------------------------------
+ -- Need to detect when writing into an empty FIFO,
+ -------------------------------------------------------------------------
+ First_Write : process (Clk) is
+ begin -- process First_Write
+ if Clk'event and Clk = '1' then -- rising clock edge
+ if Reset = '1' then -- synchronous reset (active high)
+ first_write_on_empty_fifo <= '0';
+ else
+ first_write_on_empty_fifo <= WE and not exists_i;
+ end if;
+ end if;
+ end process First_Write;
+
+ -------------------------------------------------------------------------
+ -- Read out BRAM contents on the first word written in an empty FIFO and
+ -- all other FIFO read except when the last word is read since the "real"
+ -- FIFO is actually empty at this time since the last word is on the
+ -- output of the BRAM
+ -------------------------------------------------------------------------
+ last_word <= '1' when (fifo_length = 1) else '0';
+ read_bram_enable <= first_write_on_empty_fifo or (RD and (not last_word or WE));
+
+ read_addr_incr <= read_bram_enable;
+
+ -------------------------------------------------------------------------
+ -- The exists flag is now if the BRAM output has valid data and not the
+ -- content of the FIFO
+ -------------------------------------------------------------------------
+ FIFO_Exists_DFF : process (Clk) is
+ begin -- process FIFO_Exists_DFF
+ if Clk'event and Clk = '1' then -- rising clock edge
+ if Reset = '1' then -- synchronous reset (active high)
+ Exists <= '0';
+ else
+ if (first_write_on_empty_fifo = '1') then
+ Exists <= '1';
+ elsif ((RD = '1') and (WE = '0') and (last_word = '1')) then
+ Exists <= '0';
+ end if;
+ end if;
+ end if;
+ end process FIFO_Exists_DFF;
+
+ -------------------------------------------------------------------------
+ -- Data output with fallthrough
+ -------------------------------------------------------------------------
+ use_fall_through_DFF : process (Clk) is
+ begin -- process FIFO_Exists_DFF
+ if Clk'event and Clk = '1' then -- rising clock edge
+ if ((RD and (not WE)) = '1') or (Reset = '1') then -- synchronous reset (active high)
+ use_fall_through <= '0';
+ elsif (RD and not last_word) = '1' then
+ use_fall_through <= '0';
+ elsif (RD = '1') then
+-- The equation (RD and WE and last_word) = '1' can be reduced to (RD = '1')
+ use_fall_through <= '1';
+ end if;
+ end if;
+ end process use_fall_through_DFF;
+
+ fall_through_data_DFF : process (Clk) is
+ begin -- process FIFO_Exists_DFF
+ if Clk'event and Clk = '1' then -- rising clock edge
+ if (RD and WE and last_word) = '1' then
+ fall_through_data <= DataIn;
+ end if;
+ end if;
+ end process fall_through_data_DFF;
+
+ DataOut <= fall_through_data when (use_fall_through = '1') else DataOut_BRAM;
+
+ end generate Rd_Delay_For_Bram;
+
+ Rd_No_Delay : if (C_IMPL_STYLE = 0) generate
+ read_addr_incr <= RD;
+ Exists <= exists_i;
+ end generate Rd_No_Delay;
+
+ -- Set Full and empty flags
+ full_i <= '1' when (fifo_length = MemSize) else '0';
+ exists_i <= '1' when (fifo_length /= 0) else '0';
+
+ Full <= full_i;
+
+ -- Increment Read Address Pointer
+ Read_Addr_Handle : process (Clk)
+ begin
+ if (Clk'event and Clk = '1') then
+ if (Reset = '1') then
+ read_addr_ptr <= 0;
+ elsif (read_addr_incr = '1') then
+ read_addr_ptr <= (read_addr_ptr + 1) mod (2 ** AddrWidth);
+ end if;
+ end if;
+ end process Read_Addr_Handle;
+
+ -- Increment Write Address Pointer
+ Write_Addr_Handle : process (Clk)
+ begin
+ if (Clk'event and Clk = '1') then
+ if (Reset = '1') then
+ write_addr_ptr <= 0;
+ elsif (WE = '1') then
+ write_addr_ptr <= (write_addr_ptr + 1) mod (2 ** AddrWidth);
+ end if;
+ end if;
+ end process Write_Addr_Handle;
+
+ Write_Address <= std_logic_vector(to_unsigned(write_addr_ptr, AddrWidth));
+ Read_Address <= std_logic_vector(to_unsigned(read_addr_ptr, AddrWidth));
+
+ end generate FSL_Flag_Handle;
+
+
+ Sync_FIFO_I : if (C_IMPL_STYLE = 0) generate
+ srl_fifo_i : if (MemSize <= 16) generate
+ FSL_FIFO : SRL_FIFO
+ generic map (
+ C_DATA_BITS => WordSize,
+ C_DEPTH => MemSize)
+ port map (
+ Clk => Clk,
+ Reset => Reset,
+ FIFO_Write => WE, -- Master Write Signal
+ Data_In => DataIn, -- Master Data
+ FIFO_Read => RD, -- Slave Read Signal
+ Data_Out => DataOut, -- Slave Data
+ FIFO_Full => Full, -- FIFO full signal
+ -- FIFO_Half_Full => open,
+ -- FIFO_Half_Empty => open,
+ Data_Exists => Exists); -- Slave Data exists
+ end generate srl_fifo_i;
+
+ dpram_fifo_i : if (MemSize > 16) generate
+ DPRAM_FIFO : SYNC_DPRAM
+ generic map (
+ C_DWIDTH => WordSize,
+ C_AWIDTH => AddrWidth)
+ port map (
+ clk => Clk,
+ we => WE,
+ a => Write_Address,
+ dpra => Read_Address,
+ di => DataIn,
+ dpo => DataOut);
+ end generate dpram_fifo_i;
+
+ end generate Sync_FIFO_I;
+
+ Sync_BRAM_FIFO : if (C_IMPL_STYLE /= 0) generate
+ Sync_BRAM_I1 : Sync_BRAM
+ generic map (
+ C_DWIDTH => WordSize, -- [integer]
+ C_AWIDTH => AddrWidth) -- [integer]
+ port map (
+ clk => Clk, -- [in std_logic]
+
+ -- Write port
+ we => WE, -- [in std_logic]
+ a => Write_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
+ di => DataIn, -- [in std_logic_vector(C_DWIDTH-1 downto 0)]
+
+ -- Read port
+ dpra_en => read_bram_enable, -- [in std_logic]
+ dpra => Read_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
+ dpo => DataOut_BRAM); -- [out std_logic_vector(C_DWIDTH-1 downto 0)]
+ end generate Sync_BRAM_FIFO;
+
+end VHDL_RTL;
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a8a07f827b996c97b23beed8e495647f4a33e9f1
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/hdllib.cfg
@@ -0,0 +1,22 @@
+hdl_lib_name = compaandesign_com_common_hwnode_1
+hdl_library_clause_name = compaandesign_com_common_hwnode_1_lib
+hdl_lib_uses_synth = compaandesign_com_common_common_1 compaandesign_com_common_altera_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/controller.vhd
+ src/vhdl/counter.vhd
+ src/vhdl/it_mod.vhd
+ src/vhdl/it_mul.vhd
+ src/vhdl/parameters.vhd
+ src/vhdl/read_mux.vhd
+ src/vhdl/read_mmux.vhd
+ src/vhdl/write_demux.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/controller.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/controller.vhd
similarity index 95%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/controller.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/controller.vhd
index 9c232e661419837d2702374caea8658f59558351..9074fbf3208fea113918480689ef0e87597140ab 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/controller.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/controller.vhd
@@ -41,6 +41,8 @@ entity CONTROLLER is
ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
+
+ EXIST_WR : out std_logic;
CLK : in std_logic;
RST : in std_logic
@@ -104,4 +106,7 @@ architecture RTL of CONTROLLER is
READ <= EXIST and p_en(0);
ENABLE_EX(N_STAGES-1 downto 0) <= pipe(N_STAGES-1 downto 0) and p_en(N_STAGES downto 1);
+ EXIST_WR <= pipe(N_STAGES);
+
end RTL;
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/counter.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/counter.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f2a39e8df64292c851239aabea44ef33e1ebb1b8
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/counter.vhd
@@ -0,0 +1,220 @@
+ -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
+ --
+ -- This file, or parts of it, or modified versions of it, may not be
+ -- copied, reproduced or transmitted in any form, including
+ -- reprinting, translation, photocopying or microfilming, or by any
+ -- means, electronic, mechanical or otherwise, or stored in a
+ -- retrieval system, or used for any purpose, without the prior
+ -- written permission of all Owners unless it is explicitly marked as
+ -- having Classification `Public'.
+ --
+ -- Classification: Restricted.
+ --
+ -- Owners of this file give notice:
+ -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
+ -- All rights, including copyrights, reserved.
+ --
+ -- This file contains or may contain restricted information and is
+ -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
+ -- Notice(s) above do not evidence any actual or intended publication
+ -- of such source code. This file is additionally subject to the
+ -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
+ --
+ -- END OF COPYRIGHT NOTICE
+ --
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity counter is
+ generic(
+ C_STEP : natural := 1;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+end counter;
+
+architecture RTL of counter is
+
+ signal sl_counter : unsigned(C_WIDTH-1 downto 0);
+ signal sl_register : unsigned(C_WIDTH-1 downto 0);
+ signal sl_LOWER_BND : unsigned(C_WIDTH-1 downto 0);
+ signal sl_UPPER_BND : unsigned(C_WIDTH-1 downto 0);
+ signal sl_last_count : std_logic;
+ signal sl_done : std_logic;
+
+begin
+ ITERATOR(C_WIDTH-1 downto 0) <= STD_LOGIC_VECTOR(sl_counter);
+ REG_CNTR(C_WIDTH-1 downto 0) <= STD_LOGIC_VECTOR(sl_register);
+
+ sl_LOWER_BND <= UNSIGNED(LOWER_BND(C_WIDTH-1 downto 0));
+ sl_UPPER_BND <= UNSIGNED(UPPER_BND(C_WIDTH-1 downto 0));
+
+
+ sl_counter <= sl_LOWER_BND when (sl_done='1' or RST='1' ) else (sl_register + C_STEP);
+ --sl_last_count <= '1' when (sl_counter >= sl_UPPER_BND) else '0';
+ sl_last_count <= '1' when (sl_register >= sl_UPPER_BND) else '0';
+ sl_done <= sl_last_count;
+
+ REG_PRCS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST='1' ) then
+ sl_register <= sl_LOWER_BND;
+ --sl_done <= sl_last_count; -- special case: (sl_LOWER_BND == sl_UPPER_BND)
+ elsif( ENABLE='1' ) then
+ sl_register <= sl_counter;
+ --sl_done <= sl_last_count;
+ end if;
+ end if;
+ end process;
+
+
+-- REG_PRCS : process(CLK, RST)
+-- begin
+-- if( RST='1' ) then
+-- sl_register <= sl_LOWER_BND;
+-- sl_done <= sl_last_count; -- special case: (sl_LOWER_BND == sl_UPPER_BND)
+-- elsif rising_edge(CLK) then
+-- if( ENABLE='1' ) then
+-- sl_register <= sl_counter;
+-- sl_done <= sl_last_count;
+-- end if;
+-- end if;
+-- end process;
+ --
+ DONE <= sl_done;
+
+
+end RTL;
+
+--==============================================================================
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity gen_counter is
+ generic (
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ FIRE : in std_logic;
+ ENABLE : in std_logic;
+ LOWER_BND_IN : in std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ UPPER_BND_IN : in std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ ITERATORS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ DONE : out std_logic;
+ STOP : out std_logic
+ );
+end gen_counter;
+
+architecture RTL of gen_counter is
+
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_stop : std_logic;
+
+begin
+
+ GEN_LAB : for i in 0 to N_CNTRS-1 generate
+ CNTR : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_cntr_en(i),
+ LOWER_BND => LOWER_BND_IN(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => UPPER_BND_IN(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => ITERATORS(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => REG_CNTRS(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+
+
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and WRAP=false) then
+ sl_stop <= '1';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+-- DONE_PRCS: process(CLK, RST)
+-- begin
+-- if( RST = '1' ) then
+-- sl_stop <= '0';
+-- sl_done_all <= '0';
+-- elsif rising_edge(clk) then
+-- if (sl_cntr_en(N_CNTRS)='1' and WRAP=false) then
+-- sl_stop <= '1';
+-- end if;
+-- if (sl_stop='0') then
+-- sl_done_all <= sl_cntr_en(N_CNTRS);
+-- end if;
+-- end if;
+-- end process;
+
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+
+ sl_cntr_en(0) <= '0' when (sl_stop='1') else
+ '1' when ((FIRE='0') or (ENABLE='1')) else '0';
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/it_mod.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/it_mod.vhd
similarity index 100%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/it_mod.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/it_mod.vhd
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/it_mul.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/it_mul.vhd
similarity index 100%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/it_mul.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/it_mul.vhd
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/parameters.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/parameters.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a6e9ba6cc0b214f4df1b11bc43a33c486896cfd0
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/parameters.vhd
@@ -0,0 +1,273 @@
+ -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
+ --
+ -- This file, or parts of it, or modified versions of it, may not be
+ -- copied, reproduced or transmitted in any form, including
+ -- reprinting, translation, photocopying or microfilming, or by any
+ -- means, electronic, mechanical or otherwise, or stored in a
+ -- retrieval system, or used for any purpose, without the prior
+ -- written permission of all Owners unless it is explicitly marked as
+ -- having Classification `Public'.
+ --
+ -- Classification: Restricted.
+ --
+ -- Owners of this file give notice:
+ -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
+ -- All rights, including copyrights, reserved.
+ --
+ -- This file contains or may contain restricted information and is
+ -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
+ -- Notice(s) above do not evidence any actual or intended publication
+ -- of such source code. This file is additionally subject to the
+ -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
+ --
+ -- END OF COPYRIGHT NOTICE
+ --
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_altera_1_lib;
+use compaandesign_com_common_altera_1_lib.all;
+
+entity PARAMETERS is
+ generic (
+ PAR_WIDTH : natural;
+ PAR_BITWIDTH : natural;
+ PAR_VECTOR : t_par_vector;
+ CNT_BITWIDTH : natural := 10;
+ N_PAR : natural
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ FIFO_FULL : out std_logic;
+ SOF_RD : in std_logic;
+ SOF_WR : in std_logic;
+ HALT_RD : out std_logic;
+ HALT_WR : out std_logic;
+ SYNC_NUM : out std_logic_vector(9 downto 0);
+ PARAM_DT : in std_logic_vector(CNT_BITWIDTH+PAR_BITWIDTH-1 downto 0);
+ PARAM_LD : in std_logic;
+ PARAMETERS_RD : out std_logic_vector(PAR_BITWIDTH-1 downto 0);
+ PARAMETERS_WR : out std_logic_vector(PAR_BITWIDTH-1 downto 0)
+ );
+end PARAMETERS;
+
+architecture RTL of PARAMETERS is
+
+component fsl_v20 is
+ generic (
+ C_EXT_RESET_HIGH : integer := 1;
+ C_ASYNC_CLKS : integer := 0;
+ C_IMPL_STYLE : integer := 0;
+ C_USE_CONTROL : integer := 1;
+ C_FSL_DWIDTH : integer := 32;
+ C_FSL_DEPTH : integer := 8
+ );
+ port (
+ -- Clock and reset signals
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+
+ -- FSL master signals
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(CNT_BITWIDTH+PAR_WIDTH-1 downto 0);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+
+ -- FSL slave signals
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(CNT_BITWIDTH+PAR_WIDTH-1 downto 0);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+
+ -- FIFO status signals
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic
+ );
+end component fsl_v20;
+
+ signal sl_det_0, sl_det_1, sl_PARAM_LD : std_logic;
+
+ type state_type is (s_idle, s_update_rd, s_update_wr, s_fifo_read);
+ signal state : state_type;
+
+ signal fsl_m_control : std_logic;
+ signal fsl_m_clk : std_logic;
+ signal fsl_write : std_logic;
+ signal fsl_data_write : std_logic_vector(CNT_BITWIDTH+PAR_WIDTH-1 downto 0);
+ signal fsl_m_full : std_logic;
+ signal fsl_read : std_logic;
+ signal fsl_data_read : std_logic_vector(CNT_BITWIDTH+PAR_WIDTH-1 downto 0);
+ signal fsl_s_clk : std_logic;
+ signal fsl_s_control : std_logic;
+ signal fsl_s_exists : std_logic;
+
+ signal sof_cnt : natural;
+ signal sof_cnt_a : natural;
+ signal sof_cnt_b : natural;
+ signal sof_num : std_logic_vector(CNT_BITWIDTH-1 downto 0);
+ signal sof_num_a : std_logic_vector(CNT_BITWIDTH-1 downto 0);
+ signal sof_num_b : std_logic_vector(CNT_BITWIDTH-1 downto 0);
+
+ signal sync_in_num : std_logic_vector(CNT_BITWIDTH-1 downto 0);
+ signal sync_now : std_logic;
+
+begin
+
+ GenLabel1 : if N_PAR > 0 generate
+
+ -- Rising_edge detection of PARAM_LD signal --------------------
+ Edge_det_prcss : process(CLK)
+ begin
+ if falling_edge( CLK ) then
+ sl_det_0 <= PARAM_LD;
+ sl_det_1 <= sl_det_0;
+ end if;
+ end process;
+
+ sl_PARAM_LD <= sl_det_0 and not(sl_det_1);
+
+ -- Update the parameters (from the temp buffer) ----------------
+
+ FIFO_FULL <= fsl_m_full;
+
+ FIFO_WRITE : process(CLK, RST)
+ begin
+ if rising_edge(CLK) then
+ if( RST='1' ) then
+ fsl_data_write <= (others => '0');
+ fsl_write <= '0';
+ else
+ if rising_edge(CLK) then
+ fsl_data_write <= PARAM_DT;
+ if fsl_m_full = '0' and sl_PARAM_LD = '1' then
+ fsl_write <= '1';
+ else
+ fsl_write <= '0';
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ SOF_CNT_Proc : process(CLK,RST,SOF_RD)
+ begin
+ if rising_edge(CLK) then
+ if( RST='1' ) then
+ sof_cnt <= 1;
+ else
+ if(SOF_RD='1') then
+ if sof_cnt < 100 then
+ sof_cnt <= sof_cnt + 1;
+ else
+ sof_cnt <= 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ sof_cnt_a <= sof_cnt + 1 when sof_cnt /= 100 else 1;
+
+ sof_num <= STD_LOGIC_VECTOR(to_signed(sof_cnt,CNT_BITWIDTH));
+ sof_num_a <= STD_LOGIC_VECTOR(to_signed(sof_cnt_a,CNT_BITWIDTH));
+
+ sync_now <= '1' when SOF_RD='1' and sync_in_num=sof_num else '0';
+
+ sync_in_num <= fsl_data_read(CNT_BITWIDTH+PAR_BITWIDTH-1 downto PAR_BITWIDTH);
+
+ SYNC_NUM <= sof_num_a;
+
+ FSM : process(CLK, RST)
+ begin
+ if rising_edge(CLK) then
+ if( RST='1' ) then
+ state <= s_idle;
+ parameters_rd <= STD_LOGIC_VECTOR(to_signed(0,PAR_BITWIDTH));
+ parameters_wr <= STD_LOGIC_VECTOR(to_signed(0,PAR_BITWIDTH));
+ fsl_read <= '0';
+ else
+ case (state) is
+ when s_idle =>
+ if (fsl_s_exists='1') then
+ if(sync_now = '1') then
+ parameters_rd <= fsl_data_read(PAR_BITWIDTH-1 downto 0);
+ state <= s_update_wr;
+ else
+ state <= s_update_rd;
+ end if;
+ end if;
+ when s_update_rd =>
+ if(sync_now = '1') then
+ parameters_rd <= fsl_data_read(PAR_BITWIDTH-1 downto 0);
+ if(SOF_WR = '1') then
+ parameters_wr <= fsl_data_read(PAR_BITWIDTH-1 downto 0);
+ fsl_read <= '1';
+ state <= s_fifo_read;
+ else
+ state <= s_update_wr;
+ end if;
+ end if;
+ when s_update_wr =>
+ if(SOF_WR = '1') then
+ parameters_wr <= fsl_data_read(PAR_BITWIDTH-1 downto 0);
+ fsl_read <= '1';
+ state <= s_fifo_read;
+ end if;
+ when s_fifo_read =>
+ fsl_read <= '0';
+ state <= s_idle;
+ when others => state <= s_idle;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ fsl_m_control <= '0';
+ fsl_m_clk <= '0';
+ fsl_s_clk <= '0';
+ fsl_s_control <= '0';
+
+ fsl_cirular : fsl_v20
+ generic map (
+ C_EXT_RESET_HIGH => 1,
+ C_ASYNC_CLKS =>0,
+ C_USE_CONTROL => 1,
+ C_IMPL_STYLE => 0,
+ C_FSL_DWIDTH => PAR_BITWIDTH + CNT_BITWIDTH,
+ C_FSL_DEPTH => 4
+ )
+ port map (
+ -- Clock and reset signals
+ FSL_Clk => CLK,
+ SYS_Rst => RST,
+ FSL_Rst => open,
+ -- FSL master signals
+ FSL_M_Clk => fsl_m_clk,
+ FSL_M_Data => fsl_data_write,
+ FSL_M_Control => fsl_m_control,
+ FSL_M_Write => fsl_write,
+ FSL_M_Full => fsl_m_full,
+ -- FSL slave signals
+ FSL_S_Clk => fsl_s_clk,
+ FSL_S_Data => fsl_data_read,
+ FSL_S_Control => fsl_s_control,
+ FSL_S_Read => fsl_read,
+ FSL_S_Exists => fsl_s_exists,
+ -- FIFO status signals
+ FSL_Full => open,
+ FSL_Has_Data => open
+ );
+
+ end generate; -- GenLabel1
+
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/read_mmux.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/read_mmux.vhd
similarity index 96%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/read_mmux.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/read_mmux.vhd
index af3df7940e2a4166253d084927eca7d131082f61..2b2c9a62b361f12ac383b9da59e390be27aafcb3 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/read_mmux.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/read_mmux.vhd
@@ -1,285 +1,288 @@
--- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity read_mmux is
- generic(
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32;
- C_IMPL_STYLE : integer := 0;
- C_FSL_DWIDTH : natural := 32;
- C_FSL_DEPTH : natural := 64
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
- CLK : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
-
- RST : in std_logic;
- OBTAIN_OOMX : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE_OOMX : in std_logic_vector(N_PORTS-1 downto 0)
- );
-end read_mmux;
-
-architecture RTL of read_mmux is
-
-signal fsl_m_control : std_logic;
-signal fsl_m_clk : std_logic;
-signal fsl_write : std_logic;
-signal fsl_data_write : std_logic_vector(0 to C_FSL_DWIDTH-1);
-signal fsl_m_full : std_logic;
-signal fsl_read : std_logic;
-signal fsl_data_read : std_logic_vector(0 to C_FSL_DWIDTH-1);
-signal fsl_s_clk : std_logic;
-signal fsl_s_control : std_logic;
-signal fsl_s_exists : std_logic;
-
-signal sl_read : std_logic;
-signal sl_exist : std_logic;
- signal sl_avail : std_logic;
-
-component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer := 1;
- C_ASYNC_CLKS : integer := 0;
- C_IMPL_STYLE : integer := 0;
- C_USE_CONTROL : integer := 1;
- C_FSL_DWIDTH : integer := 32;
- C_FSL_DEPTH : integer := 16
- );
- port (
- -- Clock and reset signals
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
-
- -- FSL master signals
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
-
- -- FSL slave signals
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
-
- -- FIFO status signals
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic
- );
-end component fsl_v20;
-
-
-
-begin
-
- -- REUSE_READ => OBTAIN
- -- REUSE => RELEASE
-
- EXIST <= READ_EN and sl_exist;
- sl_read <= READ_EN and READ;
- READ_ST <= (sl_read and sl_exist) or (sl_avail);
-
- DEMUX_GEN : for i in 0 to N_PORTS-1 generate
- READS(i) <= EXISTS(i) and CONTROL(i) and sl_read and OBTAIN_OOMX(i);
- fsl_read <= not OBTAIN_OOMX(i) and (sl_read );
- fsl_write <= not RELEASE_OOMX(i) and (sl_read );
- end generate;
-
- MUX_PRCSS : process(CONTROL, RELEASE_OOMX, OBTAIN_OOMX, IN_PORTS, fsl_data_read)
- begin
- OUT_PORT <= (others=>'0');
- -- OUT_PORT <= IN_PORTS(PORT_WIDTH-1 downto 0);
-
- -- Extra check giving feedback that sizing FIFO is very tight or too small
- assert fsl_m_full = '0'
- report "Internal FIFO is FULL!!!"
- severity WARNING;
-
- for i in 0 to N_PORTS-1 loop
-
- -- If control is high, we need data
- if( CONTROL(i) = '1' ) then
-
- -- peek (take the token fron the fsl and send it to the output and back to fsl)
- -- obtained is hoog, en release hoog
- -- Should not happen
- if( OBTAIN_OOMX(i) = '1' and RELEASE_OOMX(i) = '1') then
-
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
- --assert false
- -- report "Phase in which OBTAIN and RELEASE are both 1 should never be reached"
- -- severity FAILURE;
-
- sl_avail <= '0';
- -- sl_exist <= EXISTS(i);
-
- --OUT_PORT <= fsl_data_read;
- --fsl_data_write <= fsl_data_read;
- end if;
-
- -- peek last (read from the fifo without rewriting to the fsl)
- -- obtained is hoog, en release laag
- -- Read from external FIFO and store locally.
- if( OBTAIN_OOMX(i) = '1' and RELEASE_OOMX(i) = '0') then
-
- -- read from outside and forward
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
-
- -- and put a copy in the local FIFO
- fsl_data_write <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
-
- sl_avail <= '0';
- -- sl_exist <= EXISTS(i);
-
- --OUT_PORT <= fsl_data_read;
- --fsl_data_write <= fsl_data_read;
- end if;
-
- -- take first (take the first token from te input and store it to the fsl)
- -- obtained is laag, en release hoog
-
- if( OBTAIN_OOMX(i) = '0' and RELEASE_OOMX(i) = '1') then
-
- -- read from the internal FIFO, and let the FIFO run empty
- OUT_PORT <= fsl_data_read;
- sl_avail <= '1';
- -- sl_exist <= '1' ;
-
- end if;
-
- --take (take from the input and wirte to the output)
- -- obtained is laag, en release laag
- if( OBTAIN_OOMX(i) = '0' and RELEASE_OOMX(i) = '0') then
-
- -- steady state...
- -- read from internal FIFO
- OUT_PORT <= fsl_data_read;
-
- -- and put the value back in the FIFO
- fsl_data_write <= fsl_data_read;
-
- sl_avail <= '1';
- -- sl_exist <= '1';
-
- end if;
- end if;
-
- end loop;
- end process;
-
-
- MUX_EXIST : process(EXISTS, OBTAIN_OOMX, CONTROL)
- begin
- -- The default value needs to be '1'. See the node's top-level: sl_exist <= sl_exist_1 and sl_exist_0;
- --EXIST <= '0';
- -- sl_exist <= '0';
- for i in 0 to N_PORTS-1 loop
- if( CONTROL(i) = '1' ) then
- --EXIST <= EXISTS(i);
- sl_exist <= (EXISTS(i) and OBTAIN_OOMX(i)) or (not OBTAIN_OOMX(i));
-
- -- Problem hier is dat EXISTS door FIFO wordt gestuurd. Dus in interne FIFO, moet deze hoog worden, ongeacht wat externe FIFO zegt...
- -- sl_exist <= '1' when ((EXISTS(i)='1' and (REUSE_READ(i) = '1')) or (REUSE_READ(i)='0')) else '0';
-
-
- end if;
- end loop;
- end process;
-
-
- -- Checks
- process(CONTROL)
- variable c : integer;
- begin
- c := 0;
- for i in 0 to CONTROL'Length-1 loop
- if (CONTROL(i)='1') then
- c := c + 1;
- end if;
- end loop;
- assert (c <= 1)
- report "Signal CONTROL contains more than one bit that is set to '1' ! The CONTROL signal must be one-hot encoded. "
- severity ERROR;
- end process;
-
-
- fsl_m_control <= '0';
- fsl_m_clk <= '0';
- fsl_s_clk <= '0';
- fsl_s_control <= '0';
-
- fsl_cirular : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS =>0,
- C_USE_CONTROL => 1,
- C_IMPL_STYLE => C_IMPL_STYLE,
- C_FSL_DWIDTH => C_FSL_DWIDTH,
- C_FSL_DEPTH => C_FSL_DEPTH
- )
- port map (
- -- Clock and reset signals
- FSL_Clk => CLK,
- SYS_Rst => RST,
- FSL_Rst => open,
- -- FSL master signals
- FSL_M_Clk => fsl_m_clk,
- FSL_M_Data => fsl_data_write,
- FSL_M_Control => fsl_m_control,
- FSL_M_Write => fsl_write,
- FSL_M_Full => fsl_m_full,
- -- FSL slave signals
- FSL_S_Clk => fsl_s_clk,
- FSL_S_Data => fsl_data_read,
- FSL_S_Control => fsl_s_control,
- FSL_S_Read => fsl_read,
- FSL_S_Exists => fsl_s_exists,
- -- FIFO status signals
- FSL_Full => open,
- FSL_Has_Data => open
- );
-
-
-end RTL;
+-- COPYRIGHT NOTICE (NOT TO BE REMOVED):
+ --
+ -- This file, or parts of it, or modified versions of it, may not be
+ -- copied, reproduced or transmitted in any form, including
+ -- reprinting, translation, photocopying or microfilming, or by any
+ -- means, electronic, mechanical or otherwise, or stored in a
+ -- retrieval system, or used for any purpose, without the prior
+ -- written permission of all Owners unless it is explicitly marked as
+ -- having Classification `Public'.
+ --
+ -- Classification: Restricted.
+ --
+ -- Owners of this file give notice:
+ -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
+ -- All rights, including copyrights, reserved.
+ --
+ -- This file contains or may contain restricted information and is
+ -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
+ -- Notice(s) above do not evidence any actual or intended publication
+ -- of such source code. This file is additionally subject to the
+ -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
+ --
+ -- END OF COPYRIGHT NOTICE
+ --
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_altera_1_lib;
+use compaandesign_com_common_altera_1_lib.all;
+
+entity read_mmux is
+ generic(
+ N_PORTS : natural := 1;
+ PORT_WIDTH : natural := 32;
+ C_IMPL_STYLE : integer := 0;
+ C_FSL_DWIDTH : natural := 32;
+ C_FSL_DEPTH : natural := 64
+ );
+ port(
+ IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+ EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
+ READS : out std_logic_vector(N_PORTS-1 downto 0);
+ SOFS : in std_logic_vector(N_PORTS-1 downto 0);
+
+ OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
+ EXIST : out std_logic;
+ READ : in std_logic;
+ SOF : in std_logic;
+ CLK : in std_logic;
+
+ READ_EN : in std_logic;
+ READ_ST : out std_logic;
+ RELEASE : in std_logic_vector(N_PORTS-1 downto 0);
+ OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
+
+ RST : in std_logic;
+ OBTAIN_OOMX : in std_logic_vector(N_PORTS-1 downto 0);
+ RELEASE_OOMX : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+end read_mmux;
+
+architecture RTL of read_mmux is
+
+signal fsl_m_control : std_logic;
+signal fsl_m_clk : std_logic;
+signal fsl_write : std_logic;
+signal fsl_data_write : std_logic_vector(0 to C_FSL_DWIDTH-1);
+signal fsl_m_full : std_logic;
+signal fsl_read : std_logic;
+signal fsl_data_read : std_logic_vector(0 to C_FSL_DWIDTH-1);
+signal fsl_s_clk : std_logic;
+signal fsl_s_control : std_logic;
+signal fsl_s_exists : std_logic;
+
+signal sl_read : std_logic;
+signal sl_exist : std_logic;
+ signal sl_avail : std_logic;
+
+component fsl_v20 is
+ generic (
+ C_EXT_RESET_HIGH : integer := 1;
+ C_ASYNC_CLKS : integer := 0;
+ C_IMPL_STYLE : integer := 0;
+ C_USE_CONTROL : integer := 1;
+ C_FSL_DWIDTH : integer := 32;
+ C_FSL_DEPTH : integer := 16
+ );
+ port (
+ -- Clock and reset signals
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+
+ -- FSL master signals
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+
+ -- FSL slave signals
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+
+ -- FIFO status signals
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic
+ );
+end component fsl_v20;
+
+
+
+begin
+
+ -- REUSE_READ => OBTAIN
+ -- REUSE => RELEASE
+
+ EXIST <= READ_EN and sl_exist;
+ sl_read <= READ_EN and READ;
+ READ_ST <= (sl_read and sl_exist) or (sl_avail);
+
+ DEMUX_GEN : for i in 0 to N_PORTS-1 generate
+ READS(i) <= EXISTS(i) and CONTROL(i) and sl_read and OBTAIN_OOMX(i);
+ fsl_read <= not OBTAIN_OOMX(i) and (sl_read );
+ fsl_write <= not RELEASE_OOMX(i) and (sl_read );
+ end generate;
+
+ MUX_PRCSS : process(CONTROL, RELEASE_OOMX, OBTAIN_OOMX, IN_PORTS, fsl_data_read)
+ begin
+ OUT_PORT <= (others=>'0');
+ -- OUT_PORT <= IN_PORTS(PORT_WIDTH-1 downto 0);
+
+ -- Extra check giving feedback that sizing FIFO is very tight or too small
+ assert fsl_m_full = '0'
+ report "Internal FIFO is FULL!!!"
+ severity WARNING;
+
+ for i in 0 to N_PORTS-1 loop
+
+ -- If control is high, we need data
+ if( CONTROL(i) = '1' ) then
+
+ -- peek (take the token fron the fsl and send it to the output and back to fsl)
+ -- obtained is hoog, en release hoog
+ -- Should not happen
+ if( OBTAIN_OOMX(i) = '1' and RELEASE_OOMX(i) = '1') then
+
+ OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
+ --assert false
+ -- report "Phase in which OBTAIN and RELEASE are both 1 should never be reached"
+ -- severity FAILURE;
+
+ sl_avail <= '0';
+ -- sl_exist <= EXISTS(i);
+
+ --OUT_PORT <= fsl_data_read;
+ --fsl_data_write <= fsl_data_read;
+ end if;
+
+ -- peek last (read from the fifo without rewriting to the fsl)
+ -- obtained is hoog, en release laag
+ -- Read from external FIFO and store locally.
+ if( OBTAIN_OOMX(i) = '1' and RELEASE_OOMX(i) = '0') then
+
+ -- read from outside and forward
+ OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
+
+ -- and put a copy in the local FIFO
+ fsl_data_write <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
+
+ sl_avail <= '0';
+ -- sl_exist <= EXISTS(i);
+
+ --OUT_PORT <= fsl_data_read;
+ --fsl_data_write <= fsl_data_read;
+ end if;
+
+ -- take first (take the first token from te input and store it to the fsl)
+ -- obtained is laag, en release hoog
+
+ if( OBTAIN_OOMX(i) = '0' and RELEASE_OOMX(i) = '1') then
+
+ -- read from the internal FIFO, and let the FIFO run empty
+ OUT_PORT <= fsl_data_read;
+ sl_avail <= '1';
+ -- sl_exist <= '1' ;
+
+ end if;
+
+ --take (take from the input and wirte to the output)
+ -- obtained is laag, en release laag
+ if( OBTAIN_OOMX(i) = '0' and RELEASE_OOMX(i) = '0') then
+
+ -- steady state...
+ -- read from internal FIFO
+ OUT_PORT <= fsl_data_read;
+
+ -- and put the value back in the FIFO
+ fsl_data_write <= fsl_data_read;
+
+ sl_avail <= '1';
+ -- sl_exist <= '1';
+
+ end if;
+ end if;
+
+ end loop;
+ end process;
+
+
+ MUX_EXIST : process(EXISTS, OBTAIN_OOMX, CONTROL)
+ begin
+ -- The default value needs to be '1'. See the node's top-level: sl_exist <= sl_exist_1 and sl_exist_0;
+ --EXIST <= '0';
+ -- sl_exist <= '0';
+ for i in 0 to N_PORTS-1 loop
+ if( CONTROL(i) = '1' ) then
+ --EXIST <= EXISTS(i);
+ sl_exist <= (EXISTS(i) and OBTAIN_OOMX(i)) or (not OBTAIN_OOMX(i));
+
+ -- Problem hier is dat EXISTS door FIFO wordt gestuurd. Dus in interne FIFO, moet deze hoog worden, ongeacht wat externe FIFO zegt...
+ -- sl_exist <= '1' when ((EXISTS(i)='1' and (REUSE_READ(i) = '1')) or (REUSE_READ(i)='0')) else '0';
+
+
+ end if;
+ end loop;
+ end process;
+
+
+ -- Checks
+ process(CONTROL)
+ variable c : integer;
+ begin
+ c := 0;
+ for i in 0 to CONTROL'Length-1 loop
+ if (CONTROL(i)='1') then
+ c := c + 1;
+ end if;
+ end loop;
+ assert (c <= 1)
+ report "Signal CONTROL contains more than one bit that is set to '1' ! The CONTROL signal must be one-hot encoded. "
+ severity ERROR;
+ end process;
+
+
+ fsl_m_control <= '0';
+ fsl_m_clk <= '0';
+ fsl_s_clk <= '0';
+ fsl_s_control <= '0';
+
+ fsl_cirular : fsl_v20
+ generic map (
+ C_EXT_RESET_HIGH => 1,
+ C_ASYNC_CLKS =>0,
+ C_USE_CONTROL => 1,
+ C_IMPL_STYLE => C_IMPL_STYLE,
+ C_FSL_DWIDTH => C_FSL_DWIDTH,
+ C_FSL_DEPTH => C_FSL_DEPTH
+ )
+ port map (
+ -- Clock and reset signals
+ FSL_Clk => CLK,
+ SYS_Rst => RST,
+ FSL_Rst => open,
+ -- FSL master signals
+ FSL_M_Clk => fsl_m_clk,
+ FSL_M_Data => fsl_data_write,
+ FSL_M_Control => fsl_m_control,
+ FSL_M_Write => fsl_write,
+ FSL_M_Full => fsl_m_full,
+ -- FSL slave signals
+ FSL_S_Clk => fsl_s_clk,
+ FSL_S_Data => fsl_data_read,
+ FSL_S_Control => fsl_s_control,
+ FSL_S_Read => fsl_read,
+ FSL_S_Exists => fsl_s_exists,
+ -- FIFO status signals
+ FSL_Full => open,
+ FSL_Has_Data => open
+ );
+
+
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/read_mux.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd
similarity index 96%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/read_mux.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd
index 266ea323d4c5706496f5419cfed887b5035a94bc..7862c0361b91429a098675e4fbdb3a473288e9b2 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/read_mux.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd
@@ -1,128 +1,128 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity read_mux is
- generic(
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- --CLK : in std_logic;
-
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
-end read_mux;
-
-architecture RTL of read_mux is
- signal sl_read : std_logic;
- signal sl_exist : std_logic;
- signal TMP : std_logic_vector(PORT_WIDTH-1 downto 0);
-begin
- EXIST <= READ_EN and sl_exist;
- sl_read <= READ_EN and READ;
- READ_ST <= sl_read and sl_exist;
-
- DEMUX_GEN : for i in 0 to N_PORTS-1 generate
- --
- -- READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read and (not SOFS(i) or SOF);
- -- The Reorder work showed problems as a result of SOFS signal. For now switched off until
- -- its use becomes clear again. BK 31mar14
- --
- READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read;
- end generate;
-
- MUX_DATA : process(CONTROL, IN_PORTS, OBTAIN, RELEASE, TMP)
- begin
- OUT_PORT <= IN_PORTS(PORT_WIDTH-1 downto 0);
- for i in 0 to N_PORTS-1 loop
- if( CONTROL(i) = '1') then
-
- if( OBTAIN(i) = '1' and RELEASE(i) = '0') then
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
- TMP <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH); -- keep a copy of the value
- end if ;
-
- if( OBTAIN(i) = '0' and RELEASE(i) = '0') then
- OUT_PORT <= TMP;
- end if ;
-
- if( OBTAIN(i) = '0' and RELEASE(i) = '1') then
- OUT_PORT <= TMP;
- end if ;
-
- if( OBTAIN(i) = '1' and RELEASE(i) = '1') then
- --assert false
- -- report "Phase in which OBTAIN and RELEASE are both 1 should never be reached"
- -- severity WARNING;
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
- end if ;
- end if;
- end loop;
- end process;
-
- MUX_EXIST : process(EXISTS, READ, CONTROL)
- begin
- sl_exist <= '0';
- for i in 0 to N_PORTS-1 loop
- if( CONTROL(i) = '1' ) then
- sl_exist <= EXISTS(i);
- end if;
- end loop;
- end process;
-
-
- -- Checks. For simulation only
- process(CONTROL)
- variable c : integer;
- begin
- c := 0;
- for i in 0 to CONTROL'Length-1 loop
- if (CONTROL(i)='1') then
- c := c + 1;
- end if;
- end loop;
- assert (c <= 1)
- report "Signal CONTROL contains more than one bit that is set to '1' ! The CONTROL signal must be one-hot encoded. "
- severity ERROR;
- end process;
-
-end RTL;
\ No newline at end of file
+ -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
+ --
+ -- This file, or parts of it, or modified versions of it, may not be
+ -- copied, reproduced or transmitted in any form, including
+ -- reprinting, translation, photocopying or microfilming, or by any
+ -- means, electronic, mechanical or otherwise, or stored in a
+ -- retrieval system, or used for any purpose, without the prior
+ -- written permission of all Owners unless it is explicitly marked as
+ -- having Classification `Public'.
+ --
+ -- Classification: Restricted.
+ --
+ -- Owners of this file give notice:
+ -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
+ -- All rights, including copyrights, reserved.
+ --
+ -- This file contains or may contain restricted information and is
+ -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
+ -- Notice(s) above do not evidence any actual or intended publication
+ -- of such source code. This file is additionally subject to the
+ -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
+ --
+ -- END OF COPYRIGHT NOTICE
+ --
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity read_mux is
+ generic(
+ N_PORTS : natural := 1;
+ PORT_WIDTH : natural := 32
+ );
+ port(
+ IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+ EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
+ READS : out std_logic_vector(N_PORTS-1 downto 0);
+ SOFS : in std_logic_vector(N_PORTS-1 downto 0);
+
+ OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
+ EXIST : out std_logic;
+ READ : in std_logic;
+ SOF : in std_logic;
+
+ READ_EN : in std_logic;
+ READ_ST : out std_logic;
+ --CLK : in std_logic;
+
+ RELEASE : in std_logic_vector(N_PORTS-1 downto 0);
+ OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+end read_mux;
+
+architecture RTL of read_mux is
+ signal sl_read : std_logic;
+ signal sl_exist : std_logic;
+ signal TMP : std_logic_vector(PORT_WIDTH-1 downto 0);
+begin
+ EXIST <= READ_EN and sl_exist;
+ sl_read <= READ_EN and READ;
+ READ_ST <= sl_read and sl_exist;
+
+ DEMUX_GEN : for i in 0 to N_PORTS-1 generate
+ --
+ -- READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read and (not SOFS(i) or SOF);
+ -- The Reorder work showed problems as a result of SOFS signal. For now switched off until
+ -- its use becomes clear again. BK 31mar14
+ --
+ READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read;
+ end generate;
+
+ MUX_DATA : process(CONTROL, IN_PORTS, OBTAIN, RELEASE, TMP)
+ begin
+ OUT_PORT <= IN_PORTS(PORT_WIDTH-1 downto 0);
+ for i in 0 to N_PORTS-1 loop
+ if( CONTROL(i) = '1') then
+
+ if( OBTAIN(i) = '1' and RELEASE(i) = '0') then
+ OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
+ TMP <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH); -- keep a copy of the value
+ end if ;
+
+ if( OBTAIN(i) = '0' and RELEASE(i) = '0') then
+ OUT_PORT <= TMP;
+ end if ;
+
+ if( OBTAIN(i) = '0' and RELEASE(i) = '1') then
+ OUT_PORT <= TMP;
+ end if ;
+
+ if( OBTAIN(i) = '1' and RELEASE(i) = '1') then
+ --assert false
+ -- report "Phase in which OBTAIN and RELEASE are both 1 should never be reached"
+ -- severity WARNING;
+ OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
+ end if ;
+ end if;
+ end loop;
+ end process;
+
+ MUX_EXIST : process(EXISTS, READ, CONTROL)
+ begin
+ sl_exist <= '0';
+ for i in 0 to N_PORTS-1 loop
+ if( CONTROL(i) = '1' ) then
+ sl_exist <= EXISTS(i);
+ end if;
+ end loop;
+ end process;
+
+
+ -- Checks. For simulation only
+ process(CONTROL)
+ variable c : integer;
+ begin
+ c := 0;
+ for i in 0 to CONTROL'Length-1 loop
+ if (CONTROL(i)='1') then
+ c := c + 1;
+ end if;
+ end loop;
+ assert (c <= 1)
+ report "Signal CONTROL contains more than one bit that is set to '1' ! The CONTROL signal must be one-hot encoded. "
+ severity ERROR;
+ end process;
+
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/write_demux.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/write_demux.vhd
similarity index 100%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/hwnode/1/write_demux.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/src/vhdl/write_demux.vhd
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/wire_connector/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/wire_connector/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..72183708144acbf3d30442c17e34c79b3325f917
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/wire_connector/hdllib.cfg
@@ -0,0 +1,15 @@
+hdl_lib_name = compaandesign_com_common_wire_connector_1
+hdl_library_clause_name = compaandesign_com_common_wire_connector_1_lib
+hdl_lib_uses_synth =
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/wire_connector.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/wire_connector/1/wire_connector.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/wire_connector/src/vhdl/wire_connector.vhd
similarity index 95%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/common/wire_connector/1/wire_connector.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/common/wire_connector/src/vhdl/wire_connector.vhd
index 7e2ea3d072eb2e0c7d7d65bd85e9ab25d5c499e7..8db9cdd109bbf56f6f1812c0cab099861e0e72d3 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/common/wire_connector/1/wire_connector.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/wire_connector/src/vhdl/wire_connector.vhd
@@ -74,4 +74,4 @@ begin
FSL_S_Control <= FSL_M_Control;
FSL_S_Data <= FSL_M_Data;
-end architecture STRUCTURE;
\ No newline at end of file
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..5c0ba00ff11df137556f02545a380fa58ea8a01f
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/hdllib.cfg
@@ -0,0 +1,20 @@
+hdl_lib_name = compaandesign_com_ipcore2rtl_functions_1
+hdl_library_clause_name = compaandesign_com_ipcore2rtl_functions_1_lib
+hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/compaan_outlinedproc0.vhd
+ src/vhdl/compaan_outlinedproc0_pipeline.vhd
+ src/vhdl/transformer.vhd
+ src/vhdl/transformer_pipeline.vhd
+ src/vhdl/compaan_outlinedproc1.vhd
+ src/vhdl/compaan_outlinedproc1_pipeline.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd
similarity index 90%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd
index 973a47c2f355f0179ff7ab2781688bbac38fad42..8f5e5834fe71fa228cadfcd08d825792358aa648 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd
@@ -1,153 +1,161 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity compaan_outlinedproc0 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end compaan_outlinedproc0;
-
-architecture RTL of compaan_outlinedproc0 is
-
- component compaan_outlinedproc0_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : compaan_outlinedproc0_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_tmp1 => ip_tmp1,
- -- Iterators
- it_i => it_i,
- -- Outputs
- op_tmp0 => op_tmp0,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity compaan_outlinedproc0 is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(31 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Iterators
+ it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(31 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end compaan_outlinedproc0;
+
+architecture RTL of compaan_outlinedproc0 is
+
+ component compaan_outlinedproc0_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(31 downto 0);
+ -- Iterators
+ it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(31 downto 0);
+
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+ end component;
+
+ component CONTROLLER is
+ generic (
+ N_STAGES : natural := 1;
+ BLOCKING : natural := 0
+ );
+ port (
+ READ : out std_logic;
+ EXIST : in std_logic;
+ WRITE : out std_logic;
+ FULL : in std_logic;
+ --
+ ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
+ STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
+ STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
+ --
+ CLK : in std_logic;
+ RST : in std_logic
+ );
+ end component;
+
+ constant c_BLOCKING : natural := 1;
+
+ signal sl_EXIST : std_logic;
+ signal sl_READ : std_logic;
+ signal sl_FULL : std_logic;
+ signal sl_WRITE : std_logic;
+ signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
+ --
+
+ --
+
+ --
+
+begin
+
+ -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+ sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+ -- Functional Evaluation. Only when all signals are high, we can set READF high.
+ READF <= (READF'range =>sl_READ);
+ sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+ WRITEF <= (WRITEF'range=>sl_WRITE);
+
+ PIPELINE : compaan_outlinedproc0_pipeline
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ -- Inputs
+ ip_tmp1 => ip_tmp1,
+ -- Iterators
+ it_i => it_i,
+ -- Outputs
+ op_tmp0 => op_tmp0,
+ --
+ ENi => sl_READ,
+ EN => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ ERROR => ERROR
+ );
+
+ CTRL : CONTROLLER
+ generic map (
+ N_STAGES => c_STAGES,
+ BLOCKING => c_BLOCKING
+ )
+ port map (
+ RST => RST,
+ CLK => CLK,
+ READ => sl_READ,
+ EXIST => sl_EXIST,
+ --
+ ENABLE_EX => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ --
+ WRITE => sl_WRITE,
+ FULL => sl_FULL
+ );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0_pipeline.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd
similarity index 91%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0_pipeline.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd
index e745898193ebc59c4f64217737b5180184e10aea..35f401e2bdfd3a2f1e8e295d6f013f58c4b12c56 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc0_pipeline.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd
@@ -1,89 +1,91 @@
--- File automatically generated by KpnMapper
--- This file defines a template for pipelined function implementation
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-
-entity compaan_outlinedproc0_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end compaan_outlinedproc0_pipeline;
-
-architecture RTL of compaan_outlinedproc0_pipeline is
---
- constant error_int : integer := -1;
- constant reset_int : std_logic_vector(0 downto 0) := b"0";
- -- Input registers
- signal ipr_tmp1 : std_logic_vector(31 downto 0);
-
- -- Iterator registers
- signal itr_i : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- --
-
- --
- -- Your pipeline signals
- --
- -- STAGE_0
- signal s0_tmp1 : std_logic_vector(31 downto 0);
- signal r0_tmp1 : std_logic_vector(31 downto 0);
-
-begin
-
- PIPE_REGS : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_tmp1 <= ip_tmp1;
- -- Iterator Registers
- itr_i <= it_i;
- end if;
- -- Pipeline Depth: 1 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- r0_tmp1 <= s0_tmp1;
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
- --
- -- PIPE_COMB:
- s0_tmp1 <= ipr_tmp1;
- --
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
- ERROR <= '0';
-end RTL;
-
-
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity compaan_outlinedproc0_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(31 downto 0);
+ -- Iterators
+ it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(31 downto 0);
+ --
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+end compaan_outlinedproc0_pipeline;
+
+architecture RTL of compaan_outlinedproc0_pipeline is
+--
+ constant error_int : integer := -1;
+ constant reset_int : std_logic_vector(0 downto 0) := b"0";
+ -- Input registers
+ signal ipr_tmp1 : std_logic_vector(31 downto 0);
+
+ -- Iterator registers
+ signal itr_i : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ --
+
+ --
+ -- Your pipeline signals
+ --
+ -- STAGE_0
+ signal s0_tmp1 : std_logic_vector(31 downto 0);
+ signal r0_tmp1 : std_logic_vector(31 downto 0);
+
+begin
+
+ PIPE_REGS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RST='1') then
+ -- Something to reset?
+ else
+ if( ENi = '1' ) then
+ -- Input Registers
+ ipr_tmp1 <= ip_tmp1;
+ -- Iterator Registers
+ itr_i <= it_i;
+ end if;
+ -- Pipeline Depth: 1 stages
+ -- STAGE_0
+ if( EN(0) = '1' ) then
+ r0_tmp1 <= s0_tmp1;
+ end if;
+ end if;
+ end if;
+ end process; -- PIPE_REGS
+ --
+ -- Output
+ op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
+ --
+ -- PIPE_COMB:
+ s0_tmp1 <= ipr_tmp1;
+ --
+ STALL_FRONT <= (others=>'0');
+ STALL_BACK <= (others=>'0');
+ ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc1.vhd
similarity index 90%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc1.vhd
index 3b230d9701f265ed686f575bc5b5d9b610369e26..52e75a50639efc5b27e2303f104b7108688a1856 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc1.vhd
@@ -1,153 +1,161 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity compaan_outlinedproc1 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end compaan_outlinedproc1;
-
-architecture RTL of compaan_outlinedproc1 is
-
- component compaan_outlinedproc1_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : compaan_outlinedproc1_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_tmp1 => ip_tmp1,
- -- Iterators
- it_x => it_x,
- -- Outputs
- op_tmp0 => op_tmp0,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "compaan_outlinedproc1"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity compaan_outlinedproc1 is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(31 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Iterators
+ it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(31 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end compaan_outlinedproc1;
+
+architecture RTL of compaan_outlinedproc1 is
+
+ component compaan_outlinedproc1_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(31 downto 0);
+ -- Iterators
+ it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(31 downto 0);
+
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+ end component;
+
+ component CONTROLLER is
+ generic (
+ N_STAGES : natural := 1;
+ BLOCKING : natural := 0
+ );
+ port (
+ READ : out std_logic;
+ EXIST : in std_logic;
+ WRITE : out std_logic;
+ FULL : in std_logic;
+ --
+ ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
+ STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
+ STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
+ --
+ CLK : in std_logic;
+ RST : in std_logic
+ );
+ end component;
+
+ constant c_BLOCKING : natural := 1;
+
+ signal sl_EXIST : std_logic;
+ signal sl_READ : std_logic;
+ signal sl_FULL : std_logic;
+ signal sl_WRITE : std_logic;
+ signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
+ --
+
+ --
+
+ --
+
+begin
+
+ -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+ sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+ -- Functional Evaluation. Only when all signals are high, we can set READF high.
+ READF <= (READF'range =>sl_READ);
+ sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+ WRITEF <= (WRITEF'range=>sl_WRITE);
+
+ PIPELINE : compaan_outlinedproc1_pipeline
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ -- Inputs
+ ip_tmp1 => ip_tmp1,
+ -- Iterators
+ it_x => it_x,
+ -- Outputs
+ op_tmp0 => op_tmp0,
+ --
+ ENi => sl_READ,
+ EN => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ ERROR => ERROR
+ );
+
+ CTRL : CONTROLLER
+ generic map (
+ N_STAGES => c_STAGES,
+ BLOCKING => c_BLOCKING
+ )
+ port map (
+ RST => RST,
+ CLK => CLK,
+ READ => sl_READ,
+ EXIST => sl_EXIST,
+ --
+ ENABLE_EX => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ --
+ WRITE => sl_WRITE,
+ FULL => sl_FULL
+ );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1_pipeline.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc1_pipeline.vhd
similarity index 91%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1_pipeline.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc1_pipeline.vhd
index c19d6c81e15fef6b98cb1927fcc33e499c40bce3..7be613d7fdcdcbdadacd81fcf292752be0d660fd 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/compaan_outlinedproc1_pipeline.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc1_pipeline.vhd
@@ -1,89 +1,91 @@
--- File automatically generated by KpnMapper
--- This file defines a template for pipelined function implementation
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-
-entity compaan_outlinedproc1_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end compaan_outlinedproc1_pipeline;
-
-architecture RTL of compaan_outlinedproc1_pipeline is
---
- constant error_int : integer := -1;
- constant reset_int : std_logic_vector(0 downto 0) := b"0";
- -- Input registers
- signal ipr_tmp1 : std_logic_vector(31 downto 0);
-
- -- Iterator registers
- signal itr_x : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- --
-
- --
- -- Your pipeline signals
- --
- -- STAGE_0
- signal s0_tmp1 : std_logic_vector(31 downto 0);
- signal r0_tmp1 : std_logic_vector(31 downto 0);
-
-begin
-
- PIPE_REGS : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_tmp1 <= ip_tmp1;
- -- Iterator Registers
- itr_x <= it_x;
- end if;
- -- Pipeline Depth: 1 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- r0_tmp1 <= s0_tmp1;
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
- --
- -- PIPE_COMB:
- s0_tmp1 <= ipr_tmp1;
- --
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
- ERROR <= '0';
-end RTL;
-
-
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "compaan_outlinedproc1"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity compaan_outlinedproc1_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(31 downto 0);
+ -- Iterators
+ it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(31 downto 0);
+ --
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+end compaan_outlinedproc1_pipeline;
+
+architecture RTL of compaan_outlinedproc1_pipeline is
+--
+ constant error_int : integer := -1;
+ constant reset_int : std_logic_vector(0 downto 0) := b"0";
+ -- Input registers
+ signal ipr_tmp1 : std_logic_vector(31 downto 0);
+
+ -- Iterator registers
+ signal itr_x : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ --
+
+ --
+ -- Your pipeline signals
+ --
+ -- STAGE_0
+ signal s0_tmp1 : std_logic_vector(31 downto 0);
+ signal r0_tmp1 : std_logic_vector(31 downto 0);
+
+begin
+
+ PIPE_REGS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RST='1') then
+ -- Something to reset?
+ else
+ if( ENi = '1' ) then
+ -- Input Registers
+ ipr_tmp1 <= ip_tmp1;
+ -- Iterator Registers
+ itr_x <= it_x;
+ end if;
+ -- Pipeline Depth: 1 stages
+ -- STAGE_0
+ if( EN(0) = '1' ) then
+ r0_tmp1 <= s0_tmp1;
+ end if;
+ end if;
+ end if;
+ end process; -- PIPE_REGS
+ --
+ -- Output
+ op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
+ --
+ -- PIPE_COMB:
+ s0_tmp1 <= ipr_tmp1;
+ --
+ STALL_FRONT <= (others=>'0');
+ STALL_BACK <= (others=>'0');
+ ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/transformer.vhd
similarity index 89%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/transformer.vhd
index 4af2d7f9f1128af703ffc4f43331962f97bc5854..a6759c3233d07504bfbd0cb5f9f069c47a035e6e 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/transformer.vhd
@@ -1,153 +1,161 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity transformer is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end transformer;
-
-architecture RTL of transformer is
-
- component transformer_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : transformer_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_a => ip_a,
- -- Iterators
- it_j => it_j,
- -- Outputs
- op_b => op_b,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "transformer"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity transformer is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_a : in std_logic_vector(31 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Iterators
+ it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_b : out std_logic_vector(31 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end transformer;
+
+architecture RTL of transformer is
+
+ component transformer_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_a : in std_logic_vector(31 downto 0);
+ -- Iterators
+ it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_b : out std_logic_vector(31 downto 0);
+
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+ end component;
+
+ component CONTROLLER is
+ generic (
+ N_STAGES : natural := 1;
+ BLOCKING : natural := 0
+ );
+ port (
+ READ : out std_logic;
+ EXIST : in std_logic;
+ WRITE : out std_logic;
+ FULL : in std_logic;
+ --
+ ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
+ STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
+ STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
+ --
+ CLK : in std_logic;
+ RST : in std_logic
+ );
+ end component;
+
+ constant c_BLOCKING : natural := 1;
+
+ signal sl_EXIST : std_logic;
+ signal sl_READ : std_logic;
+ signal sl_FULL : std_logic;
+ signal sl_WRITE : std_logic;
+ signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
+ signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
+ --
+
+ --
+
+ --
+
+begin
+
+ -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+ sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+ -- Functional Evaluation. Only when all signals are high, we can set READF high.
+ READF <= (READF'range =>sl_READ);
+ sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+ WRITEF <= (WRITEF'range=>sl_WRITE);
+
+ PIPELINE : transformer_pipeline
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ -- Inputs
+ ip_a => ip_a,
+ -- Iterators
+ it_j => it_j,
+ -- Outputs
+ op_b => op_b,
+ --
+ ENi => sl_READ,
+ EN => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ ERROR => ERROR
+ );
+
+ CTRL : CONTROLLER
+ generic map (
+ N_STAGES => c_STAGES,
+ BLOCKING => c_BLOCKING
+ )
+ port map (
+ RST => RST,
+ CLK => CLK,
+ READ => sl_READ,
+ EXIST => sl_EXIST,
+ --
+ ENABLE_EX => sl_EN,
+ STALL_FRONT => sl_STALL_FRONT,
+ STALL_BACK => sl_STALL_BACK,
+ --
+ WRITE => sl_WRITE,
+ FULL => sl_FULL
+ );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer_pipeline.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/transformer_pipeline.vhd
similarity index 89%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer_pipeline.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/transformer_pipeline.vhd
index d2ea3417e89ac5dd07cfa280d927a9a981944d6a..a22293c0cf210f0dc7346ef4adb65ebd4bdd6384 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/functions/1/transformer_pipeline.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/src/vhdl/transformer_pipeline.vhd
@@ -1,88 +1,91 @@
--- File automatically generated by KpnMapper
--- This file defines a template for pipelined function implementation
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity transformer_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end transformer_pipeline;
-
-architecture RTL of transformer_pipeline is
---
- constant error_int : integer := -1;
- constant reset_int : std_logic_vector(0 downto 0) := b"0";
- -- Input registers
- signal ipr_a : std_logic_vector(31 downto 0);
-
- -- Iterator registers
- signal itr_j : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- --
-
- --
- -- Your pipeline signals
- --
- -- STAGE_0
- signal s0_a : std_logic_vector(31 downto 0);
- signal r0_a : std_logic_vector(31 downto 0);
-
-begin
-
- PIPE_REGS : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_a <= ip_a;
- -- Iterator Registers
- itr_j <= it_j;
- end if;
- -- Pipeline Depth: 1 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- r0_a <= s0_a(30 downto 0) & '0';
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_b <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_a), op_b'Length));
- --
- -- PIPE_COMB:
- s0_a <= ipr_a;
- --
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
- ERROR <= '0';
-end RTL;
-
-
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "transformer"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity transformer_pipeline is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_a : in std_logic_vector(31 downto 0);
+ -- Iterators
+ it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ -- Outputs
+ op_b : out std_logic_vector(31 downto 0);
+ --
+ ENi : in std_logic;
+ EN : in std_logic_vector(c_STAGES-1 downto 0);
+ STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
+ STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
+ ERROR : out std_logic
+ );
+end transformer_pipeline;
+
+architecture RTL of transformer_pipeline is
+--
+ constant error_int : integer := -1;
+ constant reset_int : std_logic_vector(0 downto 0) := b"0";
+ -- Input registers
+ signal ipr_a : std_logic_vector(31 downto 0);
+
+ -- Iterator registers
+ signal itr_j : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ --
+
+ --
+ -- Your pipeline signals
+ --
+ -- STAGE_0
+ signal s0_a : std_logic_vector(31 downto 0);
+ signal r0_a : std_logic_vector(31 downto 0);
+
+begin
+
+ PIPE_REGS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RST='1') then
+ -- Something to reset?
+ else
+ if( ENi = '1' ) then
+ -- Input Registers
+ ipr_a <= ip_a;
+ -- Iterator Registers
+ itr_j <= it_j;
+ end if;
+ -- Pipeline Depth: 1 stages
+ -- STAGE_0
+ if( EN(0) = '1' ) then
+ r0_a <= s0_a;
+ end if;
+ end if;
+ end if;
+ end process; -- PIPE_REGS
+ --
+ -- Output
+ op_b <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_a), op_b'Length));
+ --
+ -- PIPE_COMB:
+ s0_a <= ipr_a;
+ --
+ STALL_FRONT <= (others=>'0');
+ STALL_BACK <= (others=>'0');
+ ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..bc7ff43915c03efe0a505df9ed4aa892b63d288b
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_ipcore2rtl_hwn_nd_1_1
+hdl_library_clause_name = compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib
+hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/ipcore2rtl_hwn_nd_1_execution_unit.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_rd.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_wr.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_1.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd.bak b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1.vhd
similarity index 84%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd.bak
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1.vhd
index ab79559f0e6bbb34ee991adcbe100cf7204c5815..9cbf126de9ec7df330ce1936be26c3f8c3f0d329 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd.bak
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1.vhd
@@ -1,456 +1,475 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-
-entity ipcore2RTL_hwn_nd_1 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 16;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- data_in_Rd : out std_logic;
- data_in_Din : in std_logic_vector(31 downto 0);
- data_in_Exist : in std_logic;
- data_in_CLK : out std_logic;
- data_in_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- -- ED_1 : out_0
- ND_1OP_1_Wr : out std_logic;
- ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_Full : in std_logic;
- ND_1OP_1_CLK : out std_logic;
- ND_1OP_1_CTRL : out std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_hwn_nd_1 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 1; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 0; -- number of global parameters
- constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- tmp1
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- tmp0
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(0 downto 0)
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(1*32-1 downto 0); -- tmp1
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- tmp1
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- tmp0
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(0 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- data_in_CLK <= CLK;
- ND_1OP_1_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "tmp1"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 1,
- PORT_WIDTH => 32
- )
- port map (
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(0 downto 0),
- READS => sl_READS(0 downto 0),
- SOFS => sl_CTRLS(0 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(0 downto 0),
- OBTAIN => sl_obtain_rd(0 downto 0),
- RELEASE => sl_release_rd(0 downto 0)
- );
-
- data_in_Rd <= sl_READS(0);
-
- sl_IN_PORTS_0 <= data_in_Din;
-
- sl_EXISTS(0) <= data_in_Exist ;
- sl_CTRLS(0) <= data_in_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "tmp0"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 1
- )
- port map (
- WRITES => sl_WRITES(0 downto 0),
- FULLS => sl_FULLS(0 downto 0),
- CONTROL => sl_lortnoc_wr(0 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- ND_1OP_1_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
- ND_1OP_1_CTRL <= sl_sof_wr ;
- ND_1OP_1_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= ND_1OP_1_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_1
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- PARAMETERS => sl_parameters
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) ) );
-
-end RTL;
+-- HWN Entity File automatically generated by KpnMapper
+-- Top level file for a Hardware Accelerator
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+entity ipcore2rtl_hwn_nd_1 is
+ generic (
+ STIM_DIR : string := "bla";
+ RESET_HIGH : natural := 1;
+ PAR_WIDTH : natural := 16;
+ QUANT : natural := 32;
+ WRAP : boolean := true
+ );
+ port (
+
+ -- Dataflow input interfaces
+ data_in_Rd : out std_logic;
+ data_in_Din : in std_logic_vector(31 downto 0);
+ data_in_Exist : in std_logic;
+ data_in_CLK : out std_logic;
+ data_in_CTRL : in std_logic;
+
+ -- Dataflow output interfaces
+ -- ED_1 : out_0
+ ND_1OP_1_Wr : out std_logic;
+ ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
+ ND_1OP_1_Full : in std_logic;
+ ND_1OP_1_CLK : out std_logic;
+ ND_1OP_1_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(PAR_WIDTH+10-1 downto 0);
+ PARAM_LD : in std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic
+ );
+end ipcore2rtl_hwn_nd_1;
+
+architecture RTL of ipcore2rtl_hwn_nd_1 is
+ --
+ -- ====================================
+ -- = Constants declaration =
+ -- ====================================
+ -- Setting the parameters of the HW Node
+ constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
+ constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
+ constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
+ constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+ constant c_COUNTERS : natural := 1; -- number of iterators
+ -- ===========================================
+ -- = Iterators run from Inner to Outer loop =
+ -- ===========================================
+ constant c_CNTR_QUANT : natural := 13;
+ constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
+ constant c_CNTR_WIDTHS : t_counter_width := ( 0=>13, others=>10 );
+ constant c_STAGES : natural := 1; -- number of pipeline stages or delay
+ constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
+ constant c_WRAP : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
+ constant c_PAR_NUMBER : natural := 0; -- number of global parameters
+ constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
+ constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
+ constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+ (0,0,0,0), (0,0,0,0) -- two dummy elements
+ );
+ --
+ -- ====================================
+ -- = Components declaration =
+ -- ====================================
+ component ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_1 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+ end component;
+
+ component READ_MUX is
+ generic (
+ N_PORTS : natural := 1;
+ PORT_WIDTH : natural := 32
+ );
+ port(
+ IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+ EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
+ READS : out std_logic_vector(N_PORTS-1 downto 0);
+ SOFS : in std_logic_vector(N_PORTS-1 downto 0);
+
+ OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
+ EXIST : out std_logic;
+ READ : in std_logic;
+ SOF : in std_logic;
+
+ READ_EN : in std_logic;
+ READ_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
+ OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
+ RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+ component ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_1 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+ end component;
+
+ component WRITE_DEMUX is
+ generic (
+ N_PORTS : natural := 1
+ );
+ port(
+ WRITES : out std_logic_vector(N_PORTS-1 downto 0);
+ WRITE : in std_logic;
+
+ FULLS : in std_logic_vector(N_PORTS-1 downto 0);
+ FULL : out std_logic;
+
+ WRITE_EN : in std_logic;
+ WRITE_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+ component ipcore2rtl_EXECUTION_UNIT_hwn_nd_1 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ QUANT : natural := 32;
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+ -- Func. Input parameters
+ IN_PORT_0 : in std_logic_vector(31 downto 0); -- tmp1
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Func. Output parameters
+ OUT_PORT_0 : out std_logic_vector(31 downto 0); -- tmp0
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ component PARAMETERS is
+ generic (
+ PAR_WIDTH : natural:=16;
+ PAR_BITWIDTH : natural:=1;
+ PAR_VECTOR : t_par_vector;
+ N_PAR : natural:=0
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ FIFO_FULL : out std_logic;
+ HALT_RD : out std_logic;
+ HALT_WR : out std_logic;
+ SOF_RD : in std_logic;
+ SOF_WR : in std_logic;
+ SYNC_NUM : out std_logic_vector(9 downto 0);
+
+ PARAM_DT : in std_logic_vector(PAR_WIDTH+10-1 downto 0);
+ PARAM_LD : in std_logic;
+
+ PARAMETERS_RD : out std_logic_vector(0 downto 0);
+ PARAMETERS_WR : out std_logic_vector(0 downto 0)
+ );
+ end component;
+
+ --
+ -- ====================================
+ -- = Signals declaration =
+ -- ====================================
+ --
+ -- HW Node Input Ports
+ signal sl_IN_PORTS_0 : std_logic_vector(1*32-1 downto 0); -- tmp1
+ signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ --
+ -- Func. Input parameters
+ signal sl_in_port_0 : std_logic_vector(31 downto 0); -- tmp1
+ signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ --
+ signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+ --
+ -- HW Node Output Ports
+ signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ --
+ -- Func. Output parameters
+ signal sl_out_port_0 : std_logic_vector(31 downto 0); -- tmp0
+ signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ --
+ --
+ signal sl_halt : std_logic;
+ signal sl_halted : std_logic;
+ signal sl_halt_wr : std_logic;
+ signal sl_halt_rd : std_logic;
+ signal sl_param_halt_wr : std_logic;
+ signal sl_param_halt_rd : std_logic;
+ signal sl_done_wr : std_logic;
+ signal sl_done_rd : std_logic;
+ signal sl_stop_wr : std_logic;
+ signal sl_stop_rd : std_logic;
+ signal sl_fire_wr : std_logic;
+ signal sl_fire_rd : std_logic;
+ signal sl_sof_wr : std_logic;
+ signal sl_sof_rd : std_logic;
+ signal sl_error : std_logic;
+
+ --
+ -- Parameter related signals
+ signal sl_parameters_rd : std_logic_vector(0 downto 0);
+ signal sl_parameters_wr : std_logic_vector(0 downto 0);
+ signal sl_param_fifo_full : std_logic;
+ signal sl_sync_num : std_logic_vector(9 downto 0);
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when RESET_HIGH=1 else not RST;
+ data_in_CLK <= CLK;
+ ND_1OP_1_CLK <= CLK;
+
+ --
+ -- ==========================================================
+ -- = HWN Input related modules =
+ -- ==========================================================
+ -- Func. Input param. "tmp1"
+ RD_MUX_0 : READ_MUX
+ generic map (
+ N_PORTS => 1,
+ PORT_WIDTH => 32
+ )
+ port map (
+ IN_PORTS => sl_IN_PORTS_0,
+ EXISTS => sl_EXISTS(0 downto 0),
+ READS => sl_READS(0 downto 0),
+ SOFS => sl_CTRLS(0 downto 0),
+
+ OUT_PORT => sl_in_port_0,
+ EXIST => sl_exist(0),
+ READ => sl_read(0),
+ SOF => sl_sof_rd,
+
+ READ_EN => sl_read_en(0),
+ READ_ST => sl_read_st(0),
+ CONTROL => sl_control_rd(0 downto 0),
+ OBTAIN => sl_obtain_rd(0 downto 0),
+ RELEASE => sl_release_rd(0 downto 0)
+ );
+
+ data_in_Rd <= sl_READS(0);
+
+ sl_IN_PORTS_0 <= data_in_Din;
+
+ sl_EXISTS(0) <= data_in_Exist ;
+ sl_CTRLS(0) <= data_in_CTRL ;
+
+ EVAL_RD : ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_1
+ generic map (
+ N_IN_PORTS => c_IN_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map(
+ RST => sl_RST,
+ CLK => CLK,
+ PARAMETERS => sl_parameters_rd,
+ REG_CNTRS => sl_REG_CNTRS_RD,
+ READ_EN => sl_read_en,
+ READ_ST => sl_read_st,
+ HALT => sl_halt_rd,
+ FIRE => sl_fire_rd,
+ DONE => sl_done_rd,
+ STOP => sl_stop_rd,
+ SOF => sl_sof_rd,
+ CONTROL => sl_control_rd,
+ OBTAIN => sl_obtain_rd,
+ RELEASE => sl_release_rd
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Output related modules =
+ -- ==========================================================
+ --
+ -- Func. Output param. "tmp0"
+ DEMUX_0 : WRITE_DEMUX
+ generic map (
+ N_PORTS => 1
+ )
+ port map (
+ WRITES => sl_WRITES(0 downto 0),
+ FULLS => sl_FULLS(0 downto 0),
+ CONTROL => sl_lortnoc_wr(0 downto 0),
+ WRITE => sl_write(0),
+ FULL => sl_full(0),
+ WRITE_EN => sl_write_en(0),
+ WRITE_ST => sl_write_st(0)
+ );
+ --
+ ND_1OP_1_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
+ ND_1OP_1_CTRL <= sl_sof_wr ;
+ ND_1OP_1_Wr <= sl_WRITES(0);
+ sl_FULLS(0) <= ND_1OP_1_Full;
+ sl_lortnoc_wr(0) <= sl_control_wr(0);
+ --
+ --
+ EVAL_WR : ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_1
+ generic map (
+ N_OUT_PORTS => c_OUT_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ PARAMETERS => sl_parameters_wr,
+ WRITE_EN => sl_write_en,
+ WRITE_ST => sl_write_st,
+ HALT => sl_halt_wr,
+ FIRE => sl_fire_wr,
+ DONE => sl_done_wr,
+ STOP => sl_stop_wr,
+ SOF => sl_sof_wr,
+ CONTROL => sl_control_wr
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Execution Unit =
+ -- ==========================================================
+ EX : ipcore2rtl_EXECUTION_UNIT_hwn_nd_1
+ generic map (
+ N_INPORTS => c_IN_FUNC_VAR,
+ N_OUTPORTS => c_OUT_FUNC_VAR,
+ IP_RESET => c_IP_RESET,
+ QUANT => QUANT,
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => c_COUNTERS,
+ CNTR_QUANT => c_CNTR_QUANT,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- Iterators
+ REG_CNTRS_RD => sl_REG_CNTRS_RD,
+ -- Func. Input parameters
+ IN_PORT_0 => sl_in_port_0,
+ READ => sl_read,
+ EXIST => sl_exist,
+ -- Func. Output parameters
+ OUT_PORT_0 => sl_out_port_0,
+ WRITE => sl_write,
+ FULL => sl_full,
+ --
+ STOP_WR => sl_stop_wr,
+ STOP_RD => sl_stop_rd,
+ ERROR => sl_error
+ );
+
+ PAR_LOAD : PARAMETERS
+ generic map (
+ PAR_WIDTH => PAR_WIDTH,
+ PAR_BITWIDTH => c_PAR_BITWIDTH,
+ PAR_VECTOR => c_PAR_VECTOR,
+ N_PAR => c_N_PAR
+ )
+ port map(
+ RST => sl_RST,
+ CLK => CLK,
+ FIFO_FULL => sl_param_fifo_full,
+ HALT_RD => sl_param_halt_rd,
+ HALT_WR => sl_param_halt_wr,
+ SOF_RD => sl_sof_rd,
+ SOF_WR => sl_sof_wr,
+ PARAM_DT => PARAM_DT,
+ PARAM_LD => PARAM_LD,
+ SYNC_NUM => sl_sync_num,
+ PARAMETERS_RD => sl_parameters_rd,
+ PARAMETERS_WR => sl_parameters_wr
+ );
+
+ sl_halt_rd <= sl_param_halt_rd;
+-- sl_halt_wr <= sl_halt and sl_stop_rd;
+ sl_halt_wr <= sl_param_halt_wr;
+-- sl_halted <= sl_sof_rd;
+ STOP <= sl_done_wr;
+ ERROR <= sl_error;
+ BLOCK_RD <= not ( ( sl_READS(0) ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd.bak b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_rd.vhd
similarity index 87%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd.bak
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_rd.vhd
index e96b4a3fe2a9e543220e4ad9ca66e36a3bb90889..382b6a59a08dfefdc00ace3cf797510628c9d1c1 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd.bak
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_rd.vhd
@@ -1,266 +1,275 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(0 downto 0);
- READ_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_i, sl_high_i : integer;
- signal sl_loop_i, sl_loop_i_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_sof : std_logic;
- signal sl_eof : std_logic;
-
- -- alias signals
- alias update_i : std_logic is sl_cntr_en(0);
- alias load_i : std_logic is sl_load(0);
-
- -- Trigger signals
- signal sl_trigger_i : std_logic;
-
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function input parameter "data_in[i]", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
-
- signal e0, e1 : boolean;
-
- signal sl_obtain0 : std_logic;
- signal sl_release0 : std_logic;
-
- -- define control variables
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments
-
- sl_loop_i <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_i <= 0;
- sl_high_i <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
- -- Special definitions
-
- -- Entity and control variables
- -- Release matrix expressions
- e0 <= sl_loop_i_rg>=0;
- e1 <= -sl_loop_i_rg + 9>=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Read Port in_1 : EXTERNAL
- sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
- sl_release0 <= ('1');
-
- sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
- OBTAIN(0) <= sl_obtain0;
- RELEASE(0) <= sl_release0;
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function input parameter "data_in[i]", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= READ_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
- CNTR_RD : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or HALT='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and HALT='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- REG_CNTRS <= sl_reg_cntrs;
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
- SOF <= sl_sof; -- Start-of-frame
- --
-end RTL;
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_1 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(0 downto 0);
+ READ_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+end ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_1;
+
+architecture RTL of ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_1 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_i, sl_high_i : integer;
+ signal sl_loop_i, sl_loop_i_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_sof : std_logic;
+ signal sl_eof : std_logic;
+
+ -- alias signals
+ alias update_i : std_logic is sl_cntr_en(0);
+ alias load_i : std_logic is sl_load(0);
+
+ -- Trigger signals
+ signal sl_trigger_i : std_logic;
+
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- Multirate related signals
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function input parameter "data_in[i]", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+
+ signal e0, e1 : boolean;
+
+ signal sl_obtain0 : std_logic;
+ signal sl_release0 : std_logic;
+
+ -- define control variables
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ --
+ -- Parameter related signal assignments
+ sl_cnt_rst <= '0';
+ sl_halt <= '0';
+
+ sl_loop_i <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_i <= 0;
+ sl_high_i <= 2919;
+
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+ -- Special definitions
+
+ -- Entity and control variables
+ -- Release matrix expressions
+ e0 <= sl_loop_i_rg>=0;
+ e1 <= -sl_loop_i_rg + 2919>=0;
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Read Port in_1 : EXTERNAL
+ sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
+ sl_release0 <= ('1');
+
+ sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
+ OBTAIN(0) <= sl_obtain0;
+ RELEASE(0) <= sl_release0;
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function input parameter "data_in[i]", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ --
+ READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ sl_mr_en <= READ_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+ CNTR_RD : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true and sl_halt='0') then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ REG_CNTRS <= sl_reg_cntrs;
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ sl_cntr_en(0) <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
+ SOF <= sl_eof; -- Start-of-frame
+ --
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd.bak b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_wr.vhd
similarity index 87%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd.bak
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_wr.vhd
index 801f3df0a72ea5bbe44b4521457f63a31a4b3e4f..9002b0cf89282e26775c9e41a1b23acc37a2b0c1 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd.bak
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_wr.vhd
@@ -1,252 +1,261 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(0 downto 0);
- WRITE_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function output parameter "out_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_i, sl_high_i : integer;
- signal sl_loop_i, sl_loop_i_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_eof : std_logic;
- signal sl_sof : std_logic;
- --
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- alias signals
- alias update_i : std_logic is sl_cntr_en(0);
- --
- alias load_i : std_logic is sl_load(0);
- -- Trigger signals
- signal sl_trigger_i : std_logic;
-
-
- -- define control variables
- -- MOD related signals
-
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments
-
- sl_loop_i <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_i <= 0;
- sl_high_i <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
-
- -- Special definitions
-
- -- Entity and control variables
-
- sl_fire <= ('1');
-
- -- Convert FIFO Write Port out_1 : ED_1
- sl_CONTROL(0) <= sl_fire and ('1');
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function output parameter "out_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
- CNTR_WR : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or HALT='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and HALT='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
- SOF <= sl_sof; -- Start-of-frame (FF)
- --
-end RTL;
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_1 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ WRITE_EN : out std_logic_vector(0 downto 0);
+ WRITE_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+end ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_1;
+
+architecture RTL of ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_1 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ -- Multirate related signals
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function output parameter "out_0", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_i, sl_high_i : integer;
+ signal sl_loop_i, sl_loop_i_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_eof : std_logic;
+ signal sl_sof : std_logic;
+ --
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- alias signals
+ alias update_i : std_logic is sl_cntr_en(0);
+ --
+ alias load_i : std_logic is sl_load(0);
+ -- Trigger signals
+ signal sl_trigger_i : std_logic;
+
+
+ -- define control variables
+ -- MOD related signals
+
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ --
+ -- Parameter related signal assignments
+ sl_cnt_rst <= '0';
+ sl_halt <= '0';
+
+ sl_loop_i <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_i <= 0;
+ sl_high_i <= 2919;
+
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+
+ -- Special definitions
+
+ -- Entity and control variables
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Write Port out_1 : ED_1
+ sl_CONTROL(0) <= sl_fire and ('1');
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function output parameter "out_0", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ --
+ WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+ CNTR_WR : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true and sl_halt='0') then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ sl_cntr_en(0) <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
+ SOF <= sl_eof; -- Start-of-frame (FF)
+ --
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_execution_unit.vhd.bak b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_execution_unit.vhd
similarity index 83%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_execution_unit.vhd.bak
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_execution_unit.vhd
index 356b704093aa1eaf9f416bf792f3c7c1e66e4243..b510d0406f3367ae3970f605a5e41e4e22f28b94 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_execution_unit.vhd.bak
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_execution_unit.vhd
@@ -1,106 +1,109 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_ipcore2RTL_functions_1;
-use compaandesign_com_ipcore2RTL_functions_1.all;
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "tmp1"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "tmp0"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
-
- component compaan_outlinedproc0 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : compaan_outlinedproc0
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_tmp1 => IN_PORT_0,
- -- Iterators
- it_i => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_tmp0 => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
+-- Execute Unit automatically generated by KpnMapper
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_ipcore2rtl_functions_1_lib;
+use compaandesign_com_ipcore2rtl_functions_1_lib.all;
+
+entity ipcore2rtl_EXECUTION_UNIT_hwn_nd_1 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ STIM_DIR : string := "bla";
+ QUANT : natural := 32;
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Funtion Input parameters
+ IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "tmp1"
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+ -- Funtion Output parameters
+ OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "tmp0"
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end ipcore2rtl_EXECUTION_UNIT_hwn_nd_1 ;
+
+-- Laura implementation
+architecture Laura of ipcore2rtl_EXECUTION_UNIT_hwn_nd_1 is
+
+ component compaan_outlinedproc0 is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(31 downto 0);
+ -- Iterators
+ it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(31 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when IP_RESET=1 else not RST;
+
+ FUNC : compaan_outlinedproc0
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- Inputs
+ ip_tmp1 => IN_PORT_0,
+ -- Iterators
+ it_i => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+ EXIST => EXIST,
+ READF => READ,
+ -- Outputs
+ op_tmp0 => OUT_PORT_0,
+ FULL => FULL,
+ WRITEF=> WRITE,
+ --
+ STOP_RD => STOP_RD,
+ STOP_WR => STOP_WR,
+ ERROR => ERROR
+ );
+
+end Laura;
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..fbc97274bd14bbd46864a1d324270dbb01543302
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_ipcore2rtl_hwn_nd_2_1
+hdl_library_clause_name = compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib
+hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/ipcore2rtl_hwn_nd_2_execution_unit.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_rd.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_wr.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_2.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd.bak b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2.vhd
similarity index 84%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd.bak
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2.vhd
index 3cf2c35e0c318dc281dd8ab9d8fb43845860a628..a031df8598872101e5006a291e2d0f048268be7d 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd.bak
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2.vhd
@@ -1,456 +1,476 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-
-entity ipcore2RTL_hwn_nd_2 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 16;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- -- ED_1 : in_0
- ND_2IP_1_Rd : out std_logic;
- ND_2IP_1_Din : in std_logic_vector(31 downto 0);
- ND_2IP_1_Exist : in std_logic;
- ND_2IP_1_CLK : out std_logic;
- ND_2IP_1_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- -- ED_2 : out_0
- ND_2OP_1_Wr : out std_logic;
- ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_Full : in std_logic;
- ND_2OP_1_CLK : out std_logic;
- ND_2OP_1_CTRL : out std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_2;
-
-architecture RTL of ipcore2RTL_hwn_nd_2 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 1; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 0; -- number of global parameters
- constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- a
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- b
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(0 downto 0)
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(1*32-1 downto 0); -- a
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- a
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- b
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(0 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- ND_2IP_1_CLK <= CLK;
- ND_2OP_1_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "a"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 1,
- PORT_WIDTH => 32
- )
- port map (
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(0 downto 0),
- READS => sl_READS(0 downto 0),
- SOFS => sl_CTRLS(0 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(0 downto 0),
- OBTAIN => sl_obtain_rd(0 downto 0),
- RELEASE => sl_release_rd(0 downto 0)
- );
-
- ND_2IP_1_Rd <= sl_READS(0);
-
- sl_IN_PORTS_0 <= ND_2IP_1_Din;
-
- sl_EXISTS(0) <= ND_2IP_1_Exist ;
- sl_CTRLS(0) <= ND_2IP_1_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "b"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 1
- )
- port map (
- WRITES => sl_WRITES(0 downto 0),
- FULLS => sl_FULLS(0 downto 0),
- CONTROL => sl_lortnoc_wr(0 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- ND_2OP_1_Dout <= sl_out_port_0; -- Func. Output param. "b"
- ND_2OP_1_CTRL <= sl_sof_wr ;
- ND_2OP_1_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= ND_2OP_1_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_2
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- PARAMETERS => sl_parameters
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) ) );
-
-end RTL;
+-- HWN Entity File automatically generated by KpnMapper
+-- Top level file for a Hardware Accelerator
+-- Function "transformer"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+entity ipcore2rtl_hwn_nd_2 is
+ generic (
+ STIM_DIR : string := "bla";
+ RESET_HIGH : natural := 1;
+ PAR_WIDTH : natural := 16;
+ QUANT : natural := 32;
+ WRAP : boolean := true
+ );
+ port (
+
+ -- Dataflow input interfaces
+ -- ED_1 : in_0
+ ND_2IP_1_Rd : out std_logic;
+ ND_2IP_1_Din : in std_logic_vector(31 downto 0);
+ ND_2IP_1_Exist : in std_logic;
+ ND_2IP_1_CLK : out std_logic;
+ ND_2IP_1_CTRL : in std_logic;
+
+ -- Dataflow output interfaces
+ -- ED_2 : out_0
+ ND_2OP_1_Wr : out std_logic;
+ ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
+ ND_2OP_1_Full : in std_logic;
+ ND_2OP_1_CLK : out std_logic;
+ ND_2OP_1_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(PAR_WIDTH+10-1 downto 0);
+ PARAM_LD : in std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic
+ );
+end ipcore2rtl_hwn_nd_2;
+
+architecture RTL of ipcore2rtl_hwn_nd_2 is
+ --
+ -- ====================================
+ -- = Constants declaration =
+ -- ====================================
+ -- Setting the parameters of the HW Node
+ constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
+ constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
+ constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
+ constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+ constant c_COUNTERS : natural := 1; -- number of iterators
+ -- ===========================================
+ -- = Iterators run from Inner to Outer loop =
+ -- ===========================================
+ constant c_CNTR_QUANT : natural := 13;
+ constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
+ constant c_CNTR_WIDTHS : t_counter_width := ( 0=>13, others=>10 );
+ constant c_STAGES : natural := 1; -- number of pipeline stages or delay
+ constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
+ constant c_WRAP : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
+ constant c_PAR_NUMBER : natural := 0; -- number of global parameters
+ constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
+ constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
+ constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+ (0,0,0,0), (0,0,0,0) -- two dummy elements
+ );
+ --
+ -- ====================================
+ -- = Components declaration =
+ -- ====================================
+ component ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_2 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+ end component;
+
+ component READ_MUX is
+ generic (
+ N_PORTS : natural := 1;
+ PORT_WIDTH : natural := 32
+ );
+ port(
+ IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+ EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
+ READS : out std_logic_vector(N_PORTS-1 downto 0);
+ SOFS : in std_logic_vector(N_PORTS-1 downto 0);
+
+ OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
+ EXIST : out std_logic;
+ READ : in std_logic;
+ SOF : in std_logic;
+
+ READ_EN : in std_logic;
+ READ_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
+ OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
+ RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+ component ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_2 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+ end component;
+
+ component WRITE_DEMUX is
+ generic (
+ N_PORTS : natural := 1
+ );
+ port(
+ WRITES : out std_logic_vector(N_PORTS-1 downto 0);
+ WRITE : in std_logic;
+
+ FULLS : in std_logic_vector(N_PORTS-1 downto 0);
+ FULL : out std_logic;
+
+ WRITE_EN : in std_logic;
+ WRITE_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+ component ipcore2rtl_EXECUTION_UNIT_hwn_nd_2 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ QUANT : natural := 32;
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+ -- Func. Input parameters
+ IN_PORT_0 : in std_logic_vector(31 downto 0); -- a
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Func. Output parameters
+ OUT_PORT_0 : out std_logic_vector(31 downto 0); -- b
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ component PARAMETERS is
+ generic (
+ PAR_WIDTH : natural:=16;
+ PAR_BITWIDTH : natural:=1;
+ PAR_VECTOR : t_par_vector;
+ N_PAR : natural:=0
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ FIFO_FULL : out std_logic;
+ HALT_RD : out std_logic;
+ HALT_WR : out std_logic;
+ SOF_RD : in std_logic;
+ SOF_WR : in std_logic;
+ SYNC_NUM : out std_logic_vector(9 downto 0);
+
+ PARAM_DT : in std_logic_vector(PAR_WIDTH+10-1 downto 0);
+ PARAM_LD : in std_logic;
+
+ PARAMETERS_RD : out std_logic_vector(0 downto 0);
+ PARAMETERS_WR : out std_logic_vector(0 downto 0)
+ );
+ end component;
+
+ --
+ -- ====================================
+ -- = Signals declaration =
+ -- ====================================
+ --
+ -- HW Node Input Ports
+ signal sl_IN_PORTS_0 : std_logic_vector(1*32-1 downto 0); -- a
+ signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ --
+ -- Func. Input parameters
+ signal sl_in_port_0 : std_logic_vector(31 downto 0); -- a
+ signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ --
+ signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+ --
+ -- HW Node Output Ports
+ signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ --
+ -- Func. Output parameters
+ signal sl_out_port_0 : std_logic_vector(31 downto 0); -- b
+ signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ --
+ --
+ signal sl_halt : std_logic;
+ signal sl_halted : std_logic;
+ signal sl_halt_wr : std_logic;
+ signal sl_halt_rd : std_logic;
+ signal sl_param_halt_wr : std_logic;
+ signal sl_param_halt_rd : std_logic;
+ signal sl_done_wr : std_logic;
+ signal sl_done_rd : std_logic;
+ signal sl_stop_wr : std_logic;
+ signal sl_stop_rd : std_logic;
+ signal sl_fire_wr : std_logic;
+ signal sl_fire_rd : std_logic;
+ signal sl_sof_wr : std_logic;
+ signal sl_sof_rd : std_logic;
+ signal sl_error : std_logic;
+
+ --
+ -- Parameter related signals
+ signal sl_parameters_rd : std_logic_vector(0 downto 0);
+ signal sl_parameters_wr : std_logic_vector(0 downto 0);
+ signal sl_param_fifo_full : std_logic;
+ signal sl_sync_num : std_logic_vector(9 downto 0);
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when RESET_HIGH=1 else not RST;
+ ND_2IP_1_CLK <= CLK;
+ ND_2OP_1_CLK <= CLK;
+
+ --
+ -- ==========================================================
+ -- = HWN Input related modules =
+ -- ==========================================================
+ -- Func. Input param. "a"
+ RD_MUX_0 : READ_MUX
+ generic map (
+ N_PORTS => 1,
+ PORT_WIDTH => 32
+ )
+ port map (
+ IN_PORTS => sl_IN_PORTS_0,
+ EXISTS => sl_EXISTS(0 downto 0),
+ READS => sl_READS(0 downto 0),
+ SOFS => sl_CTRLS(0 downto 0),
+
+ OUT_PORT => sl_in_port_0,
+ EXIST => sl_exist(0),
+ READ => sl_read(0),
+ SOF => sl_sof_rd,
+
+ READ_EN => sl_read_en(0),
+ READ_ST => sl_read_st(0),
+ CONTROL => sl_control_rd(0 downto 0),
+ OBTAIN => sl_obtain_rd(0 downto 0),
+ RELEASE => sl_release_rd(0 downto 0)
+ );
+
+ ND_2IP_1_Rd <= sl_READS(0);
+
+ sl_IN_PORTS_0 <= ND_2IP_1_Din;
+
+ sl_EXISTS(0) <= ND_2IP_1_Exist ;
+ sl_CTRLS(0) <= ND_2IP_1_CTRL ;
+
+ EVAL_RD : ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_2
+ generic map (
+ N_IN_PORTS => c_IN_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map(
+ RST => sl_RST,
+ CLK => CLK,
+ PARAMETERS => sl_parameters_rd,
+ REG_CNTRS => sl_REG_CNTRS_RD,
+ READ_EN => sl_read_en,
+ READ_ST => sl_read_st,
+ HALT => sl_halt_rd,
+ FIRE => sl_fire_rd,
+ DONE => sl_done_rd,
+ STOP => sl_stop_rd,
+ SOF => sl_sof_rd,
+ CONTROL => sl_control_rd,
+ OBTAIN => sl_obtain_rd,
+ RELEASE => sl_release_rd
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Output related modules =
+ -- ==========================================================
+ --
+ -- Func. Output param. "b"
+ DEMUX_0 : WRITE_DEMUX
+ generic map (
+ N_PORTS => 1
+ )
+ port map (
+ WRITES => sl_WRITES(0 downto 0),
+ FULLS => sl_FULLS(0 downto 0),
+ CONTROL => sl_lortnoc_wr(0 downto 0),
+ WRITE => sl_write(0),
+ FULL => sl_full(0),
+ WRITE_EN => sl_write_en(0),
+ WRITE_ST => sl_write_st(0)
+ );
+ --
+ ND_2OP_1_Dout <= sl_out_port_0; -- Func. Output param. "b"
+ ND_2OP_1_CTRL <= sl_sof_wr ;
+ ND_2OP_1_Wr <= sl_WRITES(0);
+ sl_FULLS(0) <= ND_2OP_1_Full;
+ sl_lortnoc_wr(0) <= sl_control_wr(0);
+ --
+ --
+ EVAL_WR : ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_2
+ generic map (
+ N_OUT_PORTS => c_OUT_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ PARAMETERS => sl_parameters_wr,
+ WRITE_EN => sl_write_en,
+ WRITE_ST => sl_write_st,
+ HALT => sl_halt_wr,
+ FIRE => sl_fire_wr,
+ DONE => sl_done_wr,
+ STOP => sl_stop_wr,
+ SOF => sl_sof_wr,
+ CONTROL => sl_control_wr
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Execution Unit =
+ -- ==========================================================
+ EX : ipcore2rtl_EXECUTION_UNIT_hwn_nd_2
+ generic map (
+ N_INPORTS => c_IN_FUNC_VAR,
+ N_OUTPORTS => c_OUT_FUNC_VAR,
+ IP_RESET => c_IP_RESET,
+ QUANT => QUANT,
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => c_COUNTERS,
+ CNTR_QUANT => c_CNTR_QUANT,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- Iterators
+ REG_CNTRS_RD => sl_REG_CNTRS_RD,
+ -- Func. Input parameters
+ IN_PORT_0 => sl_in_port_0,
+ READ => sl_read,
+ EXIST => sl_exist,
+ -- Func. Output parameters
+ OUT_PORT_0 => sl_out_port_0,
+ WRITE => sl_write,
+ FULL => sl_full,
+ --
+ STOP_WR => sl_stop_wr,
+ STOP_RD => sl_stop_rd,
+ ERROR => sl_error
+ );
+
+ PAR_LOAD : PARAMETERS
+ generic map (
+ PAR_WIDTH => PAR_WIDTH,
+ PAR_BITWIDTH => c_PAR_BITWIDTH,
+ PAR_VECTOR => c_PAR_VECTOR,
+ N_PAR => c_N_PAR
+ )
+ port map(
+ RST => sl_RST,
+ CLK => CLK,
+ FIFO_FULL => sl_param_fifo_full,
+ HALT_RD => sl_param_halt_rd,
+ HALT_WR => sl_param_halt_wr,
+ SOF_RD => sl_sof_rd,
+ SOF_WR => sl_sof_wr,
+ PARAM_DT => PARAM_DT,
+ PARAM_LD => PARAM_LD,
+ SYNC_NUM => sl_sync_num,
+ PARAMETERS_RD => sl_parameters_rd,
+ PARAMETERS_WR => sl_parameters_wr
+ );
+
+ sl_halt_rd <= sl_param_halt_rd;
+-- sl_halt_wr <= sl_halt and sl_stop_rd;
+ sl_halt_wr <= sl_param_halt_wr;
+-- sl_halted <= sl_sof_rd;
+ STOP <= sl_done_wr;
+ ERROR <= sl_error;
+ BLOCK_RD <= not ( ( sl_READS(0) ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_rd.vhd
similarity index 87%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_rd.vhd
index 68e933311dd02539c5c2544d083493ef64394a0a..4c22ec8b66d255d247c2583aa67b60d3a75dcc09 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_rd.vhd
@@ -1,260 +1,272 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(0 downto 0);
- READ_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_j, sl_high_j : integer;
- signal sl_loop_j, sl_loop_j_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_sof : std_logic;
- signal sl_eof : std_logic;
-
- -- alias signals
- alias update_j : std_logic is sl_cntr_en(0);
- alias load_j : std_logic is sl_load(0);
-
- -- Trigger signals
- signal sl_trigger_j : std_logic;
-
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function input parameter "in_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
-
-
- signal sl_obtain0 : std_logic;
- signal sl_release0 : std_logic;
-
- -- define control variables
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments
-
- sl_loop_j <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_j <= 0;
- sl_high_j <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
- -- Special definitions
-
- -- Entity and control variables
- -- Release matrix expressions
-
- sl_fire <= ('1');
-
- -- Convert FIFO Read Port ND_2IP_1 Argument in_1 : ED_1 : 0 of type IOMM
- sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
- sl_release0 <= ('1');
-
- sl_CONTROL(0) <= sl_fire and ('1');
- OBTAIN(0) <= sl_obtain0;
- RELEASE(0) <= sl_release0;
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function input parameter "in_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= READ_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
- CNTR_RD : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or HALT='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and HALT='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- REG_CNTRS <= sl_reg_cntrs;
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
- SOF <= sl_sof; -- Start-of-frame
- --
-end RTL;
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_2 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(0 downto 0);
+ READ_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+end ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_2;
+
+architecture RTL of ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_2 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_j, sl_high_j : integer;
+ signal sl_loop_j, sl_loop_j_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_sof : std_logic;
+ signal sl_eof : std_logic;
+
+ -- alias signals
+ alias update_j : std_logic is sl_cntr_en(0);
+ alias load_j : std_logic is sl_load(0);
+
+ -- Trigger signals
+ signal sl_trigger_j : std_logic;
+
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- Multirate related signals
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function input parameter "in_0", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+
+
+ signal sl_obtain0 : std_logic;
+ signal sl_release0 : std_logic;
+
+ -- define control variables
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ --
+ -- Parameter related signal assignments
+ sl_cnt_rst <= '0';
+ sl_halt <= '0';
+
+ sl_loop_j <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_j <= 0;
+ sl_high_j <= 2919;
+
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+ -- Special definitions
+
+ -- Entity and control variables
+ -- Release matrix expressions
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Read Port ND_2IP_1 Argument in_1 : ED_1 : 0 of type IOMM
+ sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
+ sl_release0 <= ('1');
+
+ sl_CONTROL(0) <= sl_fire and ('1');
+ OBTAIN(0) <= sl_obtain0;
+ RELEASE(0) <= sl_release0;
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function input parameter "in_0", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ --
+ READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ sl_mr_en <= READ_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+ CNTR_RD : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true and sl_halt='0') then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ REG_CNTRS <= sl_reg_cntrs;
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ sl_cntr_en(0) <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
+ SOF <= sl_eof; -- Start-of-frame
+ --
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_wr.vhd
similarity index 86%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_wr.vhd
index 13de23943aa7060f73e921574e0702f4f45d034e..bb29008ea947a9a0b2f8e1168615d9a251c79d1c 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_wr.vhd
@@ -1,249 +1,261 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(31 downto 0);
- WRITE_EN : out std_logic_vector(0 downto 0);
- WRITE_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function output parameter "out_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_j, sl_high_j : integer;
- signal sl_loop_j, sl_loop_j_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_eof : std_logic;
- signal sl_sof : std_logic;
- --
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- alias signals
- alias update_j : std_logic is sl_cntr_en(0);
- --
- alias load_j : std_logic is sl_load(0);
- -- Trigger signals
- signal sl_trigger_j : std_logic;
-
-
- -- define control variables
- -- MOD related signals
-
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments
-
- sl_loop_j <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_j <= 0;
- sl_high_j <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
-
- -- Special definitions
-
- -- Entity and control variables
-
- sl_fire <= ('1');
-
- -- Convert FIFO Write Port out_1 : ED_2
- sl_CONTROL(0) <= sl_fire and ('1');
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function output parameter "out_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
- CNTR_WR : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or HALT='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and HALT='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
- SOF <= sl_sof; -- Start-of-frame (FF)
- --
-end RTL;
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_2 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ WRITE_EN : out std_logic_vector(0 downto 0);
+ WRITE_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+end ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_2;
+
+architecture RTL of ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_2 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ -- Multirate related signals
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function output parameter "out_0", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_j, sl_high_j : integer;
+ signal sl_loop_j, sl_loop_j_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_eof : std_logic;
+ signal sl_sof : std_logic;
+ --
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- alias signals
+ alias update_j : std_logic is sl_cntr_en(0);
+ --
+ alias load_j : std_logic is sl_load(0);
+ -- Trigger signals
+ signal sl_trigger_j : std_logic;
+
+
+ -- define control variables
+ -- MOD related signals
+
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ --
+ -- Parameter related signal assignments
+ sl_cnt_rst <= '0';
+ sl_halt <= '0';
+
+ sl_loop_j <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_j <= 0;
+ sl_high_j <= 2919;
+
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+
+ -- Special definitions
+
+ -- Entity and control variables
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Write Port out_1 : ED_2
+ sl_CONTROL(0) <= sl_fire and ('1');
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function output parameter "out_0", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ --
+ WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+ CNTR_WR : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true and sl_halt='0') then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ sl_cntr_en(0) <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
+ SOF <= sl_eof; -- Start-of-frame (FF)
+ --
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_execution_unit.vhd.bak b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_execution_unit.vhd
similarity index 83%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_execution_unit.vhd.bak
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_execution_unit.vhd
index 780b1b3d9c340ab6b24a26a607ff8e4e91449d1e..50cdcd2372656d43592fa0c1b4609b7003d62321 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_execution_unit.vhd.bak
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_execution_unit.vhd
@@ -1,105 +1,109 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-library compaandesign_com_ipcore2RTL_functions_1;
-use compaandesign_com_ipcore2RTL_functions_1.all;
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "a"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "b"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
-
- component transformer is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : transformer
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_a => IN_PORT_0,
- -- Iterators
- it_j => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_b => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
+-- Execute Unit automatically generated by KpnMapper
+-- Function "transformer"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_ipcore2rtl_functions_1_lib;
+use compaandesign_com_ipcore2rtl_functions_1_lib.all;
+
+entity ipcore2rtl_EXECUTION_UNIT_hwn_nd_2 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ STIM_DIR : string := "bla";
+ QUANT : natural := 32;
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Funtion Input parameters
+ IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "a"
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+ -- Funtion Output parameters
+ OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "b"
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end ipcore2rtl_EXECUTION_UNIT_hwn_nd_2 ;
+
+-- Laura implementation
+architecture Laura of ipcore2rtl_EXECUTION_UNIT_hwn_nd_2 is
+
+ component transformer is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_a : in std_logic_vector(31 downto 0);
+ -- Iterators
+ it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Outputs
+ op_b : out std_logic_vector(31 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when IP_RESET=1 else not RST;
+
+ FUNC : transformer
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- Inputs
+ ip_a => IN_PORT_0,
+ -- Iterators
+ it_j => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+ EXIST => EXIST,
+ READF => READ,
+ -- Outputs
+ op_b => OUT_PORT_0,
+ FULL => FULL,
+ WRITEF=> WRITE,
+ --
+ STOP_RD => STOP_RD,
+ STOP_WR => STOP_WR,
+ ERROR => ERROR
+ );
+
+end Laura;
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..abe75a4174e343eee1cb5f210dbab33446e96ae4
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_ipcore2rtl_hwn_nd_3_1
+hdl_library_clause_name = compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib
+hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/ipcore2rtl_hwn_nd_3_execution_unit.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_rd.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_wr.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_3.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd.bak b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3.vhd
similarity index 84%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd.bak
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3.vhd
index 9245c951bececd433c09333ee11e05c88cbce2a8..e3be61b674a512c4fe4f9f6c9927bd7c1fe2949d 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd.bak
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3.vhd
@@ -1,481 +1,475 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.hw_node_pkg.all;
-
-entity ipcore2RTL_hwn_nd_3 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 16;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- -- ED_2 : in_0
- ND_3IP_2_Rd : out std_logic;
- ND_3IP_2_Din : in std_logic_vector(31 downto 0);
- ND_3IP_2_Exist : in std_logic;
- ND_3IP_2_CLK : out std_logic;
- ND_3IP_2_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
- data_out_SOP : out std_logic;
- data_out_EOP : out std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_hwn_nd_3 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 1; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 0; -- number of global parameters
- constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- tmp1
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- tmp0
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(0 downto 0)
- );
- end component;
-
- component pkg_signals is
- port (
- data_write : in std_logic;
- data_data : in std_logic_vector(31 downto 0);
- eop : out std_logic;
- sop : out std_logic;
- data_write_out : out std_logic;
- data_data_out : out std_logic_vector(31 downto 0);
- RST : in std_logic;
- CLK : in std_logic
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(1*32-1 downto 0); -- tmp1
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- tmp1
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- tmp0
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(0 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- ND_3IP_2_CLK <= CLK;
- data_out_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "tmp1"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 1,
- PORT_WIDTH => 32
- )
- port map (
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(0 downto 0),
- READS => sl_READS(0 downto 0),
- SOFS => sl_CTRLS(0 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(0 downto 0),
- OBTAIN => sl_obtain_rd(0 downto 0),
- RELEASE => sl_release_rd(0 downto 0)
- );
-
- ND_3IP_2_Rd <= sl_READS(0);
-
- sl_IN_PORTS_0 <= ND_3IP_2_Din;
-
- sl_EXISTS(0) <= ND_3IP_2_Exist ;
- sl_CTRLS(0) <= ND_3IP_2_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "tmp0"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 1
- )
- port map (
- WRITES => sl_WRITES(0 downto 0),
- FULLS => sl_FULLS(0 downto 0),
- CONTROL => sl_lortnoc_wr(0 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- --data_out_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
- data_out_CTRL <= sl_sof_wr ;
- --data_out_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= data_out_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
-
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_3
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- PARAMETERS => sl_parameters
- );
-
- PKG_SIGNALS_GEN : pkg_signals
- port map (
- data_write => sl_WRITES(0),
- data_data => sl_out_port_0,
- eop => data_out_EOP,
- sop => data_out_SOP,
- data_write_out => data_out_Dout,
- data_data_out => data_out_Wr,
- RST => sl_RST,
- CLK => CLK
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) ) );
-
-end RTL;
+-- HWN Entity File automatically generated by KpnMapper
+-- Top level file for a Hardware Accelerator
+-- Function "compaan_outlinedproc1"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+entity ipcore2rtl_hwn_nd_3 is
+ generic (
+ STIM_DIR : string := "bla";
+ RESET_HIGH : natural := 1;
+ PAR_WIDTH : natural := 16;
+ QUANT : natural := 32;
+ WRAP : boolean := true
+ );
+ port (
+
+ -- Dataflow input interfaces
+ -- ED_2 : in_0
+ ND_3IP_2_Rd : out std_logic;
+ ND_3IP_2_Din : in std_logic_vector(31 downto 0);
+ ND_3IP_2_Exist : in std_logic;
+ ND_3IP_2_CLK : out std_logic;
+ ND_3IP_2_CTRL : in std_logic;
+
+ -- Dataflow output interfaces
+ data_out_Wr : out std_logic;
+ data_out_Dout : out std_logic_vector(31 downto 0);
+ data_out_Full : in std_logic;
+ data_out_CLK : out std_logic;
+ data_out_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(PAR_WIDTH+10-1 downto 0);
+ PARAM_LD : in std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic
+ );
+end ipcore2rtl_hwn_nd_3;
+
+architecture RTL of ipcore2rtl_hwn_nd_3 is
+ --
+ -- ====================================
+ -- = Constants declaration =
+ -- ====================================
+ -- Setting the parameters of the HW Node
+ constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
+ constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
+ constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
+ constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+ constant c_COUNTERS : natural := 1; -- number of iterators
+ -- ===========================================
+ -- = Iterators run from Inner to Outer loop =
+ -- ===========================================
+ constant c_CNTR_QUANT : natural := 13;
+ constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
+ constant c_CNTR_WIDTHS : t_counter_width := ( 0=>13, others=>10 );
+ constant c_STAGES : natural := 1; -- number of pipeline stages or delay
+ constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
+ constant c_WRAP : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
+ constant c_PAR_NUMBER : natural := 0; -- number of global parameters
+ constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
+ constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
+ constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+ (0,0,0,0), (0,0,0,0) -- two dummy elements
+ );
+ --
+ -- ====================================
+ -- = Components declaration =
+ -- ====================================
+ component ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_3 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+ end component;
+
+ component READ_MUX is
+ generic (
+ N_PORTS : natural := 1;
+ PORT_WIDTH : natural := 32
+ );
+ port(
+ IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+ EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
+ READS : out std_logic_vector(N_PORTS-1 downto 0);
+ SOFS : in std_logic_vector(N_PORTS-1 downto 0);
+
+ OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
+ EXIST : out std_logic;
+ READ : in std_logic;
+ SOF : in std_logic;
+
+ READ_EN : in std_logic;
+ READ_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
+ OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
+ RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+ component ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_3 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+ end component;
+
+ component WRITE_DEMUX is
+ generic (
+ N_PORTS : natural := 1
+ );
+ port(
+ WRITES : out std_logic_vector(N_PORTS-1 downto 0);
+ WRITE : in std_logic;
+
+ FULLS : in std_logic_vector(N_PORTS-1 downto 0);
+ FULL : out std_logic;
+
+ WRITE_EN : in std_logic;
+ WRITE_ST : out std_logic;
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
+ );
+ end component;
+
+ component ipcore2rtl_EXECUTION_UNIT_hwn_nd_3 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ QUANT : natural := 32;
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+ -- Func. Input parameters
+ IN_PORT_0 : in std_logic_vector(31 downto 0); -- tmp1
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Func. Output parameters
+ OUT_PORT_0 : out std_logic_vector(31 downto 0); -- tmp0
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ component PARAMETERS is
+ generic (
+ PAR_WIDTH : natural:=16;
+ PAR_BITWIDTH : natural:=1;
+ PAR_VECTOR : t_par_vector;
+ N_PAR : natural:=0
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ FIFO_FULL : out std_logic;
+ HALT_RD : out std_logic;
+ HALT_WR : out std_logic;
+ SOF_RD : in std_logic;
+ SOF_WR : in std_logic;
+ SYNC_NUM : out std_logic_vector(9 downto 0);
+
+ PARAM_DT : in std_logic_vector(PAR_WIDTH+10-1 downto 0);
+ PARAM_LD : in std_logic;
+
+ PARAMETERS_RD : out std_logic_vector(0 downto 0);
+ PARAMETERS_WR : out std_logic_vector(0 downto 0)
+ );
+ end component;
+
+ --
+ -- ====================================
+ -- = Signals declaration =
+ -- ====================================
+ --
+ -- HW Node Input Ports
+ signal sl_IN_PORTS_0 : std_logic_vector(1*32-1 downto 0); -- tmp1
+ signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
+ --
+ -- Func. Input parameters
+ signal sl_in_port_0 : std_logic_vector(31 downto 0); -- tmp1
+ signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+ --
+ signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+ --
+ -- HW Node Output Ports
+ signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
+ --
+ -- Func. Output parameters
+ signal sl_out_port_0 : std_logic_vector(31 downto 0); -- tmp0
+ signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+ --
+ --
+ signal sl_halt : std_logic;
+ signal sl_halted : std_logic;
+ signal sl_halt_wr : std_logic;
+ signal sl_halt_rd : std_logic;
+ signal sl_param_halt_wr : std_logic;
+ signal sl_param_halt_rd : std_logic;
+ signal sl_done_wr : std_logic;
+ signal sl_done_rd : std_logic;
+ signal sl_stop_wr : std_logic;
+ signal sl_stop_rd : std_logic;
+ signal sl_fire_wr : std_logic;
+ signal sl_fire_rd : std_logic;
+ signal sl_sof_wr : std_logic;
+ signal sl_sof_rd : std_logic;
+ signal sl_error : std_logic;
+
+ --
+ -- Parameter related signals
+ signal sl_parameters_rd : std_logic_vector(0 downto 0);
+ signal sl_parameters_wr : std_logic_vector(0 downto 0);
+ signal sl_param_fifo_full : std_logic;
+ signal sl_sync_num : std_logic_vector(9 downto 0);
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when RESET_HIGH=1 else not RST;
+ ND_3IP_2_CLK <= CLK;
+ data_out_CLK <= CLK;
+
+ --
+ -- ==========================================================
+ -- = HWN Input related modules =
+ -- ==========================================================
+ -- Func. Input param. "tmp1"
+ RD_MUX_0 : READ_MUX
+ generic map (
+ N_PORTS => 1,
+ PORT_WIDTH => 32
+ )
+ port map (
+ IN_PORTS => sl_IN_PORTS_0,
+ EXISTS => sl_EXISTS(0 downto 0),
+ READS => sl_READS(0 downto 0),
+ SOFS => sl_CTRLS(0 downto 0),
+
+ OUT_PORT => sl_in_port_0,
+ EXIST => sl_exist(0),
+ READ => sl_read(0),
+ SOF => sl_sof_rd,
+
+ READ_EN => sl_read_en(0),
+ READ_ST => sl_read_st(0),
+ CONTROL => sl_control_rd(0 downto 0),
+ OBTAIN => sl_obtain_rd(0 downto 0),
+ RELEASE => sl_release_rd(0 downto 0)
+ );
+
+ ND_3IP_2_Rd <= sl_READS(0);
+
+ sl_IN_PORTS_0 <= ND_3IP_2_Din;
+
+ sl_EXISTS(0) <= ND_3IP_2_Exist ;
+ sl_CTRLS(0) <= ND_3IP_2_CTRL ;
+
+ EVAL_RD : ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_3
+ generic map (
+ N_IN_PORTS => c_IN_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map(
+ RST => sl_RST,
+ CLK => CLK,
+ PARAMETERS => sl_parameters_rd,
+ REG_CNTRS => sl_REG_CNTRS_RD,
+ READ_EN => sl_read_en,
+ READ_ST => sl_read_st,
+ HALT => sl_halt_rd,
+ FIRE => sl_fire_rd,
+ DONE => sl_done_rd,
+ STOP => sl_stop_rd,
+ SOF => sl_sof_rd,
+ CONTROL => sl_control_rd,
+ OBTAIN => sl_obtain_rd,
+ RELEASE => sl_release_rd
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Output related modules =
+ -- ==========================================================
+ --
+ -- Func. Output param. "tmp0"
+ DEMUX_0 : WRITE_DEMUX
+ generic map (
+ N_PORTS => 1
+ )
+ port map (
+ WRITES => sl_WRITES(0 downto 0),
+ FULLS => sl_FULLS(0 downto 0),
+ CONTROL => sl_lortnoc_wr(0 downto 0),
+ WRITE => sl_write(0),
+ FULL => sl_full(0),
+ WRITE_EN => sl_write_en(0),
+ WRITE_ST => sl_write_st(0)
+ );
+ --
+ data_out_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
+ data_out_CTRL <= sl_sof_wr ;
+ data_out_Wr <= sl_WRITES(0);
+ sl_FULLS(0) <= data_out_Full;
+ sl_lortnoc_wr(0) <= sl_control_wr(0);
+ --
+ --
+ EVAL_WR : ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_3
+ generic map (
+ N_OUT_PORTS => c_OUT_PORTS,
+ WRAP => c_WRAP,
+ N_CNTRS => c_COUNTERS,
+ QUANT => c_CNTR_QUANT,
+ CNTR_STEP => c_CNTR_STEPS,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ PARAMETERS => sl_parameters_wr,
+ WRITE_EN => sl_write_en,
+ WRITE_ST => sl_write_st,
+ HALT => sl_halt_wr,
+ FIRE => sl_fire_wr,
+ DONE => sl_done_wr,
+ STOP => sl_stop_wr,
+ SOF => sl_sof_wr,
+ CONTROL => sl_control_wr
+ );
+
+ --
+ -- ==========================================================
+ -- = HWN Execution Unit =
+ -- ==========================================================
+ EX : ipcore2rtl_EXECUTION_UNIT_hwn_nd_3
+ generic map (
+ N_INPORTS => c_IN_FUNC_VAR,
+ N_OUTPORTS => c_OUT_FUNC_VAR,
+ IP_RESET => c_IP_RESET,
+ QUANT => QUANT,
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => c_COUNTERS,
+ CNTR_QUANT => c_CNTR_QUANT,
+ CNTR_WIDTH => c_CNTR_WIDTHS
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- Iterators
+ REG_CNTRS_RD => sl_REG_CNTRS_RD,
+ -- Func. Input parameters
+ IN_PORT_0 => sl_in_port_0,
+ READ => sl_read,
+ EXIST => sl_exist,
+ -- Func. Output parameters
+ OUT_PORT_0 => sl_out_port_0,
+ WRITE => sl_write,
+ FULL => sl_full,
+ --
+ STOP_WR => sl_stop_wr,
+ STOP_RD => sl_stop_rd,
+ ERROR => sl_error
+ );
+
+ PAR_LOAD : PARAMETERS
+ generic map (
+ PAR_WIDTH => PAR_WIDTH,
+ PAR_BITWIDTH => c_PAR_BITWIDTH,
+ PAR_VECTOR => c_PAR_VECTOR,
+ N_PAR => c_N_PAR
+ )
+ port map(
+ RST => sl_RST,
+ CLK => CLK,
+ FIFO_FULL => sl_param_fifo_full,
+ HALT_RD => sl_param_halt_rd,
+ HALT_WR => sl_param_halt_wr,
+ SOF_RD => sl_sof_rd,
+ SOF_WR => sl_sof_wr,
+ PARAM_DT => PARAM_DT,
+ PARAM_LD => PARAM_LD,
+ SYNC_NUM => sl_sync_num,
+ PARAMETERS_RD => sl_parameters_rd,
+ PARAMETERS_WR => sl_parameters_wr
+ );
+
+ sl_halt_rd <= sl_param_halt_rd;
+-- sl_halt_wr <= sl_halt and sl_stop_rd;
+ sl_halt_wr <= sl_param_halt_wr;
+-- sl_halted <= sl_sof_rd;
+ STOP <= sl_done_wr;
+ ERROR <= sl_error;
+ BLOCK_RD <= not ( ( sl_READS(0) ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd.bak b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_rd.vhd
similarity index 87%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd.bak
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_rd.vhd
index e9fcf2cae65af385caa880002ab55489c9fb413f..47b3678fce753f5ca9a49242e336fc5e8c778b6a 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd.bak
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_rd.vhd
@@ -1,263 +1,272 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(0 downto 0);
- READ_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_x, sl_high_x : integer;
- signal sl_loop_x, sl_loop_x_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_sof : std_logic;
- signal sl_eof : std_logic;
-
- -- alias signals
- alias update_x : std_logic is sl_cntr_en(0);
- alias load_x : std_logic is sl_load(0);
-
- -- Trigger signals
- signal sl_trigger_x : std_logic;
-
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function input parameter "in_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
-
-
- signal sl_obtain0 : std_logic;
- signal sl_release0 : std_logic;
-
- -- define control variables
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments
-
- sl_loop_x <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_x_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_x <= 0;
- sl_high_x <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
- -- Special definitions
-
- -- Entity and control variables
- -- Release matrix expressions
-
- sl_fire <= ('1');
-
- -- Convert FIFO Read Port ND_3IP_2 Argument in_1 : ED_2 : 0 of type IOMM
- sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
- sl_release0 <= ('1');
-
- sl_CONTROL(0) <= sl_fire and ('1');
- OBTAIN(0) <= sl_obtain0;
- RELEASE(0) <= sl_release0;
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function input parameter "in_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= READ_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
- CNTR_RD : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or HALT='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and HALT='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- REG_CNTRS <= sl_reg_cntrs;
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
- SOF <= sl_sof; -- Start-of-frame
- --
-end RTL;
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_3 is
+ generic (
+ N_IN_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ READ_EN : out std_logic_vector(0 downto 0);
+ READ_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
+ RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
+ );
+end ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_3;
+
+architecture RTL of ipcore2rtl_EVAL_LOGIC_RD_hwn_nd_3 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_x, sl_high_x : integer;
+ signal sl_loop_x, sl_loop_x_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_sof : std_logic;
+ signal sl_eof : std_logic;
+
+ -- alias signals
+ alias update_x : std_logic is sl_cntr_en(0);
+ alias load_x : std_logic is sl_load(0);
+
+ -- Trigger signals
+ signal sl_trigger_x : std_logic;
+
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- Multirate related signals
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function input parameter "in_0", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+
+
+ signal sl_obtain0 : std_logic;
+ signal sl_release0 : std_logic;
+
+ -- define control variables
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ --
+ -- Parameter related signal assignments
+ sl_cnt_rst <= '0';
+ sl_halt <= '0';
+
+ sl_loop_x <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_x_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_x <= 0;
+ sl_high_x <= 2919;
+
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
+ -- Special definitions
+
+ -- Entity and control variables
+ -- Release matrix expressions
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Read Port ND_3IP_2 Argument in_1 : ED_2 : 0 of type IOMM
+ sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
+ sl_release0 <= ('1');
+
+ sl_CONTROL(0) <= sl_fire and ('1');
+ OBTAIN(0) <= sl_obtain0;
+ RELEASE(0) <= sl_release0;
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function input parameter "in_0", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ --
+ READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ sl_mr_en <= READ_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+ CNTR_RD : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true and sl_halt='0') then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ REG_CNTRS <= sl_reg_cntrs;
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ sl_cntr_en(0) <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
+ SOF <= sl_eof; -- Start-of-frame
+ --
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd.bak b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_wr.vhd
similarity index 87%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd.bak
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_wr.vhd
index b8a3de2eedfeffb21fd24ad87320ce227c3796c7..ca956d4ac7219e29ee7f3581090d8e68d46784c3 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd.bak
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_wr.vhd
@@ -1,255 +1,264 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(0 downto 0);
- WRITE_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function output parameter "data_out[x]", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_x, sl_high_x : integer;
- signal sl_loop_x, sl_loop_x_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_eof : std_logic;
- signal sl_sof : std_logic;
- --
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- alias signals
- alias update_x : std_logic is sl_cntr_en(0);
- --
- alias load_x : std_logic is sl_load(0);
- -- Trigger signals
- signal sl_trigger_x : std_logic;
-
- signal e0, e1 : boolean;
-
- -- define control variables
- -- MOD related signals
-
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments
-
- sl_loop_x <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_x_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_x <= 0;
- sl_high_x <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
-
- -- Special definitions
-
- -- Entity and control variables
- e0 <= sl_loop_x_rg>=0;
- e1 <= -sl_loop_x_rg + 9>=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Write Port out_1 : EXTERNAL
- sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function output parameter "data_out[x]", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
- CNTR_WR : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or HALT='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and HALT='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
- SOF <= sl_sof; -- Start-of-frame (FF)
- --
-end RTL;
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_3 is
+ generic (
+ N_OUT_PORTS : natural := 1;
+ WRAP : boolean := true;
+ N_CNTRS : natural := 1;
+ QUANT : natural := 32;
+ CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ PARAMETERS : in std_logic_vector(0 downto 0);
+ WRITE_EN : out std_logic_vector(0 downto 0);
+ WRITE_ST : in std_logic_vector(0 downto 0);
+ HALT : in std_logic;
+ FIRE : out std_logic;
+ DONE : out std_logic;
+ STOP : out std_logic;
+ SOF : out std_logic;
+ CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+ );
+end ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_3;
+
+architecture RTL of ipcore2rtl_EVAL_LOGIC_WR_hwn_nd_3 is
+ --
+ component counter is
+ generic(
+ C_STEP : natural := 10;
+ C_WIDTH : natural := 10
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ ENABLE : in std_logic;
+ LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
+ ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
+ REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
+ DONE : out std_logic
+ );
+ end component;
+ --
+ component it_mod is
+ generic(
+ C_MOD : natural := 10;
+ C_WIDTH : natural := 10;
+ C_INIT : natural := 1;
+ C_STEP : natural := 1
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ LOAD : in std_logic;
+ ENABLE : in std_logic;
+ MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
+ );
+ end component;
+ --
+ -- Multirate related signals
+ signal sl_mr_en : std_logic_vector(0 downto 0);
+ signal sl_mr_done : std_logic_vector(0 downto 0);
+ signal sl_mr_lock : std_logic_vector(0 downto 0);
+ signal sl_enables : std_logic_vector(0 downto 0);
+ signal sl_enable : std_logic;
+ signal ENABLE : std_logic;
+ -- Function output parameter "data_out[x]", multirate=1
+ constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
+ --
+ -- Parameter related signals
+ --
+ -- Iterator (counter) related signals
+ signal sl_low_x, sl_high_x : integer;
+ signal sl_loop_x, sl_loop_x_rg : integer;
+ signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+ --
+ signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
+ signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_done_all : std_logic;
+ signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
+ signal sl_stop : std_logic;
+ signal sl_fire : std_logic;
+ signal sl_eof : std_logic;
+ signal sl_sof : std_logic;
+ --
+ -- Special Control signal
+ signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
+ signal sl_no_request : std_logic;
+ --
+ -- alias signals
+ alias update_x : std_logic is sl_cntr_en(0);
+ --
+ alias load_x : std_logic is sl_load(0);
+ -- Trigger signals
+ signal sl_trigger_x : std_logic;
+
+ signal e0, e1 : boolean;
+
+ -- define control variables
+ -- MOD related signals
+
+
+ type state_type is (s_idle, s_halt, s_count, s_release);
+ signal state : state_type;
+ signal halt_cnt : integer;
+ signal sl_halt : std_logic;
+
+ signal sl_cnt_rst : std_logic;
+ signal cnt_rst : std_logic;
+
+begin
+
+ -- =============================================
+ -- = MOD Functions
+ -- =============================================
+ -- END of MOD definitions
+ --
+ -- Parameter related signal assignments
+ sl_cnt_rst <= '0';
+ sl_halt <= '0';
+
+ sl_loop_x <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+ sl_loop_x_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+ -- Const bounds for-loops
+ sl_low_x <= 0;
+ sl_high_x <= 2919;
+
+
+ sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
+
+ sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
+
+ -- Special definitions
+
+ -- Entity and control variables
+ e0 <= sl_loop_x_rg>=0;
+ e1 <= -sl_loop_x_rg + 2919>=0;
+
+ sl_fire <= ('1');
+
+ -- Convert FIFO Write Port out_1 : EXTERNAL
+ sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
+
+ FIRE <= sl_fire;
+
+ cnt_rst <= sl_cnt_rst or RST;
+
+ --
+ -- =============================================
+ -- = Multirate
+ -- =============================================
+ -- Function output parameter "data_out[x]", multirate=1
+ CNTR_MR0 : counter
+ generic map (
+ C_STEP => 1,
+ C_WIDTH => 1
+ )
+ port map (
+ CLK => CLK,
+ RST => RST,
+ ENABLE => sl_mr_en(0),
+ LOWER_BND => sl_mr_lbnd_0,
+ UPPER_BND => sl_mr_ubnd_0,
+ ITERATOR => open,
+ REG_CNTR => open,
+ DONE => sl_mr_done(0)
+ );
+ --
+ WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+ sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
+ sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
+ sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
+ ENABLE <= sl_enable or (not sl_fire);
+ --
+ LOCK_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_mr_lock <= (others=>'0');
+ else
+ if (ENABLE='1') then
+ sl_mr_lock <= (others=>'0');
+ else
+ for i in 0 to 0 loop
+ if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
+ sl_mr_lock(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end if;
+ end process;
+ -- END of Multirate definitions
+ --
+ -- =============================================
+ -- = Iterators
+ -- =============================================
+ GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+ CNTR_WR : counter
+ generic map (
+ C_STEP => CNTR_STEP(i),
+ C_WIDTH => CNTR_WIDTH(i)
+ )
+ port map (
+ CLK => CLK,
+ RST => cnt_rst,
+ ENABLE => sl_cntr_en(i),
+ LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+ DONE => sl_done(i)
+ );
+ end generate;
+ --
+ DONE_PRCS: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if( RST = '1' ) then
+ sl_stop <= '0';
+ sl_done_all <= '0';
+ sl_sof <= '1';
+ else
+ if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+ sl_stop <= '1';
+ elsif (WRAP=true and sl_halt='0') then
+ sl_stop <= '0';
+ end if;
+ if (sl_stop='0') then
+ sl_done_all <= sl_cntr_en(N_CNTRS);
+ end if;
+ if (ENABLE='1') then
+ sl_sof <= sl_eof;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+ CONTROL <= sl_CONTROL;
+ --
+ DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+ STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
+ sl_cntr_en(0) <= '0' when (sl_stop='1') else
+ '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+ sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
+ sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
+ SOF <= sl_eof; -- Start-of-frame (FF)
+ --
+end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_execution_unit.vhd.bak b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_execution_unit.vhd
similarity index 83%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_execution_unit.vhd.bak
rename to applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_execution_unit.vhd
index 49933b0f6a70dc92225e172a90ccfd7525da7a6f..e96fb0c950965c7cad0a7e3b7197b7ab417ff94d 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_execution_unit.vhd.bak
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_execution_unit.vhd
@@ -1,106 +1,109 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_ipcore2RTL_functions_1;
-use compaandesign_com_ipcore2RTL_functions_1.all;
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "tmp1"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "tmp0"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
-
- component compaan_outlinedproc1 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : compaan_outlinedproc1
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_tmp1 => IN_PORT_0,
- -- Iterators
- it_x => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_tmp0 => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
+-- Execute Unit automatically generated by KpnMapper
+-- Function "compaan_outlinedproc1"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_ipcore2rtl_functions_1_lib;
+use compaandesign_com_ipcore2rtl_functions_1_lib.all;
+
+entity ipcore2rtl_EXECUTION_UNIT_hwn_nd_3 is
+ generic (
+ N_INPORTS : natural := 1;
+ N_OUTPORTS : natural := 1;
+ IP_RESET : natural := 1;
+ STIM_DIR : string := "bla";
+ QUANT : natural := 32;
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Funtion Input parameters
+ IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "tmp1"
+ READ : out std_logic_vector(N_INPORTS-1 downto 0);
+ EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
+ -- Iterators
+ REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+ -- Funtion Output parameters
+ OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "tmp0"
+ WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
+ FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+end ipcore2rtl_EXECUTION_UNIT_hwn_nd_3 ;
+
+-- Laura implementation
+architecture Laura of ipcore2rtl_EXECUTION_UNIT_hwn_nd_3 is
+
+ component compaan_outlinedproc1 is
+ generic (
+ STIM_DIR : string := "bla";
+ c_STAGES : natural := 1;
+ N_CNTRS : natural := 1;
+ CNTR_QUANT : natural := 32;
+ CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+ );
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ -- Inputs
+ ip_tmp1 : in std_logic_vector(31 downto 0);
+ -- Iterators
+ it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+ EXIST : in std_logic_vector(0 downto 0);
+ READF : out std_logic_vector(0 downto 0);
+ -- Outputs
+ op_tmp0 : out std_logic_vector(31 downto 0);
+ FULL : in std_logic_vector(0 downto 0);
+ WRITEF: out std_logic_vector(0 downto 0);
+ --
+ STOP_RD : in std_logic;
+ STOP_WR : in std_logic;
+ ERROR : out std_logic
+ );
+ end component;
+
+ signal sl_RST : std_logic;
+
+begin
+
+ sl_RST <= RST when IP_RESET=1 else not RST;
+
+ FUNC : compaan_outlinedproc1
+ generic map (
+ STIM_DIR => STIM_DIR,
+ c_STAGES => c_STAGES,
+ N_CNTRS => N_CNTRS,
+ CNTR_QUANT => CNTR_QUANT,
+ CNTR_WIDTH => CNTR_WIDTH
+ )
+ port map (
+ RST => sl_RST,
+ CLK => CLK,
+ -- Inputs
+ ip_tmp1 => IN_PORT_0,
+ -- Iterators
+ it_x => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+ EXIST => EXIST,
+ READF => READ,
+ -- Outputs
+ op_tmp0 => OUT_PORT_0,
+ FULL => FULL,
+ WRITEF=> WRITE,
+ --
+ STOP_RD => STOP_RD,
+ STOP_WR => STOP_WR,
+ ERROR => ERROR
+ );
+
+end Laura;
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/register_rf/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/register_rf/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..921a0a4da0357d634a0acd3d0886d9a9b045788d
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/register_rf/hdllib.cfg
@@ -0,0 +1,15 @@
+hdl_lib_name = compaandesign_com_ipcore2rtl_register_rf_1
+hdl_library_clause_name = compaandesign_com_ipcore2rtl_register_rf_1_lib
+hdl_lib_uses_synth =
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/register_rf.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/register_rf/src/vhdl/register_rf.vhd b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/register_rf/src/vhdl/register_rf.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7c146144853a96cea6986afe906e5c97cf0c1700
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/register_rf/src/vhdl/register_rf.vhd
@@ -0,0 +1,31 @@
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity register_rf is
+
+port (
+ rst : in std_logic;
+ clk : in std_logic;
+ pci_clk : in std_logic;
+ --
+
+ -- Interface to PCIe
+ address : in std_logic_vector(18 downto 0);
+ read_data : out std_logic_vector(31 downto 0);
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0)
+ --
+);
+end register_rf;
+
+architecture RTL of register_rf is
+
+ signal sl_read_data : std_logic_vector(32-1 downto 0) := (others=>'0');
+
+begin
+ read_data <= (others => '0');
+
+end RTL;
diff --git a/applications/compaan/libraries/vhdl_altera/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..af71b8418a27e09016c6c333ccad42319ef00543
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/hdllib.cfg
@@ -0,0 +1,21 @@
+hdl_lib_name = ipcore
+hdl_library_clause_name = ipcore_lib
+
+hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_hwn_nd_3_1 compaandesign_com_ipcore2rtl_hwn_nd_1_1 compaandesign_com_ipcore2rtl_register_rf_1 compaandesign_com_ipcore2rtl_hwn_nd_2_1 compaandesign_com_common_altera_1
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+ src/vhdl/ipcore.vhd
+ src/vhdl/ipcore2rtl_ed_1_ip_wrapper.vhd
+ src/vhdl/ipcore2rtl_ed_2_ip_wrapper.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_1_ip_wrapper.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_2_ip_wrapper.vhd
+ src/vhdl/ipcore2rtl_hwn_nd_3_ip_wrapper.vhd
+ src/vhdl/ipcore2rtl_register_rf_ip_wrapper.vhd
+
+test_bench_files =
+ src/vhdl/system_ext_TB.vhd
diff --git a/applications/compaan/libraries/vhdl_altera/isim_timeline.tcl b/applications/compaan/libraries/vhdl_altera/isim_timeline.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c1ef7843c629162d8467c448bca7761f07035c43
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/isim_timeline.tcl
@@ -0,0 +1,11 @@
+add wave -divider FIFO
+wave add SUT/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/EX/FUNC/CTRL/read
+wave add SUT/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe
+wave add SUT/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/EX/FUNC/CTRL/write
+wave add SUT/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/EX/FUNC/CTRL/read
+wave add SUT/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe
+wave add SUT/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/EX/FUNC/CTRL/write
+wave add SUT/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/EX/FUNC/CTRL/read
+wave add SUT/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe
+wave add SUT/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/EX/FUNC/CTRL/write
+add wave -divider FIFO
diff --git a/applications/compaan/libraries/vhdl_altera/isim_wave.tcl b/applications/compaan/libraries/vhdl_altera/isim_wave.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e58066e9cc5e4d06f2890c9a6af7ab500bf27d6d
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/isim_wave.tcl
@@ -0,0 +1,4 @@
+add wave -divider FIFO_BEGIN
+add wave -position end -radix unsigned -label ed_1 sim:/system_ext_tb/SUT/ipcore2rtl_ed_1/FSL_S_Data
+add wave -position end -radix unsigned -label ed_2 sim:/system_ext_tb/SUT/ipcore2rtl_ed_2/FSL_S_Data
+add wave -divider FIFO_END
diff --git a/applications/compaan/libraries/vhdl_altera/modelsim_hier_timeline.tcl b/applications/compaan/libraries/vhdl_altera/modelsim_hier_timeline.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b3e07adff789eccc2c02497cd87d3b5040a494d0
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/modelsim_hier_timeline.tcl
@@ -0,0 +1,5 @@
+divider add TIMELINE -color darkgreen
+wave add SUT/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:ipcore2rtl:hwn_nd_1:1
+wave add SUT/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:ipcore2rtl:hwn_nd_2:1
+wave add SUT/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:ipcore2rtl:hwn_nd_3:1
+divider add TIMELINE -color darkgreen
diff --git a/applications/compaan/libraries/vhdl_altera/modelsim_system.do b/applications/compaan/libraries/vhdl_altera/modelsim_system.do
new file mode 100644
index 0000000000000000000000000000000000000000..624f9040b8c4a39e65c5bc81d7dba8ee612080e2
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/modelsim_system.do
@@ -0,0 +1,251 @@
+transcript on
+
+onerror {quit -f}
+onbreak {quit -f}
+config wave -signalnamewidth 1
+
+if {[file exists work]} {
+ vdel -lib work -all
+}
+vlib work
+vmap work work
+
+if {[file exists technology_lib]} {
+ vdel -lib technology_lib -all
+}
+vlib technology_lib
+vmap work technology_lib
+
+if {[file exists common_lib]} {
+ vdel -lib common_lib -all
+}
+vlib common_lib
+vmap work common_lib
+
+if {[file exists tech_memory_lib]} {
+ vdel -lib tech_memory_lib -all
+}
+vlib tech_memory_lib
+vmap work tech_memory_lib
+
+if {[file exists ip_stratixiv_fifo_lib]} {
+ vdel -lib ip_stratixiv_fifo_lib -all
+}
+vlib ip_stratixiv_fifo_lib
+vmap work ip_stratixiv_fifo_lib
+
+if {[file exists ip_stratixiv_ram_lib]} {
+ vdel -lib ip_stratixiv_ram_lib -all
+}
+vlib ip_stratixiv_ram_lib
+vmap work ip_stratixiv_ram_lib
+
+if {[file exists ip_arria10_ram_lib]} {
+ vdel -lib ip_arria10_ram_lib -all
+}
+vlib ip_arria10_ram_lib
+vmap work ip_arria10_ram_lib
+
+if {[file exists ip_arria10_fifo_lib]} {
+ vdel -lib ip_arria10_fifo_lib -all
+}
+vlib ip_arria10_fifo_lib
+vmap work ip_arria10_fifo_lib
+
+if {[file exists tech_fifo_lib]} {
+ vdel -lib tech_fifo_lib -all
+}
+vlib tech_fifo_lib
+vmap work tech_fifo_lib
+
+if {[file exists dp_lib]} {
+ vdel -lib dp_lib -all
+}
+vlib dp_lib
+vmap work dp_lib
+
+
+set SVNROOT null
+set RadioHDL ${SVNROOT}/RadioHDL/trunk
+set UniBoard ${SVNROOT}/UniBoard/trunk
+
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_pkg.vhd
+vcom -93 -work work ${UniBoard}/Firmware/modules/common/src/vhdl/common_pkg.vhd
+vcom -93 -work work ${RadioHDL}/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+vcom -93 -work work ${RadioHDL}/libraries/technology/technology_pkg.vhd
+vcom -93 -work technology_lib ${RadioHDL}/libraries/technology/technology_pkg.vhd
+vcom -93 -work work ${RadioHDL}/libraries/technology/technology_select_pkg.vhd
+vcom -93 -work technology_lib ${RadioHDL}/libraries/technology/technology_select_pkg.vhd
+
+vcom -93 -work ip_arria10_fifo_lib ${RadioHDL}/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
+
+vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_dc.vhd
+vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_sc.vhd
+vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_dc_mixed_widths.vhd
+
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_dc.vhd
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_sc.vhd
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_async.vhd
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_areset.vhd
+
+vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+vcom -93 -work dp_lib ${UniBoard}/Firmware/modules/dp/src/vhdl/dp_latency_increase.vhd
+vcom -93 -work dp_lib ${UniBoard}/Firmware/modules/dp/src/vhdl/dp_latency_adapter.vhd
+
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_fifo_sc.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_fifo_dc.vhd
+vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_async.vhd
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_pipeline.vhd
+
+vcom -93 -work ip_stratixiv_ram_lib ${RadioHDL}/libraries/technology/ip_stratixiv/ram/ip_stratixiv_ram_crw_crw.vhd
+vcom -93 -work ip_stratixiv_ram_lib ${RadioHDL}/libraries/technology/ip_stratixiv/ram/ip_stratixiv_ram_cr_cw.vhd
+
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_dual_clock.vhd
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_true_dual_port_ram_dual_clock.vhd
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
+
+vcom -93 -work tech_memory_lib ${RadioHDL}/libraries/technology/memory/tech_memory_component_pkg.vhd
+vcom -93 -work tech_memory_lib ${RadioHDL}/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+vcom -93 -work tech_memory_lib ${RadioHDL}/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_ram_r_w.vhd
+
+# -- Compaan Specific
+if {[file exists compaandesign_com_common_common_1_lib]} {
+ vdel -lib compaandesign_com_common_common_1_lib -all
+}
+vlib compaandesign_com_common_common_1_lib
+vmap work compaandesign_com_common_common_1_lib
+
+vcom -93 -work compaandesign_com_common_common_1_lib {compaandesign_com/common/common/src/vhdl/hw_node_pkg.vhd}
+
+if {[file exists compaandesign_com_common_const_connector_1_lib]} {
+ vdel -lib compaandesign_com_common_const_connector_1_lib -all
+}
+vlib compaandesign_com_common_const_connector_1_lib
+vmap work compaandesign_com_common_const_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_const_connector_1_lib {compaandesign_com/common/const_connector/src/vhdl/const_connector.vhd}
+
+if {[file exists compaandesign_com_common_altera_1_lib]} {
+ vdel -lib compaandesign_com_common_altera_1_lib -all
+}
+vlib compaandesign_com_common_altera_1_lib
+vmap work compaandesign_com_common_altera_1_lib
+
+vcom -93 -work compaandesign_com_common_altera_1_lib {compaandesign_com/common/altera/src/vhdl/fsl_v20.vhd}
+
+if {[file exists compaandesign_com_common_extern_connector_1_lib]} {
+ vdel -lib compaandesign_com_common_extern_connector_1_lib -all
+}
+vlib compaandesign_com_common_extern_connector_1_lib
+vmap work compaandesign_com_common_extern_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_extern_connector_1_lib {compaandesign_com/common/extern_connector/src/vhdl/extern_connector.vhd}
+
+if {[file exists compaandesign_com_common_hwnode_1_lib]} {
+ vdel -lib compaandesign_com_common_hwnode_1_lib -all
+}
+vlib compaandesign_com_common_hwnode_1_lib
+vmap work compaandesign_com_common_hwnode_1_lib
+
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/controller.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/counter.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/it_mod.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/it_mul.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/parameters.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/read_mmux.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/write_demux.vhd}
+
+if {[file exists compaandesign_com_common_wire_connector_1_lib]} {
+ vdel -lib compaandesign_com_common_wire_connector_1_lib -all
+}
+vlib compaandesign_com_common_wire_connector_1_lib
+vmap work compaandesign_com_common_wire_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_wire_connector_1_lib {compaandesign_com/common/wire_connector/src/vhdl/wire_connector.vhd}
+
+if {[file exists compaandesign_com_ipcore2rtl_functions_1_lib]} {
+ vdel -lib compaandesign_com_ipcore2rtl_functions_1_lib -all
+}
+vlib compaandesign_com_ipcore2rtl_functions_1_lib
+vmap work compaandesign_com_ipcore2rtl_functions_1_lib
+
+vcom -93 -work compaandesign_com_ipcore2rtl_functions_1_lib {compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_functions_1_lib {compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_functions_1_lib {compaandesign_com/ipcore2rtl/functions/src/vhdl/transformer.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_functions_1_lib {compaandesign_com/ipcore2rtl/functions/src/vhdl/transformer_pipeline.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_functions_1_lib {compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc1.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_functions_1_lib {compaandesign_com/ipcore2rtl/functions/src/vhdl/compaan_outlinedproc1_pipeline.vhd}
+
+if {[file exists compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib]} {
+ vdel -lib compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib -all
+}
+vlib compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib
+vmap work compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib
+
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_execution_unit.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_1/src/vhdl/ipcore2rtl_hwn_nd_1.vhd}
+
+if {[file exists compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib]} {
+ vdel -lib compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib -all
+}
+vlib compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib
+vmap work compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib
+
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_execution_unit.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_2/src/vhdl/ipcore2rtl_hwn_nd_2.vhd}
+
+if {[file exists compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib]} {
+ vdel -lib compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib -all
+}
+vlib compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib
+vmap work compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib
+
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_execution_unit.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib {compaandesign_com/ipcore2rtl/hwn_nd_3/src/vhdl/ipcore2rtl_hwn_nd_3.vhd}
+
+if {[file exists compaandesign_com_ipcore2rtl_register_rf_1_lib]} {
+ vdel -lib compaandesign_com_ipcore2rtl_register_rf_1_lib -all
+}
+vlib compaandesign_com_ipcore2rtl_register_rf_1_lib
+vmap work compaandesign_com_ipcore2rtl_register_rf_1_lib
+
+vcom -93 -work compaandesign_com_ipcore2rtl_register_rf_1_lib {compaandesign_com/ipcore2rtl/register_rf/src/vhdl/register_rf.vhd}
+
+
+
+
+vcom -93 -work work src/vhdl/ipcore.vhd
+vcom -93 -work work src/vhdl/ipcore2rtl_ed_1_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/ipcore2rtl_ed_2_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/ipcore2rtl_hwn_nd_1_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/ipcore2rtl_hwn_nd_2_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/ipcore2rtl_hwn_nd_3_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/ipcore2rtl_register_rf_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/system_ext_TB.vhd
+
+vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L stratixiv_hssi -L ip_stratixiv_ram_lib -L stratixiv_pcie_hip -L stratixiv -L common_lib -L tech_memory_lib -L ip_stratixiv_fifo_lib -L tech_fifo_lib -L dp_lib -L technology_lib -L rtl_work -L work -L compaandesign_com_common_wire_connector_1_lib -L compaandesign_com_ipcore2rtl_functions_1_lib -L compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib -L compaandesign_com_common_const_connector_1_lib -L compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib -L compaandesign_com_common_hwnode_1_lib -L compaandesign_com_ipcore2rtl_register_rf_1_lib -L compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib -L compaandesign_com_common_common_1_lib -L compaandesign_com_common_extern_connector_1_lib -L compaandesign_com_common_altera_1_lib -voptargs="+acc" system_ext_TB
+#add wave *
+#view structure
+#view signals
+#source isim_wave.tcl
+run -all
+quit -f
+
diff --git a/applications/compaan/libraries/vhdl_altera/run_quartus.tcl b/applications/compaan/libraries/vhdl_altera/run_quartus.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6e54813291349e91a73a4b9eea90b8965e849c78
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/run_quartus.tcl
@@ -0,0 +1,88 @@
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+ if {[string compare $quartus(project) "ipcore"]} {
+ puts "Project ipcore is not open"
+ set make_assignments 0
+}
+} else {
+ # Only open if not already open
+ if {[project_exists ipcore]} {
+ project_open -revision ipcore ipcore
+ } else {
+ project_new -revision ipcore ipcore
+ }
+}
+set need_to_close_project 1
+
+# Make assignments
+if {$make_assignments} {
+ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
+ set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:41:26 JANUARY 22, 2015"
+ set_global_assignment -name LAST_QUARTUS_VERSION 12.0
+ set_global_assignment -name FAMILY "Stratix V"
+ set_global_assignment -name TOP_LEVEL_ENTITY ipcore
+ set_global_assignment -name DEVICE auto
+ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/write_demux.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/read_mux.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/read_mmux.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/parameters.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/it_mul.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/it_mod.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/counter.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/controller.vhd -library compaandesign_com_common_hwnode_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/altera/1/fsl_v20.vhd -library compaandesign_com_common_fifo_1
+ set_global_assignment -name VHDL_FILE compaandesign_com/common/common/1/hw_node_pkg.vhd -library compaandesign_com_common_common_1
+
+
+ set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2rtl/hwn_nd_1/1/sourceCode -library compaandesign_com_ipcore2rtl_hwn_nd_1_1
+
+ set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2rtl/hwn_nd_2/1/sourceCode -library compaandesign_com_ipcore2rtl_hwn_nd_2_1
+
+ set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2rtl/hwn_nd_3/1/sourceCode -library compaandesign_com_ipcore2rtl_hwn_nd_3_1
+
+ set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2rtl/register_rf/1/sourceCode -library compaandesign_com_ipcore2rtl_register_rf_1
+
+
+# add functions of Laura node into a library
+
+ set strlist [glob compaandesign_com/ipcore2rtl/functions/1/*.vhd]
+ foreach strfile $strlist {
+ set file_name $strfile
+ set_global_assignment -name VHDL_FILE $file_name -library compaandesign_com_ipcore2rtl_functions_1
+ }
+
+
+# add wrapper to library work
+ set strlist [glob *.vhd]
+ foreach strfile $strlist {
+ set file_name $strfile
+ set_global_assignment -name VHDL_FILE $file_name -library work
+ }
+
+# testbench information
+set_global_assignment -name VHDL_FILE system_ext_TB.vhd -library work
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH ipcore -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME ipcore -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME ipcore -section_id ipcore
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ipcore -section_id ipcore
+set_global_assignment -name EDA_TEST_BENCH_FILE system_ext_TB.vhd -section_id ipcore -library work
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+# Commit assignments
+export_assignments
+
+# Close project
+if {$need_to_close_project} {
+ project_close
+}
+}
diff --git a/applications/compaan/libraries/src/vhdl/ipcore.vhd b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore.vhd
similarity index 80%
rename from applications/compaan/libraries/src/vhdl/ipcore.vhd
rename to applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore.vhd
index 2ab280cb3c1df0a8c4c5ad5a9a04231c67f9268e..fff2c5a6e35ab5e3509b4269ba1af56c5b21c1ab 100644
--- a/applications/compaan/libraries/src/vhdl/ipcore.vhd
+++ b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore.vhd
@@ -1,440 +1,402 @@
--------------------------------------------------------------------------------
--- TOP LEVEL
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity ipcore is
- port (
-
- data_in_Data : in std_logic_vector(31 downto 0 );
- data_in_Control : in std_logic;
- data_in_Read : out std_logic;
- data_in_Exists : in std_logic;
-
- data_out_Data : out std_logic_vector(31 downto 0 );
- data_out_Control : out std_logic;
- data_out_Write : out std_logic;
- data_out_Full : in std_logic;
-
- TEST_STOP : out std_logic_vector(2 downto 0 );
- TEST_ERROR : out std_logic_vector(2 downto 0 );
- TEST_FIFO_FULL : out std_logic_vector(1 downto 0 );
- TEST_BLOCK_RD : out std_logic_vector(2 downto 0 );
- address : in std_logic_vector(18 downto 0 );
- read_data : out std_logic_vector(31 downto 0 );
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0 );
-
- MM_CLK : in std_logic;
- MM_RST : in std_logic;
- KPN_CLK : in std_logic;
- KPN_RST : in std_logic
- );
-end ipcore;
-
-architecture STRUCTURE of ipcore is
-
- component ipcore2RTL_hwn_nd_1_ip_wrapper is
- port (
- data_in_Rd : out std_logic;
- data_in_Din : in std_logic_vector(31 downto 0);
- data_in_Exist : in std_logic;
- data_in_CLK : out std_logic;
- data_in_CTRL : in std_logic;
-
- ND_1OP_1_Wr : out std_logic;
- ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_Full : in std_logic;
- ND_1OP_1_CLK : out std_logic;
- ND_1OP_1_CTRL : out std_logic;
-
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
-
- RST : in std_logic;
- CLK : in std_logic
- );
- end component;
-
- component ipcore2RTL_hwn_nd_2_ip_wrapper is
- port (
- ND_2IP_1_Rd : out std_logic;
- ND_2IP_1_Din : in std_logic_vector(31 downto 0);
- ND_2IP_1_Exist : in std_logic;
- ND_2IP_1_CLK : out std_logic;
- ND_2IP_1_CTRL : in std_logic;
-
- ND_2OP_1_Wr : out std_logic;
- ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_Full : in std_logic;
- ND_2OP_1_CLK : out std_logic;
- ND_2OP_1_CTRL : out std_logic;
-
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
-
- RST : in std_logic;
- CLK : in std_logic
- );
- end component;
-
- component ipcore2RTL_hwn_nd_3_ip_wrapper is
- port (
- ND_3IP_2_Rd : out std_logic;
- ND_3IP_2_Din : in std_logic_vector(31 downto 0);
- ND_3IP_2_Exist : in std_logic;
- ND_3IP_2_CLK : out std_logic;
- ND_3IP_2_CTRL : in std_logic;
-
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
-
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
-
- RST : in std_logic;
- CLK : in std_logic
- );
- end component;
-
-component ipcore2RTL_control_if_ip_wrapper is
- port (
- PARAM_DT : out std_logic_vector(31 downto 0);
- PARAM_LD : out std_logic;
- PARAMETERS_IN : in std_logic_vector(31 downto 0);
- PARAMETERS_IN_LD : in std_logic;
- RST : in std_logic;
- CLK : in std_logic
-
- );
-end component;
-
-component ipcore2RTL_register_rf_ip_wrapper is
- port (
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0);
- reg_rf_read_data : in std_logic_vector(32-1 downto 0);
- reg_rf_read_en : out std_logic;
- reg_rf_write_en : out std_logic;
- reg_rf_write_data : out std_logic_vector(32-1 downto 0);
- RST : in std_logic;
- CLK : in std_logic
-
- );
-end component;
-
- component ipcore2RTL_ed_1_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
- component ipcore2RTL_ed_2_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
- -- Internal signals
-
- signal signal_ed_1_out_FSL_M_Control : std_logic;
- signal signal_ed_1_out_FSL_M_Data : std_logic_vector(0 to 31);
- signal signal_ed_1_out_FSL_M_Full : std_logic;
- signal signal_ed_1_out_FSL_M_Write : std_logic;
- signal signal_ed_1_in_FSL_S_Control : std_logic;
- signal signal_ed_1_in_FSL_S_Data : std_logic_vector(0 to 31);
- signal signal_ed_1_in_FSL_S_Exists : std_logic;
- signal signal_ed_1_in_FSL_S_Read : std_logic;
- signal signal_ed_2_out_FSL_M_Control : std_logic;
- signal signal_ed_2_out_FSL_M_Data : std_logic_vector(0 to 31);
- signal signal_ed_2_out_FSL_M_Full : std_logic;
- signal signal_ed_2_out_FSL_M_Write : std_logic;
- signal signal_ed_2_in_FSL_S_Control : std_logic;
- signal signal_ed_2_in_FSL_S_Data : std_logic_vector(0 to 31);
- signal signal_ed_2_in_FSL_S_Exists : std_logic;
- signal signal_ed_2_in_FSL_S_Read : std_logic;
-
- -- AD HOC Internal signals
-
- signal signal_hwn_nd_1_STOP : std_logic;
- signal signal_hwn_nd_1_ERROR : std_logic;
- signal signal_hwn_nd_1_BLOCK_RD : std_logic;
- signal signal_hwn_nd_2_STOP : std_logic;
- signal signal_hwn_nd_2_ERROR : std_logic;
- signal signal_hwn_nd_2_BLOCK_RD : std_logic;
- signal signal_hwn_nd_3_STOP : std_logic;
- signal signal_hwn_nd_3_ERROR : std_logic;
- signal signal_hwn_nd_3_BLOCK_RD : std_logic;
- signal signal_ed_1_FIFO_FULL : std_logic;
- signal signal_ed_2_FIFO_FULL : std_logic;
- signal signal_PARAM_DT : std_logic_vector(31 downto 0);
- signal signal_PARAM_LD : std_logic;
- signal signal_PARAMETERS : std_logic_vector(31 downto 0);
- signal signal_PARAMETERS_LD : std_logic;
- signal signal_address : std_logic_vector(18 downto 0);
- signal signal_read_data : std_logic_vector(31 downto 0);
- signal signal_write_data : std_logic_vector(31 downto 0);
- signal signal_read_en : std_logic;
- signal signal_write_en : std_logic;
-
- -- Hierarchical signals
-
- signal I_data_in_Control : std_logic;
- signal I_data_in_Data : std_logic_vector(31 downto 0);
- signal I_data_in_Exists : std_logic;
- signal I_data_in_Read : std_logic;
- signal I_data_out_Control : std_logic;
- signal I_data_out_Data : std_logic_vector(31 downto 0);
- signal I_data_out_Full : std_logic;
- signal I_data_out_Write : std_logic;
-
- -- Default signals
-
- signal net_gnd0 : std_logic;
- signal net_gnd16 : std_logic_vector(15 downto 0);
-
- signal sys_clk_s : std_logic;
- signal sys_rst_s : std_logic;
-
- signal mm_clk_s : std_logic;
- signal mm_rst_s : std_logic;
-
- signal snc_state : std_logic;
- signal snc_cnt : natural;
-
- signal signal_reg_rf_read_data : std_logic_vector(31 downto 0);
- signal signal_reg_rf_read_en : std_logic;
- signal signal_reg_rf_write_en : std_logic;
- signal signal_reg_rf_write_data : std_logic_vector(31 downto 0);
-
- -- START the actual definition of a Design
-
-begin
-
- -- Connect Clock
-
- sys_clk_s <= KPN_CLK;
- sys_rst_s <= KPN_RST;
-
- mm_clk_s <= MM_CLK;
- mm_rst_s <= MM_RST;
-
- -- Connect parameters
- signal_PARAMETERS <= signal_reg_rf_write_data;
- signal_PARAMETERS_LD <= signal_reg_rf_write_en;
-
- -- Connect Hiercical Interconnections
-
- -- Hierarchical signals -3- compaandesign.com:ipcore2RTL:design_ipcore:1:data_in
- I_data_in_Data <= data_in_Data;
- I_data_in_Control <= data_in_Control;
- data_in_Read <= I_data_in_Read;
- I_data_in_Exists <= data_in_Exists;
- -- Hierarchical signals -3- compaandesign.com:ipcore2RTL:design_ipcore:1:data_out
- data_out_Data <= I_data_out_Data;
- data_out_Control <= I_data_out_Control;
- data_out_Write <= I_data_out_Write;
- I_data_out_Full <= data_out_Full;
-
- -- AD HOC EXTERNAL CONNECTIONS
- -- DESIGN ID : compaandesign.com:ipcore2RTL:design_ipcore:1
- TEST_STOP(0) <= signal_hwn_nd_1_STOP;
- TEST_ERROR(0) <= signal_hwn_nd_1_ERROR;
- TEST_BLOCK_RD(0) <= signal_hwn_nd_1_BLOCK_RD;
- TEST_STOP(1) <= signal_hwn_nd_2_STOP;
- TEST_ERROR(1) <= signal_hwn_nd_2_ERROR;
- TEST_BLOCK_RD(1) <= signal_hwn_nd_2_BLOCK_RD;
- TEST_STOP(2) <= signal_hwn_nd_3_STOP;
- TEST_ERROR(2) <= signal_hwn_nd_3_ERROR;
- TEST_BLOCK_RD(2) <= signal_hwn_nd_3_BLOCK_RD;
- TEST_FIFO_FULL(0) <= signal_ed_1_FIFO_FULL;
- TEST_FIFO_FULL(1) <= signal_ed_2_FIFO_FULL;
- signal_address <= address( 18 downto 0);
- read_data( 31 downto 0) <= signal_read_data;
- signal_write_data <= write_data( 31 downto 0);
- signal_read_en <= read_en;
- signal_write_en <= write_en;
-
--- Give default signals, default values
-
- net_gnd0 <= '0';
- net_gnd16(15 downto 0) <= B"0000000000000000";
-
--- Instanciate the wrappers (HWN and Edges)
-
- ipcore2RTL_hwn_nd_1_ip : ipcore2RTL_hwn_nd_1_ip_wrapper
- port map (
- data_in_Rd => I_data_in_Read,
- data_in_Din => I_data_in_Data(31 downto 0),
- data_in_Exist => I_data_in_Exists,
- data_in_CLK => open,
- data_in_CTRL => I_data_in_Control,
- ND_1OP_1_Wr => signal_ed_1_out_FSL_M_Write,
- ND_1OP_1_Dout(31 downto 0) => signal_ed_1_out_FSL_M_Data(0 to 31),
- ND_1OP_1_Full => signal_ed_1_out_FSL_M_Full,
- ND_1OP_1_CLK => open,
- ND_1OP_1_CTRL => signal_ed_1_out_FSL_M_Control,
- PARAM_DT => signal_PARAM_DT,
- PARAM_LD => signal_PARAM_LD,
- STOP => signal_hwn_nd_1_STOP,
- ERROR => signal_hwn_nd_1_ERROR,
- BLOCK_RD => signal_hwn_nd_1_BLOCK_RD,
- RST => sys_rst_s,
- CLK => sys_clk_s
- );
-
- ipcore2RTL_hwn_nd_2_ip : ipcore2RTL_hwn_nd_2_ip_wrapper
- port map (
- ND_2IP_1_Rd => signal_ed_1_in_FSL_S_Read,
- ND_2IP_1_Din(31 downto 0) => signal_ed_1_in_FSL_S_Data(0 to 31),
- ND_2IP_1_Exist => signal_ed_1_in_FSL_S_Exists,
- ND_2IP_1_CLK => open,
- ND_2IP_1_CTRL => signal_ed_1_in_FSL_S_Control,
- ND_2OP_1_Wr => signal_ed_2_out_FSL_M_Write,
- ND_2OP_1_Dout(31 downto 0) => signal_ed_2_out_FSL_M_Data(0 to 31),
- ND_2OP_1_Full => signal_ed_2_out_FSL_M_Full,
- ND_2OP_1_CLK => open,
- ND_2OP_1_CTRL => signal_ed_2_out_FSL_M_Control,
- PARAM_DT => signal_PARAM_DT,
- PARAM_LD => signal_PARAM_LD,
- STOP => signal_hwn_nd_2_STOP,
- ERROR => signal_hwn_nd_2_ERROR,
- BLOCK_RD => signal_hwn_nd_2_BLOCK_RD,
- RST => sys_rst_s,
- CLK => sys_clk_s
- );
-
- ipcore2RTL_hwn_nd_3_ip : ipcore2RTL_hwn_nd_3_ip_wrapper
- port map (
- ND_3IP_2_Rd => signal_ed_2_in_FSL_S_Read,
- ND_3IP_2_Din(31 downto 0) => signal_ed_2_in_FSL_S_Data(0 to 31),
- ND_3IP_2_Exist => signal_ed_2_in_FSL_S_Exists,
- ND_3IP_2_CLK => open,
- ND_3IP_2_CTRL => signal_ed_2_in_FSL_S_Control,
- data_out_Wr => I_data_out_Write,
- data_out_Dout => I_data_out_Data(31 downto 0),
- data_out_Full => I_data_out_Full,
- data_out_CLK => open,
- data_out_CTRL => I_data_out_Control,
- PARAM_DT => signal_PARAM_DT,
- PARAM_LD => signal_PARAM_LD,
- STOP => signal_hwn_nd_3_STOP,
- ERROR => signal_hwn_nd_3_ERROR,
- BLOCK_RD => signal_hwn_nd_3_BLOCK_RD,
- RST => sys_rst_s,
- CLK => sys_clk_s
- );
-
- ipcore2RTL_control_if_ip : ipcore2RTL_control_if_ip_wrapper
- port map (
- PARAM_DT => signal_PARAM_DT,
- PARAM_LD => signal_PARAM_LD,
- PARAMETERS_IN => signal_PARAMETERS,
- PARAMETERS_IN_LD => signal_PARAMETERS_LD,
- RST => mm_rst_s,
- CLK => mm_clk_s
- );
-
- ipcore2RTL_register_rf_ip : ipcore2RTL_register_rf_ip_wrapper
- port map (
- address => signal_address,
- read_data => signal_read_data,
- read_en => signal_read_en,
- write_en => signal_write_en,
- write_data => signal_write_data,
- reg_rf_read_data => signal_reg_rf_read_data,
- reg_rf_read_en => signal_reg_rf_read_en,
- reg_rf_write_en => signal_reg_rf_write_en,
- reg_rf_write_data => signal_reg_rf_write_data,
- RST => mm_rst_s,
- CLK => mm_clk_s
- );
-
- ipcore2RTL_ed_1 : ipcore2RTL_ed_1_ip_wrapper
- port map (
- FSL_Clk => sys_clk_s,
- SYS_Rst => sys_rst_s,
- FSL_Rst => open,
- FSL_M_Clk => net_gnd0,
- FSL_M_Data => signal_ed_1_out_FSL_M_Data,
- FSL_M_Control => signal_ed_1_out_FSL_M_Control,
- FSL_M_Write => signal_ed_1_out_FSL_M_Write,
- FSL_M_Full => signal_ed_1_out_FSL_M_Full,
- FSL_S_Data => signal_ed_1_in_FSL_S_Data,
- FSL_S_Control => signal_ed_1_in_FSL_S_Control,
- FSL_S_Read => signal_ed_1_in_FSL_S_Read,
- FSL_S_Exists => signal_ed_1_in_FSL_S_Exists,
- FSL_S_Clk => net_gnd0,
- FSL_FULL => signal_ed_1_FIFO_FULL,
- FSL_Has_Data => open,
- FSL_Control_IRQ => open
- );
-
- ipcore2RTL_ed_2 : ipcore2RTL_ed_2_ip_wrapper
- port map (
- FSL_Clk => sys_clk_s,
- SYS_Rst => sys_rst_s,
- FSL_Rst => open,
- FSL_M_Clk => net_gnd0,
- FSL_M_Data => signal_ed_2_out_FSL_M_Data,
- FSL_M_Control => signal_ed_2_out_FSL_M_Control,
- FSL_M_Write => signal_ed_2_out_FSL_M_Write,
- FSL_M_Full => signal_ed_2_out_FSL_M_Full,
- FSL_S_Data => signal_ed_2_in_FSL_S_Data,
- FSL_S_Control => signal_ed_2_in_FSL_S_Control,
- FSL_S_Read => signal_ed_2_in_FSL_S_Read,
- FSL_S_Exists => signal_ed_2_in_FSL_S_Exists,
- FSL_S_Clk => net_gnd0,
- FSL_FULL => signal_ed_2_FIFO_FULL,
- FSL_Has_Data => open,
- FSL_Control_IRQ => open
- );
-
-end architecture STRUCTURE;
+-------------------------------------------------------------------------------
+-- TOP LEVEL
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity ipcore is
+ port (
+
+ data_in_Data : in std_logic_vector(31 downto 0 );
+ data_in_Control : in std_logic;
+ data_in_Read : out std_logic;
+ data_in_Exists : in std_logic;
+
+ data_out_Data : out std_logic_vector(31 downto 0 );
+ data_out_Control : out std_logic;
+ data_out_Write : out std_logic;
+ data_out_Full : in std_logic;
+
+ TEST_STOP : out std_logic_vector(2 downto 0 );
+ TEST_ERROR : out std_logic_vector(2 downto 0 );
+ TEST_FIFO_FULL : out std_logic_vector(1 downto 0 );
+ TEST_BLOCK_RD : out std_logic_vector(2 downto 0 );
+ address : in std_logic_vector(18 downto 0 );
+ read_data : out std_logic_vector(31 downto 0 );
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0 );
+ pci_clk : in std_logic;
+
+ KPN_CLK : in std_logic;
+ KPN_RST : in std_logic
+ );
+end ipcore;
+
+architecture STRUCTURE of ipcore is
+
+ component ipcore2rtl_hwn_nd_1_ip_wrapper is
+ port (
+ data_in_Rd : out std_logic;
+ data_in_Din : in std_logic_vector(31 downto 0);
+ data_in_Exist : in std_logic;
+ data_in_CLK : out std_logic;
+ data_in_CTRL : in std_logic;
+
+ ND_1OP_1_Wr : out std_logic;
+ ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
+ ND_1OP_1_Full : in std_logic;
+ ND_1OP_1_CLK : out std_logic;
+ ND_1OP_1_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+ end component;
+
+ component ipcore2rtl_hwn_nd_2_ip_wrapper is
+ port (
+ ND_2IP_1_Rd : out std_logic;
+ ND_2IP_1_Din : in std_logic_vector(31 downto 0);
+ ND_2IP_1_Exist : in std_logic;
+ ND_2IP_1_CLK : out std_logic;
+ ND_2IP_1_CTRL : in std_logic;
+
+ ND_2OP_1_Wr : out std_logic;
+ ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
+ ND_2OP_1_Full : in std_logic;
+ ND_2OP_1_CLK : out std_logic;
+ ND_2OP_1_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+ end component;
+
+ component ipcore2rtl_hwn_nd_3_ip_wrapper is
+ port (
+ ND_3IP_2_Rd : out std_logic;
+ ND_3IP_2_Din : in std_logic_vector(31 downto 0);
+ ND_3IP_2_Exist : in std_logic;
+ ND_3IP_2_CLK : out std_logic;
+ ND_3IP_2_CTRL : in std_logic;
+
+ data_out_Wr : out std_logic;
+ data_out_Dout : out std_logic_vector(31 downto 0);
+ data_out_Full : in std_logic;
+ data_out_CLK : out std_logic;
+ data_out_CTRL : out std_logic;
+
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+ end component;
+
+component ipcore2rtl_register_rf_ip_wrapper is
+ port (
+ address : in std_logic_vector(18 downto 0);
+ read_data : out std_logic_vector(31 downto 0);
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0);
+ pci_clk : in std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+
+ );
+end component;
+
+ component ipcore2rtl_ed_1_ip_wrapper is
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 31);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 31);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+ end component;
+
+ component ipcore2rtl_ed_2_ip_wrapper is
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 31);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 31);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+ end component;
+
+ -- Internal signals
+
+ signal signal_ed_1_out_FSL_M_Control : std_logic;
+ signal signal_ed_1_out_FSL_M_Data : std_logic_vector(0 to 31);
+ signal signal_ed_1_out_FSL_M_Full : std_logic;
+ signal signal_ed_1_out_FSL_M_Write : std_logic;
+ signal signal_ed_1_in_FSL_S_Control : std_logic;
+ signal signal_ed_1_in_FSL_S_Data : std_logic_vector(0 to 31);
+ signal signal_ed_1_in_FSL_S_Exists : std_logic;
+ signal signal_ed_1_in_FSL_S_Read : std_logic;
+ signal signal_ed_2_out_FSL_M_Control : std_logic;
+ signal signal_ed_2_out_FSL_M_Data : std_logic_vector(0 to 31);
+ signal signal_ed_2_out_FSL_M_Full : std_logic;
+ signal signal_ed_2_out_FSL_M_Write : std_logic;
+ signal signal_ed_2_in_FSL_S_Control : std_logic;
+ signal signal_ed_2_in_FSL_S_Data : std_logic_vector(0 to 31);
+ signal signal_ed_2_in_FSL_S_Exists : std_logic;
+ signal signal_ed_2_in_FSL_S_Read : std_logic;
+
+ -- AD HOC Internal signals
+
+ signal signal_hwn_nd_1_STOP : std_logic;
+ signal signal_hwn_nd_1_ERROR : std_logic;
+ signal signal_hwn_nd_1_BLOCK_RD : std_logic;
+ signal signal_hwn_nd_2_STOP : std_logic;
+ signal signal_hwn_nd_2_ERROR : std_logic;
+ signal signal_hwn_nd_2_BLOCK_RD : std_logic;
+ signal signal_hwn_nd_3_STOP : std_logic;
+ signal signal_hwn_nd_3_ERROR : std_logic;
+ signal signal_hwn_nd_3_BLOCK_RD : std_logic;
+ signal signal_ed_1_FIFO_FULL : std_logic;
+ signal signal_ed_2_FIFO_FULL : std_logic;
+ signal signal_PARAM_DT : std_logic_vector(10 downto 0);
+ signal signal_PARAM_LD : std_logic;
+ signal signal_PARAMETERS : std_logic_vector(0 downto 0);
+ signal signal_PARAMETERS_LD : std_logic;
+ signal signal_address : std_logic_vector(18 downto 0);
+ signal signal_read_data : std_logic_vector(31 downto 0);
+ signal signal_write_data : std_logic_vector(31 downto 0);
+ signal signal_read_en : std_logic;
+ signal signal_write_en : std_logic;
+ signal signal_param_ext_pci_clk : std_logic;
+ signal signal_register_rf_pci_clk : std_logic;
+ signal signal_SYNC_NUM : std_logic_vector(9 downto 0);
+
+ -- Hierarchical signals
+
+ signal I_data_in_Control : std_logic;
+ signal I_data_in_Data : std_logic_vector(31 downto 0);
+ signal I_data_in_Exists : std_logic;
+ signal I_data_in_Read : std_logic;
+ signal I_data_out_Control : std_logic;
+ signal I_data_out_Data : std_logic_vector(31 downto 0);
+ signal I_data_out_Full : std_logic;
+ signal I_data_out_Write : std_logic;
+
+ -- Default signals
+
+ signal net_gnd0 : std_logic;
+ signal net_gnd16 : std_logic_vector(15 downto 0);
+
+ signal sys_clk_s : std_logic;
+ signal sys_rst_s : std_logic;
+
+
+ -- START the actual definition of a Design
+
+begin
+
+ -- Connect Clock
+
+ sys_clk_s <= KPN_CLK;
+ sys_rst_s <= KPN_RST;
+
+
+ -- Connect Hiercical Interconnections
+
+ -- Hierarchical signals -3- compaandesign.com:ipcore2rtl:design_ipcore:1:data_in
+ I_data_in_Data <= data_in_Data;
+ I_data_in_Control <= data_in_Control;
+ data_in_Read <= I_data_in_Read;
+ I_data_in_Exists <= data_in_Exists;
+ -- Hierarchical signals -3- compaandesign.com:ipcore2rtl:design_ipcore:1:data_out
+ data_out_Data <= I_data_out_Data;
+ data_out_Control <= I_data_out_Control;
+ data_out_Write <= I_data_out_Write;
+ I_data_out_Full <= data_out_Full;
+
+ -- AD HOC EXTERNAL CONNECTIONS
+ -- DESIGN ID : compaandesign.com:ipcore2rtl:design_ipcore:1
+ TEST_STOP(0) <= signal_hwn_nd_1_STOP;
+ TEST_ERROR(0) <= signal_hwn_nd_1_ERROR;
+ TEST_BLOCK_RD(0) <= signal_hwn_nd_1_BLOCK_RD;
+ TEST_STOP(1) <= signal_hwn_nd_2_STOP;
+ TEST_ERROR(1) <= signal_hwn_nd_2_ERROR;
+ TEST_BLOCK_RD(1) <= signal_hwn_nd_2_BLOCK_RD;
+ TEST_STOP(2) <= signal_hwn_nd_3_STOP;
+ TEST_ERROR(2) <= signal_hwn_nd_3_ERROR;
+ TEST_BLOCK_RD(2) <= signal_hwn_nd_3_BLOCK_RD;
+ TEST_FIFO_FULL(0) <= signal_ed_1_FIFO_FULL;
+ TEST_FIFO_FULL(1) <= signal_ed_2_FIFO_FULL;
+ signal_address <= address( 18 downto 0);
+ read_data( 31 downto 0) <= signal_read_data;
+ signal_write_data <= write_data( 31 downto 0);
+ signal_read_en <= read_en;
+ signal_write_en <= write_en;
+ signal_param_ext_pci_clk <= pci_clk;
+ signal_register_rf_pci_clk <= pci_clk;
+
+-- Give default signals, default values
+
+ net_gnd0 <= '0';
+ net_gnd16(15 downto 0) <= B"0000000000000000";
+
+-- Instanciate the wrappers (HWN and Edges)
+
+
+ ipcore2rtl_hwn_nd_1_ip : ipcore2rtl_hwn_nd_1_ip_wrapper
+ port map (
+ data_in_Rd => I_data_in_Read,
+ data_in_Din => I_data_in_Data(31 downto 0),
+ data_in_Exist => I_data_in_Exists,
+ data_in_CLK => open,
+ data_in_CTRL => I_data_in_Control,
+ ND_1OP_1_Wr => signal_ed_1_out_FSL_M_Write,
+ ND_1OP_1_Dout(31 downto 0) => signal_ed_1_out_FSL_M_Data(0 to 31),
+ ND_1OP_1_Full => signal_ed_1_out_FSL_M_Full,
+ ND_1OP_1_CLK => open,
+ ND_1OP_1_CTRL => signal_ed_1_out_FSL_M_Control,
+ PARAM_DT => signal_PARAM_DT,
+ PARAM_LD => signal_PARAM_LD,
+ STOP => signal_hwn_nd_1_STOP,
+ ERROR => signal_hwn_nd_1_ERROR,
+ BLOCK_RD => signal_hwn_nd_1_BLOCK_RD,
+ RST => sys_rst_s,
+ CLK => sys_clk_s
+ );
+
+ ipcore2rtl_hwn_nd_2_ip : ipcore2rtl_hwn_nd_2_ip_wrapper
+ port map (
+ ND_2IP_1_Rd => signal_ed_1_in_FSL_S_Read,
+ ND_2IP_1_Din(31 downto 0) => signal_ed_1_in_FSL_S_Data(0 to 31),
+ ND_2IP_1_Exist => signal_ed_1_in_FSL_S_Exists,
+ ND_2IP_1_CLK => open,
+ ND_2IP_1_CTRL => signal_ed_1_in_FSL_S_Control,
+ ND_2OP_1_Wr => signal_ed_2_out_FSL_M_Write,
+ ND_2OP_1_Dout(31 downto 0) => signal_ed_2_out_FSL_M_Data(0 to 31),
+ ND_2OP_1_Full => signal_ed_2_out_FSL_M_Full,
+ ND_2OP_1_CLK => open,
+ ND_2OP_1_CTRL => signal_ed_2_out_FSL_M_Control,
+ PARAM_DT => signal_PARAM_DT,
+ PARAM_LD => signal_PARAM_LD,
+ STOP => signal_hwn_nd_2_STOP,
+ ERROR => signal_hwn_nd_2_ERROR,
+ BLOCK_RD => signal_hwn_nd_2_BLOCK_RD,
+ RST => sys_rst_s,
+ CLK => sys_clk_s
+ );
+
+ ipcore2rtl_hwn_nd_3_ip : ipcore2rtl_hwn_nd_3_ip_wrapper
+ port map (
+ ND_3IP_2_Rd => signal_ed_2_in_FSL_S_Read,
+ ND_3IP_2_Din(31 downto 0) => signal_ed_2_in_FSL_S_Data(0 to 31),
+ ND_3IP_2_Exist => signal_ed_2_in_FSL_S_Exists,
+ ND_3IP_2_CLK => open,
+ ND_3IP_2_CTRL => signal_ed_2_in_FSL_S_Control,
+ data_out_Wr => I_data_out_Write,
+ data_out_Dout => I_data_out_Data(31 downto 0),
+ data_out_Full => I_data_out_Full,
+ data_out_CLK => open,
+ data_out_CTRL => I_data_out_Control,
+ PARAM_DT => signal_PARAM_DT,
+ PARAM_LD => signal_PARAM_LD,
+ STOP => signal_hwn_nd_3_STOP,
+ ERROR => signal_hwn_nd_3_ERROR,
+ BLOCK_RD => signal_hwn_nd_3_BLOCK_RD,
+ RST => sys_rst_s,
+ CLK => sys_clk_s
+ );
+
+ ipcore2rtl_register_rf_ip : ipcore2rtl_register_rf_ip_wrapper
+ port map (
+ address => signal_address,
+ read_data => signal_read_data,
+ read_en => signal_read_en,
+ write_en => signal_write_en,
+ write_data => signal_write_data,
+ pci_clk => signal_register_rf_pci_clk,
+ RST => sys_rst_s,
+ CLK => sys_clk_s
+ );
+
+ ipcore2rtl_ed_1 : ipcore2rtl_ed_1_ip_wrapper
+ port map (
+ FSL_Clk => sys_clk_s,
+ SYS_Rst => sys_rst_s,
+ FSL_Rst => open,
+ FSL_M_Clk => net_gnd0,
+ FSL_M_Data => signal_ed_1_out_FSL_M_Data,
+ FSL_M_Control => signal_ed_1_out_FSL_M_Control,
+ FSL_M_Write => signal_ed_1_out_FSL_M_Write,
+ FSL_M_Full => signal_ed_1_out_FSL_M_Full,
+ FSL_S_Data => signal_ed_1_in_FSL_S_Data,
+ FSL_S_Control => signal_ed_1_in_FSL_S_Control,
+ FSL_S_Read => signal_ed_1_in_FSL_S_Read,
+ FSL_S_Exists => signal_ed_1_in_FSL_S_Exists,
+ FSL_S_Clk => net_gnd0,
+ FSL_FULL => signal_ed_1_FIFO_FULL,
+ FSL_Has_Data => open,
+ FSL_Control_IRQ => open
+ );
+
+ ipcore2rtl_ed_2 : ipcore2rtl_ed_2_ip_wrapper
+ port map (
+ FSL_Clk => sys_clk_s,
+ SYS_Rst => sys_rst_s,
+ FSL_Rst => open,
+ FSL_M_Clk => net_gnd0,
+ FSL_M_Data => signal_ed_2_out_FSL_M_Data,
+ FSL_M_Control => signal_ed_2_out_FSL_M_Control,
+ FSL_M_Write => signal_ed_2_out_FSL_M_Write,
+ FSL_M_Full => signal_ed_2_out_FSL_M_Full,
+ FSL_S_Data => signal_ed_2_in_FSL_S_Data,
+ FSL_S_Control => signal_ed_2_in_FSL_S_Control,
+ FSL_S_Read => signal_ed_2_in_FSL_S_Read,
+ FSL_S_Exists => signal_ed_2_in_FSL_S_Exists,
+ FSL_S_Clk => net_gnd0,
+ FSL_FULL => signal_ed_2_FIFO_FULL,
+ FSL_Has_Data => open,
+ FSL_Control_IRQ => open
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_ed_1_ip_wrapper.vhd b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_ed_1_ip_wrapper.vhd
similarity index 86%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_ed_1_ip_wrapper.vhd
rename to applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_ed_1_ip_wrapper.vhd
index 9f7c7c2f1716113f4dfbd708e49bfcb244aa3ab7..ada9a42c2b588cd790823ac36d86a081e54bf03f 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_ed_1_ip_wrapper.vhd
+++ b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_ed_1_ip_wrapper.vhd
@@ -1,93 +1,97 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_ed_1_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity ipcore2RTL_ed_1_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-
-
-end ipcore2RTL_ed_1_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_ed_1_ip_wrapper is
-
- component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer;
- C_ASYNC_CLKS : integer;
- C_IMPL_STYLE : integer;
- C_USE_CONTROL : integer;
- C_FSL_DWIDTH : integer;
- C_FSL_DEPTH : integer;
- C_READ_CLOCK_PERIOD : integer
- );
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
-begin
-
- ipcore2RTL_ed_1 : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS => 0,
- C_IMPL_STYLE => 0,
- C_USE_CONTROL => 0,
- C_FSL_DWIDTH => 31+1,
- C_FSL_DEPTH => 16,
- C_READ_CLOCK_PERIOD => 0
- )
- port map (
- FSL_Clk => FSL_Clk,
- SYS_Rst => SYS_Rst,
- FSL_Rst => FSL_Rst,
- FSL_M_Clk => FSL_M_Clk,
- FSL_M_Data => FSL_M_Data,
- FSL_M_Control => FSL_M_Control,
- FSL_M_Write => FSL_M_Write,
- FSL_M_Full => FSL_M_Full,
- FSL_S_Clk => FSL_S_Clk,
- FSL_S_Data => FSL_S_Data,
- FSL_S_Control => FSL_S_Control,
- FSL_S_Read => FSL_S_Read,
- FSL_S_Exists => FSL_S_Exists,
- FSL_Full => FSL_Full,
- FSL_Has_Data => FSL_Has_Data,
- FSL_Control_IRQ => FSL_Control_IRQ
- );
-
-end architecture STRUCTURE;
+-------------------------------------------------------------------------------
+-- ipcore2rtl_ed_1_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+library compaandesign_com_common_altera_1_lib;
+use compaandesign_com_common_altera_1_lib.all;
+
+entity ipcore2rtl_ed_1_ip_wrapper is
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 31);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 31);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+
+
+end ipcore2rtl_ed_1_ip_wrapper;
+
+architecture STRUCTURE of ipcore2rtl_ed_1_ip_wrapper is
+
+ component fsl_v20 is
+ generic (
+ C_EXT_RESET_HIGH : integer;
+ C_ASYNC_CLKS : integer;
+ C_IMPL_STYLE : integer;
+ C_USE_CONTROL : integer;
+ C_FSL_DWIDTH : integer;
+ C_FSL_DEPTH : integer;
+ C_READ_CLOCK_PERIOD : integer
+ );
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 31);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 31);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+ end component;
+
+begin
+
+ ipcore2rtl_ed_1 : fsl_v20
+ generic map (
+ C_EXT_RESET_HIGH => 1,
+ C_ASYNC_CLKS => 0,
+ C_IMPL_STYLE => 0,
+ C_USE_CONTROL => 0,
+ C_FSL_DWIDTH => 31+1,
+ C_FSL_DEPTH => 16,
+ C_READ_CLOCK_PERIOD => 0
+ )
+ port map (
+ FSL_Clk => FSL_Clk,
+ SYS_Rst => SYS_Rst,
+ FSL_Rst => FSL_Rst,
+ FSL_M_Clk => FSL_M_Clk,
+ FSL_M_Data => FSL_M_Data,
+ FSL_M_Control => FSL_M_Control,
+ FSL_M_Write => FSL_M_Write,
+ FSL_M_Full => FSL_M_Full,
+ FSL_S_Clk => FSL_S_Clk,
+ FSL_S_Data => FSL_S_Data,
+ FSL_S_Control => FSL_S_Control,
+ FSL_S_Read => FSL_S_Read,
+ FSL_S_Exists => FSL_S_Exists,
+ FSL_Full => FSL_Full,
+ FSL_Has_Data => FSL_Has_Data,
+ FSL_Control_IRQ => FSL_Control_IRQ
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_ed_2_ip_wrapper.vhd b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_ed_2_ip_wrapper.vhd
similarity index 86%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_ed_2_ip_wrapper.vhd
rename to applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_ed_2_ip_wrapper.vhd
index 2c9800a983d5999938ab4a36ae931a48c18444bd..cc8f2b21d8aeb05186a0ea7ca722312c200fdb71 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_ed_2_ip_wrapper.vhd
+++ b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_ed_2_ip_wrapper.vhd
@@ -1,93 +1,97 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_ed_2_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity ipcore2RTL_ed_2_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-
-
-end ipcore2RTL_ed_2_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_ed_2_ip_wrapper is
-
- component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer;
- C_ASYNC_CLKS : integer;
- C_IMPL_STYLE : integer;
- C_USE_CONTROL : integer;
- C_FSL_DWIDTH : integer;
- C_FSL_DEPTH : integer;
- C_READ_CLOCK_PERIOD : integer
- );
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
-begin
-
- ipcore2RTL_ed_2 : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS => 0,
- C_IMPL_STYLE => 0,
- C_USE_CONTROL => 0,
- C_FSL_DWIDTH => 31+1,
- C_FSL_DEPTH => 16,
- C_READ_CLOCK_PERIOD => 0
- )
- port map (
- FSL_Clk => FSL_Clk,
- SYS_Rst => SYS_Rst,
- FSL_Rst => FSL_Rst,
- FSL_M_Clk => FSL_M_Clk,
- FSL_M_Data => FSL_M_Data,
- FSL_M_Control => FSL_M_Control,
- FSL_M_Write => FSL_M_Write,
- FSL_M_Full => FSL_M_Full,
- FSL_S_Clk => FSL_S_Clk,
- FSL_S_Data => FSL_S_Data,
- FSL_S_Control => FSL_S_Control,
- FSL_S_Read => FSL_S_Read,
- FSL_S_Exists => FSL_S_Exists,
- FSL_Full => FSL_Full,
- FSL_Has_Data => FSL_Has_Data,
- FSL_Control_IRQ => FSL_Control_IRQ
- );
-
-end architecture STRUCTURE;
+-------------------------------------------------------------------------------
+-- ipcore2rtl_ed_2_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+library compaandesign_com_common_altera_1_lib;
+use compaandesign_com_common_altera_1_lib.all;
+
+entity ipcore2rtl_ed_2_ip_wrapper is
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 31);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 31);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+
+
+end ipcore2rtl_ed_2_ip_wrapper;
+
+architecture STRUCTURE of ipcore2rtl_ed_2_ip_wrapper is
+
+ component fsl_v20 is
+ generic (
+ C_EXT_RESET_HIGH : integer;
+ C_ASYNC_CLKS : integer;
+ C_IMPL_STYLE : integer;
+ C_USE_CONTROL : integer;
+ C_FSL_DWIDTH : integer;
+ C_FSL_DEPTH : integer;
+ C_READ_CLOCK_PERIOD : integer
+ );
+ port (
+ FSL_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+ FSL_Rst : out std_logic;
+ FSL_M_Clk : in std_logic;
+ FSL_M_Data : in std_logic_vector(0 to 31);
+ FSL_M_Control : in std_logic;
+ FSL_M_Write : in std_logic;
+ FSL_M_Full : out std_logic;
+ FSL_S_Clk : in std_logic;
+ FSL_S_Data : out std_logic_vector(0 to 31);
+ FSL_S_Control : out std_logic;
+ FSL_S_Read : in std_logic;
+ FSL_S_Exists : out std_logic;
+ FSL_Full : out std_logic;
+ FSL_Has_Data : out std_logic;
+ FSL_Control_IRQ : out std_logic
+ );
+ end component;
+
+begin
+
+ ipcore2rtl_ed_2 : fsl_v20
+ generic map (
+ C_EXT_RESET_HIGH => 1,
+ C_ASYNC_CLKS => 0,
+ C_IMPL_STYLE => 0,
+ C_USE_CONTROL => 0,
+ C_FSL_DWIDTH => 31+1,
+ C_FSL_DEPTH => 16,
+ C_READ_CLOCK_PERIOD => 0
+ )
+ port map (
+ FSL_Clk => FSL_Clk,
+ SYS_Rst => SYS_Rst,
+ FSL_Rst => FSL_Rst,
+ FSL_M_Clk => FSL_M_Clk,
+ FSL_M_Data => FSL_M_Data,
+ FSL_M_Control => FSL_M_Control,
+ FSL_M_Write => FSL_M_Write,
+ FSL_M_Full => FSL_M_Full,
+ FSL_S_Clk => FSL_S_Clk,
+ FSL_S_Data => FSL_S_Data,
+ FSL_S_Control => FSL_S_Control,
+ FSL_S_Read => FSL_S_Read,
+ FSL_S_Exists => FSL_S_Exists,
+ FSL_Full => FSL_Full,
+ FSL_Has_Data => FSL_Has_Data,
+ FSL_Control_IRQ => FSL_Control_IRQ
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_1_ip_wrapper.vhd b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_hwn_nd_1_ip_wrapper.vhd
similarity index 73%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_1_ip_wrapper.vhd
rename to applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_hwn_nd_1_ip_wrapper.vhd
index 49b4bf6039484b6f198e842fa51688fd8cff7174..0c7b07eb5d1b646ec1b5fad4b686698186fccd1c 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_1_ip_wrapper.vhd
+++ b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_hwn_nd_1_ip_wrapper.vhd
@@ -1,90 +1,95 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_hwn_nd_1_ip_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity ipcore2RTL_hwn_nd_1_ip_wrapper is
- port (
- data_in_Rd : out std_logic;
- data_in_Din : in std_logic_vector(31 downto 0);
- data_in_Exist : in std_logic;
- data_in_CLK : out std_logic;
- data_in_CTRL : in std_logic;
- ND_1OP_1_Wr : out std_logic;
- ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_Full : in std_logic;
- ND_1OP_1_CLK : out std_logic;
- ND_1OP_1_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-
-
-end ipcore2RTL_hwn_nd_1_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_hwn_nd_1_ip_wrapper is
-
- component ipcore2rtl_hwn_nd_1 is
- generic (
- RESET_HIGH : NATURAL := 1;
- PAR_WIDTH : NATURAL := 32;
- QUANT : NATURAL := 32;
- WRAP : BOOLEAN := true
- );
- port (
- data_in_Rd : out std_logic;
- data_in_Din : in std_logic_vector(31 downto 0);
- data_in_Exist : in std_logic;
- data_in_CLK : out std_logic;
- data_in_CTRL : in std_logic;
- ND_1OP_1_Wr : out std_logic;
- ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_Full : in std_logic;
- ND_1OP_1_CLK : out std_logic;
- ND_1OP_1_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-end component;
-
-begin
-
-ipcore2RTL_hwn_nd_1_ip_wrapper_ip : ipcore2rtl_hwn_nd_1
- generic map (
- RESET_HIGH => 1,
- PAR_WIDTH => 32,
- QUANT => 32,
- WRAP => true
- )
- port map (
- data_in_Rd => data_in_Rd,
- data_in_Din => data_in_Din,
- data_in_Exist => data_in_Exist,
- data_in_CLK => data_in_CLK,
- data_in_CTRL => data_in_CTRL,
- ND_1OP_1_Wr => ND_1OP_1_Wr,
- ND_1OP_1_Dout => ND_1OP_1_Dout,
- ND_1OP_1_Full => ND_1OP_1_Full,
- ND_1OP_1_CLK => ND_1OP_1_CLK,
- ND_1OP_1_CTRL => ND_1OP_1_CTRL,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- STOP => STOP,
- ERROR => ERROR,
- BLOCK_RD => BLOCK_RD,
- RST => RST,
- CLK => CLK
- );
-
-end architecture STRUCTURE;
+-------------------------------------------------------------------------------
+-- ipcore2rtl_hwn_nd_1_ip_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib;
+use compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib.all;
+
+entity ipcore2rtl_hwn_nd_1_ip_wrapper is
+ port (
+ data_in_Rd : out std_logic;
+ data_in_Din : in std_logic_vector(31 downto 0);
+ data_in_Exist : in std_logic;
+ data_in_CLK : out std_logic;
+ data_in_CTRL : in std_logic;
+ ND_1OP_1_Wr : out std_logic;
+ ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
+ ND_1OP_1_Full : in std_logic;
+ ND_1OP_1_CLK : out std_logic;
+ ND_1OP_1_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+
+
+end ipcore2rtl_hwn_nd_1_ip_wrapper;
+
+architecture STRUCTURE of ipcore2rtl_hwn_nd_1_ip_wrapper is
+
+ component ipcore2rtl_hwn_nd_1 is
+ generic (
+ RESET_HIGH : NATURAL := 1;
+ PAR_WIDTH : NATURAL := 16;
+ QUANT : NATURAL := 32;
+ WRAP : BOOLEAN := true;
+ STIM_DIR : STRING := "hwn_nd_1"
+ );
+ port (
+ data_in_Rd : out std_logic;
+ data_in_Din : in std_logic_vector(31 downto 0);
+ data_in_Exist : in std_logic;
+ data_in_CLK : out std_logic;
+ data_in_CTRL : in std_logic;
+ ND_1OP_1_Wr : out std_logic;
+ ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
+ ND_1OP_1_Full : in std_logic;
+ ND_1OP_1_CLK : out std_logic;
+ ND_1OP_1_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+end component;
+
+begin
+
+ipcore2rtl_hwn_nd_1_ip_wrapper_ip : ipcore2rtl_hwn_nd_1
+ generic map (
+ RESET_HIGH => 1,
+ PAR_WIDTH => 1,
+ QUANT => 32,
+ WRAP => true,
+ STIM_DIR => "compaandesign_com/ipcore2rtl/hwn_nd_1/tb/data/"
+ )
+ port map (
+ data_in_Rd => data_in_Rd,
+ data_in_Din => data_in_Din,
+ data_in_Exist => data_in_Exist,
+ data_in_CLK => data_in_CLK,
+ data_in_CTRL => data_in_CTRL,
+ ND_1OP_1_Wr => ND_1OP_1_Wr,
+ ND_1OP_1_Dout => ND_1OP_1_Dout,
+ ND_1OP_1_Full => ND_1OP_1_Full,
+ ND_1OP_1_CLK => ND_1OP_1_CLK,
+ ND_1OP_1_CTRL => ND_1OP_1_CTRL,
+ PARAM_DT => PARAM_DT,
+ PARAM_LD => PARAM_LD,
+ STOP => STOP,
+ ERROR => ERROR,
+ BLOCK_RD => BLOCK_RD,
+ RST => RST,
+ CLK => CLK
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_2_ip_wrapper.vhd b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_hwn_nd_2_ip_wrapper.vhd
similarity index 73%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_2_ip_wrapper.vhd
rename to applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_hwn_nd_2_ip_wrapper.vhd
index eb637addc4c17caca8c45f158a350b55163d9611..aa82078e092bd013c02842972523d6599344b005 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_2_ip_wrapper.vhd
+++ b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_hwn_nd_2_ip_wrapper.vhd
@@ -1,90 +1,95 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_hwn_nd_2_ip_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity ipcore2RTL_hwn_nd_2_ip_wrapper is
- port (
- ND_2IP_1_Rd : out std_logic;
- ND_2IP_1_Din : in std_logic_vector(31 downto 0);
- ND_2IP_1_Exist : in std_logic;
- ND_2IP_1_CLK : out std_logic;
- ND_2IP_1_CTRL : in std_logic;
- ND_2OP_1_Wr : out std_logic;
- ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_Full : in std_logic;
- ND_2OP_1_CLK : out std_logic;
- ND_2OP_1_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-
-
-end ipcore2RTL_hwn_nd_2_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_hwn_nd_2_ip_wrapper is
-
- component ipcore2rtl_hwn_nd_2 is
- generic (
- RESET_HIGH : NATURAL := 1;
- PAR_WIDTH : NATURAL := 32;
- QUANT : NATURAL := 32;
- WRAP : BOOLEAN := true
- );
- port (
- ND_2IP_1_Rd : out std_logic;
- ND_2IP_1_Din : in std_logic_vector(31 downto 0);
- ND_2IP_1_Exist : in std_logic;
- ND_2IP_1_CLK : out std_logic;
- ND_2IP_1_CTRL : in std_logic;
- ND_2OP_1_Wr : out std_logic;
- ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_Full : in std_logic;
- ND_2OP_1_CLK : out std_logic;
- ND_2OP_1_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-end component;
-
-begin
-
-ipcore2RTL_hwn_nd_2_ip_wrapper_ip : ipcore2rtl_hwn_nd_2
- generic map (
- RESET_HIGH => 1,
- PAR_WIDTH => 32,
- QUANT => 32,
- WRAP => true
- )
- port map (
- ND_2IP_1_Rd => ND_2IP_1_Rd,
- ND_2IP_1_Din => ND_2IP_1_Din,
- ND_2IP_1_Exist => ND_2IP_1_Exist,
- ND_2IP_1_CLK => ND_2IP_1_CLK,
- ND_2IP_1_CTRL => ND_2IP_1_CTRL,
- ND_2OP_1_Wr => ND_2OP_1_Wr,
- ND_2OP_1_Dout => ND_2OP_1_Dout,
- ND_2OP_1_Full => ND_2OP_1_Full,
- ND_2OP_1_CLK => ND_2OP_1_CLK,
- ND_2OP_1_CTRL => ND_2OP_1_CTRL,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- STOP => STOP,
- ERROR => ERROR,
- BLOCK_RD => BLOCK_RD,
- RST => RST,
- CLK => CLK
- );
-
-end architecture STRUCTURE;
+-------------------------------------------------------------------------------
+-- ipcore2rtl_hwn_nd_2_ip_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib;
+use compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib.all;
+
+entity ipcore2rtl_hwn_nd_2_ip_wrapper is
+ port (
+ ND_2IP_1_Rd : out std_logic;
+ ND_2IP_1_Din : in std_logic_vector(31 downto 0);
+ ND_2IP_1_Exist : in std_logic;
+ ND_2IP_1_CLK : out std_logic;
+ ND_2IP_1_CTRL : in std_logic;
+ ND_2OP_1_Wr : out std_logic;
+ ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
+ ND_2OP_1_Full : in std_logic;
+ ND_2OP_1_CLK : out std_logic;
+ ND_2OP_1_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+
+
+end ipcore2rtl_hwn_nd_2_ip_wrapper;
+
+architecture STRUCTURE of ipcore2rtl_hwn_nd_2_ip_wrapper is
+
+ component ipcore2rtl_hwn_nd_2 is
+ generic (
+ RESET_HIGH : NATURAL := 1;
+ PAR_WIDTH : NATURAL := 16;
+ QUANT : NATURAL := 32;
+ WRAP : BOOLEAN := true;
+ STIM_DIR : STRING := "hwn_nd_2"
+ );
+ port (
+ ND_2IP_1_Rd : out std_logic;
+ ND_2IP_1_Din : in std_logic_vector(31 downto 0);
+ ND_2IP_1_Exist : in std_logic;
+ ND_2IP_1_CLK : out std_logic;
+ ND_2IP_1_CTRL : in std_logic;
+ ND_2OP_1_Wr : out std_logic;
+ ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
+ ND_2OP_1_Full : in std_logic;
+ ND_2OP_1_CLK : out std_logic;
+ ND_2OP_1_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+end component;
+
+begin
+
+ipcore2rtl_hwn_nd_2_ip_wrapper_ip : ipcore2rtl_hwn_nd_2
+ generic map (
+ RESET_HIGH => 1,
+ PAR_WIDTH => 1,
+ QUANT => 32,
+ WRAP => true,
+ STIM_DIR => "compaandesign_com/ipcore2rtl/hwn_nd_2/tb/data/"
+ )
+ port map (
+ ND_2IP_1_Rd => ND_2IP_1_Rd,
+ ND_2IP_1_Din => ND_2IP_1_Din,
+ ND_2IP_1_Exist => ND_2IP_1_Exist,
+ ND_2IP_1_CLK => ND_2IP_1_CLK,
+ ND_2IP_1_CTRL => ND_2IP_1_CTRL,
+ ND_2OP_1_Wr => ND_2OP_1_Wr,
+ ND_2OP_1_Dout => ND_2OP_1_Dout,
+ ND_2OP_1_Full => ND_2OP_1_Full,
+ ND_2OP_1_CLK => ND_2OP_1_CLK,
+ ND_2OP_1_CTRL => ND_2OP_1_CTRL,
+ PARAM_DT => PARAM_DT,
+ PARAM_LD => PARAM_LD,
+ STOP => STOP,
+ ERROR => ERROR,
+ BLOCK_RD => BLOCK_RD,
+ RST => RST,
+ CLK => CLK
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_hwn_nd_3_ip_wrapper.vhd
similarity index 73%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd
rename to applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_hwn_nd_3_ip_wrapper.vhd
index 94d3add4b9a51be450bb85e497c05e1cc6e54ccc..eb6f98e4256315ac33425bb36033ea59b7dc21a6 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd
+++ b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_hwn_nd_3_ip_wrapper.vhd
@@ -1,90 +1,95 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_hwn_nd_3_ip_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity ipcore2RTL_hwn_nd_3_ip_wrapper is
- port (
- ND_3IP_2_Rd : out std_logic;
- ND_3IP_2_Din : in std_logic_vector(31 downto 0);
- ND_3IP_2_Exist : in std_logic;
- ND_3IP_2_CLK : out std_logic;
- ND_3IP_2_CTRL : in std_logic;
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-
-
-end ipcore2RTL_hwn_nd_3_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_hwn_nd_3_ip_wrapper is
-
- component ipcore2rtl_hwn_nd_3 is
- generic (
- RESET_HIGH : NATURAL := 1;
- PAR_WIDTH : NATURAL := 32;
- QUANT : NATURAL := 32;
- WRAP : BOOLEAN := true
- );
- port (
- ND_3IP_2_Rd : out std_logic;
- ND_3IP_2_Din : in std_logic_vector(31 downto 0);
- ND_3IP_2_Exist : in std_logic;
- ND_3IP_2_CLK : out std_logic;
- ND_3IP_2_CTRL : in std_logic;
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-end component;
-
-begin
-
-ipcore2RTL_hwn_nd_3_ip_wrapper_ip : ipcore2rtl_hwn_nd_3
- generic map (
- RESET_HIGH => 1,
- PAR_WIDTH => 32,
- QUANT => 32,
- WRAP => true
- )
- port map (
- ND_3IP_2_Rd => ND_3IP_2_Rd,
- ND_3IP_2_Din => ND_3IP_2_Din,
- ND_3IP_2_Exist => ND_3IP_2_Exist,
- ND_3IP_2_CLK => ND_3IP_2_CLK,
- ND_3IP_2_CTRL => ND_3IP_2_CTRL,
- data_out_Wr => data_out_Wr,
- data_out_Dout => data_out_Dout,
- data_out_Full => data_out_Full,
- data_out_CLK => data_out_CLK,
- data_out_CTRL => data_out_CTRL,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- STOP => STOP,
- ERROR => ERROR,
- BLOCK_RD => BLOCK_RD,
- RST => RST,
- CLK => CLK
- );
-
-end architecture STRUCTURE;
+-------------------------------------------------------------------------------
+-- ipcore2rtl_hwn_nd_3_ip_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib;
+use compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib.all;
+
+entity ipcore2rtl_hwn_nd_3_ip_wrapper is
+ port (
+ ND_3IP_2_Rd : out std_logic;
+ ND_3IP_2_Din : in std_logic_vector(31 downto 0);
+ ND_3IP_2_Exist : in std_logic;
+ ND_3IP_2_CLK : out std_logic;
+ ND_3IP_2_CTRL : in std_logic;
+ data_out_Wr : out std_logic;
+ data_out_Dout : out std_logic_vector(31 downto 0);
+ data_out_Full : in std_logic;
+ data_out_CLK : out std_logic;
+ data_out_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+
+
+end ipcore2rtl_hwn_nd_3_ip_wrapper;
+
+architecture STRUCTURE of ipcore2rtl_hwn_nd_3_ip_wrapper is
+
+ component ipcore2rtl_hwn_nd_3 is
+ generic (
+ RESET_HIGH : NATURAL := 1;
+ PAR_WIDTH : NATURAL := 16;
+ QUANT : NATURAL := 32;
+ WRAP : BOOLEAN := true;
+ STIM_DIR : STRING := "hwn_nd_3"
+ );
+ port (
+ ND_3IP_2_Rd : out std_logic;
+ ND_3IP_2_Din : in std_logic_vector(31 downto 0);
+ ND_3IP_2_Exist : in std_logic;
+ ND_3IP_2_CLK : out std_logic;
+ ND_3IP_2_CTRL : in std_logic;
+ data_out_Wr : out std_logic;
+ data_out_Dout : out std_logic_vector(31 downto 0);
+ data_out_Full : in std_logic;
+ data_out_CLK : out std_logic;
+ data_out_CTRL : out std_logic;
+ PARAM_DT : in std_logic_vector(10 downto 0);
+ PARAM_LD : in std_logic;
+ STOP : out std_logic;
+ ERROR : out std_logic;
+ BLOCK_RD : out std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+end component;
+
+begin
+
+ipcore2rtl_hwn_nd_3_ip_wrapper_ip : ipcore2rtl_hwn_nd_3
+ generic map (
+ RESET_HIGH => 1,
+ PAR_WIDTH => 1,
+ QUANT => 32,
+ WRAP => true,
+ STIM_DIR => "compaandesign_com/ipcore2rtl/hwn_nd_3/tb/data/"
+ )
+ port map (
+ ND_3IP_2_Rd => ND_3IP_2_Rd,
+ ND_3IP_2_Din => ND_3IP_2_Din,
+ ND_3IP_2_Exist => ND_3IP_2_Exist,
+ ND_3IP_2_CLK => ND_3IP_2_CLK,
+ ND_3IP_2_CTRL => ND_3IP_2_CTRL,
+ data_out_Wr => data_out_Wr,
+ data_out_Dout => data_out_Dout,
+ data_out_Full => data_out_Full,
+ data_out_CLK => data_out_CLK,
+ data_out_CTRL => data_out_CTRL,
+ PARAM_DT => PARAM_DT,
+ PARAM_LD => PARAM_LD,
+ STOP => STOP,
+ ERROR => ERROR,
+ BLOCK_RD => BLOCK_RD,
+ RST => RST,
+ CLK => CLK
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_register_rf_ip_wrapper.vhd b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_register_rf_ip_wrapper.vhd
similarity index 53%
rename from applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_register_rf_ip_wrapper.vhd
rename to applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_register_rf_ip_wrapper.vhd
index d699356bf3fa94b6072d2baaf8facb50b174849d..fbc5a1fdca4cb79ffa74c6877a6d04aa9b0d6327 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_register_rf_ip_wrapper.vhd
+++ b/applications/compaan/libraries/vhdl_altera/src/vhdl/ipcore2rtl_register_rf_ip_wrapper.vhd
@@ -1,60 +1,54 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_register_rf_ip_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity ipcore2RTL_register_rf_ip_wrapper is
- port (
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0);
- reg_rf_read_data : in std_logic_vector(32-1 downto 0);
- reg_rf_read_en : out std_logic;
- reg_rf_write_en : out std_logic;
- reg_rf_write_data : out std_logic_vector(32-1 downto 0);
- RST : in std_logic;
- CLK : in std_logic
- );
-
-
-end ipcore2RTL_register_rf_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_register_rf_ip_wrapper is
-
- component register_rf is
- port (
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0);
- reg_rf_read_data : in std_logic_vector(32-1 downto 0);
- reg_rf_read_en : out std_logic;
- reg_rf_write_en : out std_logic;
- reg_rf_write_data : out std_logic_vector(32-1 downto 0);
- RST : in std_logic;
- CLK : in std_logic
- );
-end component;
-
-begin
-
-ipcore2RTL_register_rf_ip_wrapper_ip : register_rf
- port map (
- address => address,
- read_data => read_data,
- read_en => read_en,
- write_en => write_en,
- write_data => write_data,
- reg_rf_read_data => reg_rf_read_data,
- reg_rf_read_en => reg_rf_read_en,
- reg_rf_write_en => reg_rf_write_en,
- reg_rf_write_data => reg_rf_write_data,
- RST => RST,
- CLK => CLK
- );
-
-end architecture STRUCTURE;
+-------------------------------------------------------------------------------
+-- ipcore2rtl_register_rf_ip_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library compaandesign_com_ipcore2rtl_register_rf_1_lib;
+use compaandesign_com_ipcore2rtl_register_rf_1_lib.all;
+
+entity ipcore2rtl_register_rf_ip_wrapper is
+ port (
+ address : in std_logic_vector(18 downto 0);
+ read_data : out std_logic_vector(31 downto 0);
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0);
+ pci_clk : in std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+
+
+end ipcore2rtl_register_rf_ip_wrapper;
+
+architecture STRUCTURE of ipcore2rtl_register_rf_ip_wrapper is
+
+ component register_rf is
+ port (
+ address : in std_logic_vector(18 downto 0);
+ read_data : out std_logic_vector(31 downto 0);
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0);
+ pci_clk : in std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+end component;
+
+begin
+
+ipcore2rtl_register_rf_ip_wrapper_ip : register_rf
+ port map (
+ address => address,
+ read_data => read_data,
+ read_en => read_en,
+ write_en => write_en,
+ write_data => write_data,
+ pci_clk => pci_clk,
+ RST => RST,
+ CLK => CLK
+ );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/vhdl_altera/src/vhdl/system_ext_TB.vhd b/applications/compaan/libraries/vhdl_altera/src/vhdl/system_ext_TB.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..efd3ce1c0421aa4273472d622ead316c25b9bdb6
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/src/vhdl/system_ext_TB.vhd
@@ -0,0 +1,411 @@
+-- System TestBench; automatically generated by KpnMapper
+-- Use this file to test the system generated by XPS
+-- The interface of the tested System includes only the FIFO interfaces
+-- declared as external interfaces and not the FIFO interfaces connected
+-- to platform FIFOs
+-- To generate a System with complete interface select the *noboard* platform option
+--
+-- =====================================================================================
+-- To use this testbench file you have to:
+-- 1. Set propper Time-Out interval (constant TIMEOUT)
+-- 2. If you read stimuli from files, provide a path to the directory that contains the stimuli files (constant STIM_DIR)
+-- 3. For each input select whether stimuli is read from a file (default) or from a table (see processes *_STIM_DRV)
+-- 4. For each output select whether stimuli is read from a file (default) or from a table (see processes *_STIM_CMP)
+-- 5. For each stimuli that is read from a table fill the stimuli data in the table (constant *_STIM)
+-- =====================================================================================
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library std;
+use std.textio.all;
+
+entity system_ext_TB is
+end system_ext_TB;
+
+architecture RTL of system_ext_TB is
+
+ constant CLK_PERIOD : TIME := 10 ns; -- Period of the system clock
+ constant RESET_LENGTH : natural := 5; -- Reset duration [clock cycles]
+ constant STIM_DELAY : natural := RESET_LENGTH + 5; -- When stimuli supply starts [clock cycles]
+ --
+ -- Set Time-0ut interval sufficienly long for your application to complete
+ constant TIMEOUT : natural := 60000; -- Time-Out [clock cycles]
+ --
+ constant STIM_DIR : string := "C:\Users\Bart\Documents\workspace\ipcore_astron\"; -- Provide here the path to your stimuli files directory
+ -- Input stimuli files: to provide data streams to input FIFOs
+ constant STIM_FILE_data_in : string := "STIM_FILE_data_in.txt";
+ constant STIM_FILE_data_out : string := "STIM_FILE_data_out.txt";
+
+ signal ENDSIM : boolean := false; -- Simulation has finished
+ signal ENDSTIM_IN : boolean := false; -- All input stimuli has been sent
+ signal ENDSTIM_OUT : boolean := false; -- All expected data has been received
+ signal ENDTIMEOUT : boolean := false; -- Simulation Time-Out has occured
+ signal timeout_cntr : natural;
+ signal ERROR_SYS : boolean := false; -- Error: Some of te system nodes indicated error
+ signal ERROR_OUT : boolean := false; -- Error: Detected output data differs from the expected output data
+ signal FIRST_ERROR : time; -- The time when the first error occured
+ signal ENDSTOP : boolean := true; -- All system nodes have flagged 'Stop'
+
+ --
+ -- Component Under Test
+ component ipcore is
+ port (
+ -- FIFO_In Interface: data_in
+ data_in_Data : in std_logic_vector(31 downto 0);
+ data_in_Control : in std_logic;
+ data_in_Read : out std_logic;
+ data_in_Exists : in std_logic;
+
+ -- FIFO_Out Interface: data_out
+ data_out_Data : out std_logic_vector(31 downto 0);
+ data_out_Control : out std_logic;
+ data_out_Write : out std_logic;
+ data_out_Full : in std_logic;
+
+ TEST_STOP : out std_logic_vector(2 downto 0);
+ TEST_ERROR : out std_logic_vector(2 downto 0);
+ TEST_FIFO_FULL : out std_logic_vector(1 downto 0);
+ TEST_BLOCK_RD : out std_logic_vector(2 downto 0);
+ address : in std_logic_vector(18 downto 0);
+ read_data : out std_logic_vector(31 downto 0);
+ read_en : in std_logic;
+ write_en : in std_logic;
+ write_data : in std_logic_vector(31 downto 0);
+ pci_clk : in std_logic;
+ --
+ KPN_CLK : in std_logic;
+ KPN_RST : in std_logic
+ );
+ end component;
+ --
+ signal RST : STD_LOGIC := '0';
+ signal CLK : STD_LOGIC := '0';
+ --
+ type FIFO_SRC_REC is record
+ Data : integer;
+ Control : std_logic;
+ Read : std_logic;
+ Exists : std_logic;
+ --
+ Count : natural;
+ Done : boolean;
+ end record;
+ --
+ type FIFO_SNK_REC is record
+ Data : integer;
+ Control : std_logic;
+ Write : std_logic;
+ Full : std_logic;
+ --
+ Count : natural;
+ Done : boolean;
+ Error : boolean;
+ First_error : time;
+ end record;
+ --
+ signal data_in : FIFO_SRC_REC;
+ signal data_out : FIFO_SNK_REC;
+ --
+ signal data_in_Data : std_logic_vector(31 downto 0);
+ signal data_out_Data : std_logic_vector(31 downto 0);
+ signal TEST_STOP : std_logic_vector(2 downto 0);
+ signal TEST_ERROR : std_logic_vector(2 downto 0);
+ signal TEST_FIFO_FULL : std_logic_vector(1 downto 0);
+ signal TEST_BLOCK_RD : std_logic_vector(2 downto 0);
+ signal address : std_logic_vector(18 downto 0);
+ signal read_data : std_logic_vector(31 downto 0);
+ signal read_en : std_logic;
+ signal write_en : std_logic;
+ signal write_data : std_logic_vector(31 downto 0);
+ signal pci_clk : std_logic;
+ --
+ -- record keeping values of input and output stimuli
+ type STIM_REC is record
+ Data : integer;
+ Control : std_logic;
+ end record;
+ --
+ -- Function that reads a STIM_REC from a (stimuli) file
+ impure function FREAD_STIM(file F : TEXT) return STIM_REC is
+ variable VECTOR : STIM_REC;
+ variable IN_LINE : LINE;
+ begin
+ readline(F ,IN_LINE);
+ read(IN_LINE, VECTOR.Data);
+ deallocate(IN_LINE);
+ VECTOR.Control := '0'; -- Control bit is not used at the moment
+ return VECTOR;
+ end;
+ --
+ -- table of records
+ type STIM_ARRAY is array(positive range <>) of STIM_REC;
+ --
+ -- Stimuli can be read either from a file or from the constant tables below
+ -- If you will use constant tables, uncomment below those you need
+-- constant data_in_STIM : STIM_ARRAY := (
+-- -- Provide your stimuli here
+-- -- ( Data, Control),
+-- -- e.g. ( 0, '0'),
+-- -- e.g. ( 0, '0')
+-- );
+ --
+-- constant data_out_STIM : STIM_ARRAY := (
+-- -- Provide your stimuli here
+-- -- ( Data, Control),
+-- -- e.g. ( 0, '0'),
+-- -- e.g. ( 0, '0')
+-- );
+ --
+begin
+ --
+ -- =============================================
+ -- = System Under Test
+ -- =============================================
+ SUT : ipcore port map(
+ --
+ data_in_Data => data_in_Data ,
+ data_in_Control => data_in.Control ,
+ data_in_Read => data_in.Read ,
+ data_in_Exists => data_in.Exists ,
+ --
+ data_out_Data => data_out_Data ,
+ data_out_Control => data_out.Control ,
+ data_out_Write => data_out.Write ,
+ data_out_Full => data_out.Full ,
+ TEST_STOP => TEST_STOP ,
+ TEST_ERROR => TEST_ERROR ,
+ TEST_FIFO_FULL => TEST_FIFO_FULL ,
+ TEST_BLOCK_RD => TEST_BLOCK_RD ,
+ address => address ,
+ read_data => read_data ,
+ read_en => read_en ,
+ write_en => write_en ,
+ write_data => write_data ,
+ pci_clk => pci_clk ,
+ --
+ KPN_CLK => CLK,
+ KPN_RST => RST
+ );
+ --
+ pci_clk <= CLK;
+ --
+ data_in_Data <= STD_LOGIC_VECTOR(TO_SIGNED(data_in.Data, data_in_Data'Length));
+ data_out.Data <= TO_INTEGER(SIGNED(data_out_Data));
+
+ -- Adjust these values to changes values in the Register file to change parameters and shmem
+reg_file : process
+ variable read_in : std_logic_vector(31 downto 0);
+begin
+ address <= (others => '0');
+ write_en <= '0';
+ read_en <= '0';
+ address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
+ write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
+
+-- wait for 100ns;
+-- address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
+-- write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
+-- wait for 1*CLK_PERIOD;
+-- write_en <= '1';
+-- wait for 2*CLK_PERIOD;
+-- write_en <= '0';
+-- wait for 1*CLK_PERIOD;
+-- --read_en <= '1';
+-- wait for 2*CLK_PERIOD;
+-- --read_en <= '0';
+-- wait for 1*CLK_PERIOD;
+-- wait for 300ns;
+ wait;
+end process;
+
+ --
+ -- Stimuli Driver for input stream : data_in
+ data_in_STIM_DRV : process
+ variable VECTOR : STIM_REC;
+ file STIM_FILE : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_in;
+ begin
+ data_in.Exists <= '0';
+ data_in.Count <= 0;
+ data_in.Done <= false;
+ wait for STIM_DELAY*CLK_PERIOD;
+ wait until rising_edge(CLK);
+----------------------------------------------
+-- -- Uncomment if stimuli for data_in is read from a constant tables
+-- for i in data_in_STIM'range loop
+-- VECTOR:= data_in_STIM(i);
+----------------------------------------------
+ -- Uncomment if stimuli for data_in is read from a file
+ while not( endfile(STIM_FILE)) loop
+ VECTOR := FREAD_STIM(STIM_FILE);
+--------------------------------------------
+ data_in.Data <= VECTOR.Data;
+ data_in.Control <= VECTOR.Control;
+ data_in.Exists <= '1';
+ L1: loop
+ wait until rising_edge(CLK);
+ exit L1 when (data_in.Read = '1');
+ end loop L1;
+ data_in.Count <= data_in.Count + 1;
+ end loop;
+ data_in.Exists <= '0';
+ data_in.Done <= true;
+ wait for 10*CLK_PERIOD;
+ wait;
+ end process;
+ --
+ ENDSTIM_IN <= data_in.Done;
+ --
+ -- Stimuli Comparator for output stream data_out
+ data_out_STIM_CMP : process
+ variable VECTOR : STIM_REC;
+ file STIM_FILE : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_out;
+ begin
+ data_out.Full <= '1';
+ data_out.Count <= 0;
+ data_out.Done <= false;
+ data_out.Error <= false;
+ wait for STIM_DELAY*CLK_PERIOD;
+ wait until rising_edge(CLK);
+----------------------------------------------
+-- -- Uncomment if stimuli for data_out is read from a constant tables
+-- for i in data_out_STIM'range loop
+-- VECTOR := data_out_STIM(i);
+----------------------------------------------
+ -- Uncomment if stimuli for data_out is read from a file
+ while not( endfile(STIM_FILE)) loop
+ VECTOR := FREAD_STIM(STIM_FILE);
+----------------------------------------------
+ --
+ data_out.Full <= '0';
+ L1: loop
+ wait until rising_edge(CLK);
+ exit L1 when (data_out.Write = '1');
+ end loop L1;
+ data_out.Count <= data_out.Count + 1;
+ if (data_out.Data /= VECTOR.Data) then
+ report "TB_ERROR: Output 'data_out': the detected value " & integer'image(data_out.Data) & " differs from the expected value " & integer'image(VECTOR.Data) & "!!! (@time " & time'image(now) & ")."
+ severity WARNING;
+ if (not data_out.Error) then
+ data_out.First_error <= now;
+ end if;
+ data_out.Error <= true;
+ end if;
+ end loop;
+ data_out.Full <= '1';
+ data_out.Done <= true;
+ wait for 10*CLK_PERIOD;
+ wait;
+ end process;
+ --
+ ENDSTIM_OUT <= data_out.Done;
+ ERROR_OUT <= data_out.Error;
+ --
+ -- Record the time when the first error occures
+ FIRST_ERROR_TIME : process
+ begin
+ wait until (ERROR_OUT'event and ERROR_OUT=true) or (ERROR_SYS'event and ERROR_SYS=true);
+ FIRST_ERROR <= now;
+ wait;
+ end process;
+ --
+--=============================================
+--= All Nodes stopped ?
+--=============================================
+ process(test_stop)
+ variable s : std_logic;
+ variable e : std_logic;
+ begin
+ s := '1';
+ e := '0';
+ --
+ for i in 0 to TEST_ERROR'Length-1 loop
+ s := s and test_stop(i);
+ e := e or test_error(i);
+ end loop;
+ --
+ ENDSTOP <= (s = '1');
+ ERROR_SYS <= (e = '1');
+ --
+ end process;
+ -- Timeout counter
+ TO_CTRL : process(CLK)
+ begin
+ if (rising_edge(CLK)) then
+ if (RST = '1') then
+ timeout_cntr <= 0;
+ else
+ if (timeout_cntr = TIMEOUT) then
+ ENDTIMEOUT <= true;
+ else
+ timeout_cntr <= timeout_cntr + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+ --
+ -- Simulation control
+ ENDSIM <= (ENDSTIM_IN and ENDSTOP and ENDSTIM_OUT) or ENDTIMEOUT;
+ --
+ PRINT_REPORT : process
+ variable ERROR_CODE : natural;
+ variable l : line;
+ begin
+ -- write(l, "***TB_REPOT: Simulation in progress...");
+ writeline(output,l);
+ wait until ENDSIM=true;
+ -- write(l, "***TB_REPOT: Simulation END.");
+ writeline(output,l);
+ ERROR_CODE := 0;
+ --
+ if (ENDTIMEOUT) then
+ ERROR_CODE := ERROR_CODE + 1;
+ write(l, "***TB_REPOT: [TIMEOUT] Simulation terminated by a TIMEOUT after " & integer'image(timeout_cntr) & " clock cycles.");
+ writeline(output,l);
+ end if;
+ --
+ if (ERROR_OUT or ERROR_SYS) then
+ ERROR_CODE := ERROR_CODE + 2;
+ write(l, "***TB_REPOT: [ERROR] Simulation terminated with ERRORS!!! First error occured at time " & time'image(FIRST_ERROR) & ".");
+ writeline(output,l);
+ -- write(l, "***TB_REPOT: [ERROR] Flags ERROR = b");
+ -- write(l, test_error, RIGHT, test_error'Length);
+ -- writeline(output,l);
+ end if;
+ --
+ write(l, "***TB_REPOT: [ERROR_CODE=" & integer'image(ERROR_CODE) & "]");
+ writeline(output,l);
+ --
+ if (ERROR_CODE = 0) then
+ write(l, "***TB_REPOT: [OK] Simulation completed successfully in " & integer'image(timeout_cntr) & " cycles !!!");
+ writeline(output,l);
+ -- write(l, "None of the processors flagged ERROR. ");
+ writeline(output,l);
+ end if;
+ wait;
+ end process;
+ --
+ -- CLK generator
+ CLK_GEN: process
+ begin
+ if (ENDSIM=false) then
+ CLK <= '0';
+ wait for CLK_PERIOD/2;
+ CLK <= '1';
+ wait for CLK_PERIOD/2;
+ else
+ wait;
+ end if;
+ end process;
+ --
+ -- RESET generator
+ RST_GEN: process
+ begin
+ RST <='1';
+ wait for RESET_LENGTH*CLK_PERIOD;
+ RST <='0';
+ wait;
+ end process;
+ --
+end RTL;
diff --git a/applications/compaan/libraries/vhdl_altera/transcript b/applications/compaan/libraries/vhdl_altera/transcript
new file mode 100644
index 0000000000000000000000000000000000000000..e062e8161aa92fb058b2dc758ae3dca277412c8b
--- /dev/null
+++ b/applications/compaan/libraries/vhdl_altera/transcript
@@ -0,0 +1,17304 @@
+# // ModelSim SE-64 6.6c Aug 23 2010 Linux 3.0.101-0.7.17-default
+# //
+# // Copyright 1991-2010 Mentor Graphics Corporation
+# // All Rights Reserved.
+# //
+# // THIS WORK CONTAINS TRADE SECRET AND
+# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
+# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
+# // AND IS SUBJECT TO LICENSE TERMS.
+# //
+# do /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/tools/modelsim/commands.do
+# Loading general HDL library commands...
+lp compaan_unb1_10g_app
+# Loading project compaan_unb1_10g_app
+# compaan_unb1_10g_app
+mk
+# [mk make compaan_unb1_10g_app]
+#
+# compaan_unb1_10g_app
+mk all
+# technology ip_stratixiv_ram tech_memory ip_stratixiv_fifo tech_fifo ip_stratixiv_ddio tech_iobuf tst common mm ip_stratixiv_mult tech_mult common_mult easics dp diag uth ppsh i2c diagnostics ip_stratixiv_transceiver tech_transceiver tr_nonbonded ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx tech_tse eth numonyx_m25p128 ip_stratixiv_flash tech_flash remu ip_stratixiv_pll ip_stratixiv_pll_clk25 tech_pll epcs unb1_board ip_stratixiv_mac_10g tech_mac_10g tech_10gbase_r ip_stratixiv_phy_xaui tech_xaui tech_eth_10g mdio tr_xaui tr_10GbE compaandesign_com_common_common_1 compaandesign_com_common_altera_1 compaandesign_com_common_hwnode_1 compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_ipcore2rtl_hwn_nd_3_1 compaandesign_com_ipcore2rtl_hwn_nd_1_1 compaandesign_com_ipcore2rtl_register_rf_1 compaandesign_com_ipcore2rtl_hwn_nd_2_1 ipcore compaan_unb1_10g_app
+# [mk make technology]
+#
+# [mk make ip_stratixiv_ram]
+#
+# [mk make tech_memory]
+#
+# [mk make ip_stratixiv_fifo]
+#
+# [mk make tech_fifo]
+#
+# [mk make ip_stratixiv_ddio]
+#
+# [mk make tech_iobuf]
+#
+# [mk make tst]
+#
+# [mk make common]
+#
+# [mk make mm]
+#
+# [mk make ip_stratixiv_mult]
+#
+# [mk make tech_mult]
+#
+# [mk make common_mult]
+#
+# [mk make easics]
+#
+# [mk make dp]
+#
+# [mk make diag]
+#
+# [mk make uth]
+#
+# [mk make ppsh]
+#
+# [mk make i2c]
+#
+# [mk make diagnostics]
+#
+# [mk make ip_stratixiv_transceiver]
+#
+# [mk make tech_transceiver]
+#
+# [mk make tr_nonbonded]
+#
+# [mk make ip_stratixiv_tse_sgmii_lvds]
+#
+# [mk make ip_stratixiv_tse_sgmii_gx]
+#
+# [mk make tech_tse]
+#
+# [mk make eth]
+#
+# [mk make numonyx_m25p128]
+#
+# [mk make ip_stratixiv_flash]
+#
+# [mk make tech_flash]
+#
+# [mk make remu]
+#
+# [mk make ip_stratixiv_pll]
+#
+# [mk make ip_stratixiv_pll_clk25]
+#
+# [mk make tech_pll]
+#
+# [mk make epcs]
+#
+# [mk make unb1_board]
+#
+# [mk make ip_stratixiv_mac_10g]
+#
+# [mk make tech_mac_10g]
+#
+# [mk make tech_10gbase_r]
+#
+# [mk make ip_stratixiv_phy_xaui]
+#
+# [mk make tech_xaui]
+#
+# [mk make tech_eth_10g]
+#
+# [mk make mdio]
+#
+# [mk make tr_xaui]
+#
+# [mk make tr_10GbE]
+#
+# [mk make compaandesign_com_common_common_1]
+#
+# [mk make compaandesign_com_common_altera_1]
+#
+# [mk make compaandesign_com_common_hwnode_1]
+#
+# [mk make compaandesign_com_ipcore2rtl_functions_1]
+#
+# [mk make compaandesign_com_ipcore2rtl_hwn_nd_3_1]
+#
+# [mk make compaandesign_com_ipcore2rtl_hwn_nd_1_1]
+#
+# [mk make compaandesign_com_ipcore2rtl_register_rf_1]
+#
+# [mk make compaandesign_com_ipcore2rtl_hwn_nd_2_1]
+#
+# [mk make ipcore]
+#
+# [mk make compaan_unb1_10g_app]
+#
+# compaan_unb1_10g_app
+mk all
+# technology ip_stratixiv_ram tech_memory ip_stratixiv_fifo tech_fifo ip_stratixiv_ddio tech_iobuf tst common mm ip_stratixiv_mult tech_mult common_mult easics dp diag uth ppsh i2c diagnostics ip_stratixiv_transceiver tech_transceiver tr_nonbonded ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx tech_tse eth numonyx_m25p128 ip_stratixiv_flash tech_flash remu ip_stratixiv_pll ip_stratixiv_pll_clk25 tech_pll epcs unb1_board ip_stratixiv_mac_10g tech_mac_10g tech_10gbase_r ip_stratixiv_phy_xaui tech_xaui tech_eth_10g mdio tr_xaui tr_10GbE compaandesign_com_common_common_1 compaandesign_com_common_altera_1 compaandesign_com_common_hwnode_1 compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_ipcore2rtl_hwn_nd_3_1 compaandesign_com_ipcore2rtl_hwn_nd_1_1 compaandesign_com_ipcore2rtl_register_rf_1 compaandesign_com_ipcore2rtl_hwn_nd_2_1 ipcore compaan_unb1_10g_app
+# [mk make technology]
+#
+# [mk make ip_stratixiv_ram]
+#
+# [mk make tech_memory]
+#
+# [mk make ip_stratixiv_fifo]
+#
+# [mk make tech_fifo]
+#
+# [mk make ip_stratixiv_ddio]
+#
+# [mk make tech_iobuf]
+#
+# [mk make tst]
+#
+# [mk make common]
+#
+# [mk make mm]
+#
+# [mk make ip_stratixiv_mult]
+#
+# [mk make tech_mult]
+#
+# [mk make common_mult]
+#
+# [mk make easics]
+#
+# [mk make dp]
+#
+# [mk make diag]
+#
+# [mk make uth]
+#
+# [mk make ppsh]
+#
+# [mk make i2c]
+#
+# [mk make diagnostics]
+#
+# [mk make ip_stratixiv_transceiver]
+#
+# [mk make tech_transceiver]
+#
+# [mk make tr_nonbonded]
+#
+# [mk make ip_stratixiv_tse_sgmii_lvds]
+#
+# [mk make ip_stratixiv_tse_sgmii_gx]
+#
+# [mk make tech_tse]
+#
+# [mk make eth]
+#
+# [mk make numonyx_m25p128]
+#
+# [mk make ip_stratixiv_flash]
+#
+# [mk make tech_flash]
+#
+# [mk make remu]
+#
+# [mk make ip_stratixiv_pll]
+#
+# [mk make ip_stratixiv_pll_clk25]
+#
+# [mk make tech_pll]
+#
+# [mk make epcs]
+#
+# [mk make unb1_board]
+#
+# [mk make ip_stratixiv_mac_10g]
+#
+# [mk make tech_mac_10g]
+#
+# [mk make tech_10gbase_r]
+#
+# [mk make ip_stratixiv_phy_xaui]
+#
+# [mk make tech_xaui]
+#
+# [mk make tech_eth_10g]
+#
+# [mk make mdio]
+#
+# [mk make tr_xaui]
+#
+# [mk make tr_10GbE]
+#
+# [mk make compaandesign_com_common_common_1]
+#
+# [mk make compaandesign_com_common_altera_1]
+#
+# [mk make compaandesign_com_common_hwnode_1]
+#
+# [mk make compaandesign_com_ipcore2rtl_functions_1]
+#
+# [mk make compaandesign_com_ipcore2rtl_hwn_nd_3_1]
+#
+# [mk make compaandesign_com_ipcore2rtl_hwn_nd_1_1]
+#
+# [mk make compaandesign_com_ipcore2rtl_register_rf_1]
+#
+# [mk make compaandesign_com_ipcore2rtl_hwn_nd_2_1]
+#
+# [mk make ipcore]
+#
+# [mk make compaan_unb1_10g_app]
+#
+# compaan_unb1_10g_app
+# Load canceled
+mk clean all
+# technology ip_stratixiv_ram tech_memory ip_stratixiv_fifo tech_fifo ip_stratixiv_ddio tech_iobuf tst common mm ip_stratixiv_mult tech_mult common_mult easics dp diag uth ppsh i2c diagnostics ip_stratixiv_transceiver tech_transceiver tr_nonbonded ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx tech_tse eth numonyx_m25p128 ip_stratixiv_flash tech_flash remu ip_stratixiv_pll ip_stratixiv_pll_clk25 tech_pll epcs unb1_board ip_stratixiv_mac_10g tech_mac_10g tech_10gbase_r ip_stratixiv_phy_xaui tech_xaui tech_eth_10g mdio tr_xaui tr_10GbE compaandesign_com_common_common_1 compaandesign_com_common_altera_1 compaandesign_com_common_hwnode_1 compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_ipcore2rtl_hwn_nd_3_1 compaandesign_com_ipcore2rtl_hwn_nd_1_1 compaandesign_com_ipcore2rtl_register_rf_1 compaandesign_com_ipcore2rtl_hwn_nd_2_1 ipcore compaan_unb1_10g_app
+# [mk clean technology]
+# [mk clean ip_stratixiv_ram]
+# [mk clean tech_memory]
+# [mk clean ip_stratixiv_fifo]
+# [mk clean tech_fifo]
+# [mk clean ip_stratixiv_ddio]
+# [mk clean tech_iobuf]
+# [mk clean tst]
+# [mk clean common]
+# [mk clean mm]
+# [mk clean ip_stratixiv_mult]
+# [mk clean tech_mult]
+# [mk clean common_mult]
+# [mk clean easics]
+# [mk clean dp]
+# [mk clean diag]
+# [mk clean uth]
+# [mk clean ppsh]
+# [mk clean i2c]
+# [mk clean diagnostics]
+# [mk clean ip_stratixiv_transceiver]
+# [mk clean tech_transceiver]
+# [mk clean tr_nonbonded]
+# [mk clean ip_stratixiv_tse_sgmii_lvds]
+# [mk clean ip_stratixiv_tse_sgmii_gx]
+# [mk clean tech_tse]
+# [mk clean eth]
+# [mk clean numonyx_m25p128]
+# [mk clean ip_stratixiv_flash]
+# [mk clean tech_flash]
+# [mk clean remu]
+# [mk clean ip_stratixiv_pll]
+# [mk clean ip_stratixiv_pll_clk25]
+# [mk clean tech_pll]
+# [mk clean epcs]
+# [mk clean unb1_board]
+# [mk clean ip_stratixiv_mac_10g]
+# [mk clean tech_mac_10g]
+# [mk clean tech_10gbase_r]
+# [mk clean ip_stratixiv_phy_xaui]
+# [mk clean tech_xaui]
+# [mk clean tech_eth_10g]
+# [mk clean mdio]
+# [mk clean tr_xaui]
+# [mk clean tr_10GbE]
+# [mk clean compaandesign_com_common_common_1]
+# [mk clean compaandesign_com_common_altera_1]
+# [mk clean compaandesign_com_common_hwnode_1]
+# [mk clean compaandesign_com_ipcore2rtl_functions_1]
+# [mk clean compaandesign_com_ipcore2rtl_hwn_nd_3_1]
+# [mk clean compaandesign_com_ipcore2rtl_hwn_nd_1_1]
+# [mk clean compaandesign_com_ipcore2rtl_register_rf_1]
+# [mk clean compaandesign_com_ipcore2rtl_hwn_nd_2_1]
+# [mk clean ipcore]
+# [mk clean compaan_unb1_10g_app]
+# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is shoshkov@dop233.
+# compaan_unb1_10g_app
+mk compile all
+# technology ip_stratixiv_ram tech_memory ip_stratixiv_fifo tech_fifo ip_stratixiv_ddio tech_iobuf tst common mm ip_stratixiv_mult tech_mult common_mult easics dp diag uth ppsh i2c diagnostics ip_stratixiv_transceiver tech_transceiver tr_nonbonded ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx tech_tse eth numonyx_m25p128 ip_stratixiv_flash tech_flash remu ip_stratixiv_pll ip_stratixiv_pll_clk25 tech_pll epcs unb1_board ip_stratixiv_mac_10g tech_mac_10g tech_10gbase_r ip_stratixiv_phy_xaui tech_xaui tech_eth_10g mdio tr_xaui tr_10GbE compaandesign_com_common_common_1 compaandesign_com_common_altera_1 compaandesign_com_common_hwnode_1 compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_ipcore2rtl_hwn_nd_3_1 compaandesign_com_ipcore2rtl_hwn_nd_1_1 compaandesign_com_ipcore2rtl_register_rf_1 compaandesign_com_ipcore2rtl_hwn_nd_2_1 ipcore compaan_unb1_10g_app
+# [mk compile technology]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project technology
+# Compile of technology_pkg.vhd was successful with warnings.
+# Compile of technology_select_pkg.vhd was successful.
+# 2 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_ram]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_ram
+# Compile of ip_stratixiv_ram_crwk_crw.vhd was successful.
+# Compile of ip_stratixiv_ram_crw_crw.vhd was successful.
+# Compile of ip_stratixiv_ram_cr_cw.vhd was successful.
+# Compile of ip_stratixiv_ram_r_w.vhd was successful.
+# Compile of ip_stratixiv_rom_r.vhd was successful.
+# 5 compiles, 0 failed with no errors.
+# [mk compile tech_memory]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_memory
+# Compile of tech_memory_component_pkg.vhd was successful.
+# Compile of tech_memory_ram_cr_cw.vhd was successful.
+# Compile of tech_memory_ram_crw_crw.vhd was successful.
+# Compile of tech_memory_ram_crwk_crw.vhd was successful.
+# Compile of tech_memory_ram_r_w.vhd was successful.
+# Compile of tech_memory_rom_r.vhd was successful.
+# 6 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_fifo]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_fifo
+# Compile of ip_stratixiv_fifo_dc_mixed_widths.vhd was successful.
+# Compile of ip_stratixiv_fifo_dc.vhd was successful.
+# Compile of ip_stratixiv_fifo_sc.vhd was successful.
+# 3 compiles, 0 failed with no errors.
+# [mk compile tech_fifo]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_fifo
+# Compile of tech_fifo_component_pkg.vhd was successful.
+# Compile of tech_fifo_sc.vhd was successful.
+# Compile of tech_fifo_dc.vhd was successful.
+# Compile of tech_fifo_dc_mixed_widths.vhd was successful.
+# 4 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_ddio]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_ddio
+# Compile of ip_stratixiv_ddio_in.vhd was successful.
+# Compile of ip_stratixiv_ddio_out.vhd was successful.
+# 2 compiles, 0 failed with no errors.
+# [mk compile tech_iobuf]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_iobuf
+# Compile of tech_iobuf_component_pkg.vhd was successful.
+# Compile of tech_iobuf_ddio_in.vhd was successful.
+# Compile of tech_iobuf_ddio_out.vhd was successful.
+# 3 compiles, 0 failed with no errors.
+# [mk compile tst]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tst
+# Compile of tst_output.vhd was successful.
+# Compile of tst_input.vhd was successful with warnings.
+# 2 compiles, 0 failed with no errors.
+# [mk compile common]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project common
+# Compile of common_pkg.vhd was successful.
+# Compile of common_str_pkg.vhd was successful.
+# Compile of common_mem_pkg.vhd was successful.
+# Compile of common_field_pkg.vhd was successful.
+# Compile of common_lfsr_sequences_pkg.vhd was successful.
+# Compile of common_interface_layers_pkg.vhd was successful.
+# Compile of common_network_layers_pkg.vhd was successful.
+# Compile of common_network_total_header_pkg.vhd was successful.
+# Compile of common_components_pkg.vhd was successful.
+# Compile of common_async.vhd was successful.
+# Compile of common_async_slv.vhd was successful.
+# Compile of common_areset.vhd was successful.
+# Compile of common_acapture.vhd was successful.
+# Compile of common_acapture_slv.vhd was successful.
+# Compile of common_pipeline.vhd was successful.
+# Compile of common_pipeline_sl.vhd was successful.
+# Compile of common_pipeline_integer.vhd was successful.
+# Compile of common_pipeline_natural.vhd was successful.
+# Compile of common_ram_crw_crw_ratio.vhd was successful.
+# Compile of common_ram_cr_cw_ratio.vhd was successful.
+# Compile of common_ram_crw_crw.vhd was successful.
+# Compile of common_ram_crw_cr.vhd was successful.
+# Compile of common_ram_crw_cw.vhd was successful.
+# Compile of common_ram_cr_cw.vhd was successful.
+# Compile of common_ram_rw_rw.vhd was successful.
+# Compile of common_ram_r_w.vhd was successful.
+# Compile of common_rom.vhd was successful.
+# Compile of common_fifo_sc.vhd was successful.
+# Compile of common_fifo_dc.vhd was successful.
+# Compile of common_fifo_dc_mixed_widths.vhd was successful.
+# Compile of common_ddio_in.vhd was successful.
+# Compile of common_ddio_out.vhd was successful.
+# Compile of common_wideband_data_scope.vhd was successful.
+# Compile of common_iobuf_in.vhd was successful.
+# Compile of common_inout.vhd was successful.
+# Compile of common_fanout.vhd was successful.
+# Compile of common_fanout_tree.vhd was successful.
+# Compile of common_ddreg.vhd was successful.
+# Compile of common_ddreg_slv.vhd was successful.
+# Compile of common_evt.vhd was successful.
+# Compile of common_flank_to_pulse.vhd was successful.
+# Compile of common_toggle.vhd was successful.
+# Compile of common_switch.vhd was successful.
+# Compile of common_request.vhd was successful.
+# Compile of common_pulse_extend.vhd was successful.
+# Compile of common_spulse.vhd was successful.
+# Compile of common_counter.vhd was successful.
+# Compile of common_init.vhd was successful.
+# Compile of common_pulser.vhd was successful.
+# Compile of common_pulser_us_ms_s.vhd was successful.
+# Compile of common_led_controller.vhd was successful.
+# Compile of common_debounce.vhd was successful.
+# Compile of common_frame_busy.vhd was successful.
+# Compile of common_stable_delayed.vhd was successful.
+# Compile of common_stable_monitor.vhd was successful.
+# Compile of common_interval_monitor.vhd was successful.
+# Compile of common_clock_active_detector.vhd was successful.
+# Compile of common_clock_phase_detector.vhd was successful.
+# Compile of common_resize.vhd was successful.
+# Compile of common_round.vhd was successful.
+# Compile of common_requantize.vhd was successful.
+# Compile of common_clip.vhd was successful.
+# Compile of common_pipeline_symbol.vhd was successful.
+# Compile of common_shiftreg.vhd was successful.
+# Compile of common_shiftreg_symbol.vhd was successful.
+# Compile of common_add_symbol.vhd was successful.
+# Compile of common_select_symbol.vhd was successful.
+# Compile of common_select_m_symbols.vhd was successful.
+# Compile of common_reorder_symbol.vhd was successful.
+# Compile of common_multiplexer.vhd was successful.
+# Compile of common_demultiplexer.vhd was successful.
+# Compile of common_transpose_symbol.vhd was successful.
+# Compile of common_transpose.vhd was successful.
+# Compile of common_peak.vhd was successful.
+# Compile of common_complex_round.vhd was successful.
+# Compile of common_add_sub.vhd was successful.
+# Compile of common_complex_add_sub.vhd was successful.
+# Compile of common_accumulate.vhd was successful.
+# Compile of common_int2float.vhd was successful.
+# Compile of common_adder_staged.vhd was successful.
+# Compile of common_adder_tree.vhd was successful.
+# Compile of common_adder_tree_a_recursive.vhd was successful.
+# Compile of common_adder_tree_a_str.vhd was successful.
+# Compile of common_operation.vhd was successful.
+# Compile of common_operation_tree.vhd was successful.
+# Compile of common_rl_decrease.vhd was successful.
+# Compile of common_rl_increase.vhd was successful.
+# Compile of common_rl_register.vhd was successful.
+# Compile of common_fifo_rd.vhd was successful.
+# Compile of common_blockreg.vhd was successful.
+# Compile of common_fifo_dc_lock_control.vhd was successful.
+# Compile of common_mem_mux.vhd was successful.
+# Compile of common_mem_demux.vhd was successful.
+# Compile of common_reg_cross_domain.vhd was successful.
+# Compile of common_reg_r_w.vhd was successful.
+# Compile of common_reg_r_w_dc.vhd was successful.
+# Compile of common_interleave.vhd was successful.
+# Compile of common_deinterleave.vhd was successful.
+# Compile of common_reinterleave.vhd was successful.
+# Compile of common_paged_reg.vhd was successful.
+# Compile of common_paged_ram_crw_crw.vhd was successful.
+# Compile of common_paged_ram_rw_rw.vhd was successful.
+# Compile of common_paged_ram_r_w.vhd was successful.
+# Compile of common_paged_ram_ww_rr.vhd was successful.
+# Compile of common_paged_ram_w_rr.vhd was successful.
+# Compile of common_zip.vhd was successful.
+# Compile of common_duty_cycle.vhd was successful.
+# Compile of common_bit_delay.vhd was successful.
+# Compile of common_delay.vhd was successful.
+# Compile of common_shiftram.vhd was successful.
+# Compile of mms_common_reg.vhd was successful.
+# Compile of mms_common_stable_monitor.vhd was successful.
+# Compile of avs_common_mm.vhd was successful.
+# Compile of avs_common_mm_irq.vhd was successful.
+# Compile of avs_common_mm_readlatency0.vhd was successful.
+# Compile of avs_common_mm_readlatency2.vhd was successful.
+# Compile of avs_common_reg_r_w.vhd was successful.
+# Compile of tb_common_pkg.vhd was successful.
+# Compile of tb_common_mem_pkg.vhd was successful.
+# Compile of tb_common_acapture.vhd was successful.
+# Compile of tb_common_add_sub.vhd was successful.
+# Compile of tb_common_adder_tree.vhd was successful.
+# Compile of tb_common_async.vhd was successful.
+# Compile of tb_common_clock_phase_detector.vhd was successful.
+# Compile of tb_common_counter.vhd was successful.
+# Compile of tb_common_ddreg.vhd was successful.
+# Compile of tb_common_debounce.vhd was successful.
+# Compile of tb_common_duty_cycle.vhd was successful.
+# Compile of tb_common_fanout_tree.vhd was successful.
+# Compile of tb_common_fifo_dc_mixed_widths.vhd was successful.
+# Compile of tb_common_fifo_rd.vhd was successful.
+# Compile of tb_common_flank_to_pulse.vhd was successful.
+# Compile of tb_common_init.vhd was successful.
+# Compile of tb_common_int2float.vhd was successful.
+# Compile of tb_common_led_controller.vhd was successful.
+# Compile of tb_common_mem_mux.vhd was successful.
+# Compile of tb_common_multiplexer.vhd was successful.
+# Compile of tb_common_operation_tree.vhd was successful.
+# Compile of tb_common_paged_ram_crw_crw.vhd was successful.
+# Compile of tb_common_paged_ram_ww_rr.vhd was successful.
+# Compile of tb_common_pulse_extend.vhd was successful.
+# Compile of tb_common_pulser.vhd was successful.
+# Compile of tb_common_pulser_us_ms_s.vhd was successful.
+# Compile of tb_common_reg_cross_domain.vhd was successful.
+# Compile of tb_common_reinterleave.vhd was successful.
+# Compile of tb_common_reorder_symbol.vhd was successful.
+# Compile of tb_common_rl.vhd was successful.
+# Compile of tb_common_rl_register.vhd was successful.
+# Compile of tb_common_select_m_symbols.vhd was successful.
+# Compile of tb_common_shiftram.vhd was successful.
+# Compile of tb_common_shiftreg.vhd was successful.
+# Compile of tb_common_spulse.vhd was successful.
+# Compile of tb_common_switch.vhd was successful.
+# Compile of tb_common_toggle.vhd was successful.
+# Compile of tb_common_transpose.vhd was successful.
+# Compile of tb_common_transpose_symbol.vhd was successful.
+# Compile of tb_common_zip.vhd was successful.
+# Compile of tb_requantize.vhd was successful.
+# Compile of tb_resize.vhd was successful.
+# Compile of tb_round.vhd was successful.
+# Compile of tb_tb_common_add_sub.vhd was successful.
+# Compile of tb_tb_common_adder_tree.vhd was successful.
+# Compile of tb_tb_common_fanout_tree.vhd was successful.
+# Compile of tb_tb_common_multiplexer.vhd was successful.
+# Compile of tb_tb_common_operation_tree.vhd was successful.
+# Compile of tb_tb_common_paged_ram_ww_rr.vhd was successful.
+# Compile of tb_tb_common_reinterleave.vhd was successful.
+# Compile of tb_tb_common_reorder_symbol.vhd was successful.
+# Compile of tb_tb_common_rl.vhd was successful.
+# Compile of tb_tb_common_rl_register.vhd was successful.
+# Compile of tb_tb_common_transpose.vhd was successful.
+# 171 compiles, 0 failed with no errors.
+# [mk compile mm]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project mm
+# Compile of mm_fields.vhd was successful.
+# Compile of mm_file_pkg.vhd was successful.
+# Compile of mm_file_unb_pkg.vhd was successful.
+# Compile of timeout.v was successful.
+# Compile of wbs_arbiter.v was successful.
+# Compile of mm_arbiter.vhd was successful.
+# Compile of mm_file.vhd was successful.
+# Compile of dummy_reg.vhd was successful.
+# Compile of tb_mm_file.vhd was successful.
+# 9 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_mult]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_mult
+# Compile of ip_stratixiv_mult.vhd was successful.
+# Compile of ip_stratixiv_mult_rtl.vhd was successful.
+# Compile of ip_stratixiv_complex_mult.vhd was successful.
+# Compile of ip_stratixiv_complex_mult_rtl.vhd was successful.
+# Compile of ip_stratixiv_mult_add2_rtl.vhd was successful.
+# Compile of ip_stratixiv_mult_add4_rtl.vhd was successful.
+# 6 compiles, 0 failed with no errors.
+# [mk compile tech_mult]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_mult
+# Compile of tech_mult_component_pkg.vhd was successful.
+# Compile of tech_complex_mult.vhd was successful.
+# Compile of tech_mult_add2.vhd was successful.
+# Compile of tech_mult_add4.vhd was successful.
+# Compile of tech_mult.vhd was successful.
+# 5 compiles, 0 failed with no errors.
+# [mk compile common_mult]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project common_mult
+# Compile of common_mult.vhd was successful.
+# Compile of common_mult_add2.vhd was successful.
+# Compile of common_mult_add4.vhd was successful.
+# Compile of common_complex_mult.vhd was successful.
+# Compile of common_complex_mult_add.vhd was successful.
+# Compile of tb_common_mult.vhd was successful.
+# Compile of tb_common_mult_add2.vhd was successful.
+# Compile of tb_common_complex_mult.vhd was successful.
+# Compile of tb_tb_common_mult.vhd was successful.
+# 9 compiles, 0 failed with no errors.
+# [mk compile easics]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project easics
+# Compile of PCK_CRC64_D8.vhd was successful.
+# Compile of PCK_CRC64_D16.vhd was successful.
+# Compile of PCK_CRC64_D32.vhd was successful.
+# Compile of PCK_CRC64_D64.vhd was successful.
+# Compile of PCK_CRC64_D72.vhd was successful.
+# Compile of PCK_CRC64_D128.vhd was successful.
+# Compile of PCK_CRC64_D256.vhd was successful.
+# Compile of PCK_CRC64_D512.vhd was successful.
+# Compile of PCK_CRC64_D1024.vhd was successful.
+# Compile of PCK_CRC32_D4.vhd was successful.
+# Compile of PCK_CRC32_D8.vhd was successful.
+# Compile of PCK_CRC32_D9.vhd was successful.
+# Compile of PCK_CRC32_D10.vhd was successful.
+# Compile of PCK_CRC32_D16.vhd was successful.
+# Compile of PCK_CRC32_D18.vhd was successful.
+# Compile of PCK_CRC32_D20.vhd was successful.
+# Compile of PCK_CRC32_D24.vhd was successful.
+# Compile of PCK_CRC32_D32.vhd was successful.
+# Compile of PCK_CRC32_D36.vhd was successful.
+# Compile of PCK_CRC32_D40.vhd was successful.
+# Compile of PCK_CRC32_D48.vhd was successful.
+# Compile of PCK_CRC32_D64.vhd was successful.
+# Compile of PCK_CRC32_D72.vhd was successful.
+# Compile of PCK_CRC32_D128.vhd was successful.
+# Compile of PCK_CRC32_D256.vhd was successful.
+# Compile of PCK_CRC32_D512.vhd was successful.
+# Compile of PCK_CRC32_D1024.vhd was successful.
+# Compile of PCK_CRC16_D4.vhd was successful.
+# Compile of PCK_CRC16_D8.vhd was successful.
+# Compile of PCK_CRC16_D9.vhd was successful.
+# Compile of PCK_CRC16_D10.vhd was successful.
+# Compile of PCK_CRC16_D16.vhd was successful.
+# Compile of PCK_CRC16_D18.vhd was successful.
+# Compile of PCK_CRC16_D20.vhd was successful.
+# Compile of PCK_CRC16_D24.vhd was successful.
+# Compile of PCK_CRC16_D32.vhd was successful.
+# Compile of PCK_CRC16_D36.vhd was successful.
+# Compile of PCK_CRC16_D48.vhd was successful.
+# Compile of PCK_CRC16_D64.vhd was successful.
+# Compile of PCK_CRC16_D72.vhd was successful.
+# Compile of PCK_CRC8_D4.vhd was successful.
+# Compile of PCK_CRC8_D8.vhd was successful.
+# Compile of PCK_CRC8_D9.vhd was successful.
+# Compile of PCK_CRC8_D10.vhd was successful.
+# Compile of PCK_CRC8_D16.vhd was successful.
+# Compile of PCK_CRC8_D18.vhd was successful.
+# Compile of PCK_CRC8_D20.vhd was successful.
+# Compile of PCK_CRC8_D24.vhd was successful.
+# Compile of PCK_CRC8_D32.vhd was successful.
+# Compile of PCK_CRC8_D36.vhd was successful.
+# Compile of PCK_CRC8_D48.vhd was successful.
+# Compile of PCK_CRC8_D64.vhd was successful.
+# Compile of PCK_CRC8_D72.vhd was successful.
+# Compile of RAD_CRC20_D20.vhd was successful.
+# Compile of RAD_CRC16_D16.vhd was successful.
+# Compile of RAD_CRC18_D18.vhd was successful.
+# 56 compiles, 0 failed with no errors.
+# [mk compile dp]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project dp
+# Compile of dp_stream_pkg.vhd was successful.
+# Compile of dp_example_dut.vhd was successful.
+# Compile of dp_packetizing_pkg.vhd was successful.
+# Compile of dp_packet_pkg.vhd was successful.
+# Compile of dp_eop_extend.vhd was successful.
+# Compile of dp_validate.vhd was successful.
+# Compile of dp_ready.vhd was successful.
+# Compile of dp_frame_busy.vhd was successful.
+# Compile of dp_frame_busy_arr.vhd was successful.
+# Compile of dp_xonoff.vhd was successful.
+# Compile of dp_xonoff_reg.vhd was successful.
+# Compile of mms_dp_xonoff.vhd was successful.
+# Compile of dp_flush.vhd was successful.
+# Compile of dp_latency_increase.vhd was successful.
+# Compile of dp_latency_adapter.vhd was successful.
+# Compile of dp_latency_fifo.vhd was successful.
+# Compile of dp_hold_data.vhd was successful.
+# Compile of dp_hold_ctrl.vhd was successful.
+# Compile of dp_hold_input.vhd was successful.
+# Compile of dp_pipeline.vhd was successful.
+# Compile of dp_pipeline_arr.vhd was successful.
+# Compile of dp_pipeline_ready.vhd was successful.
+# Compile of dp_paged_sop_eop_reg.vhd was successful.
+# Compile of dp_packet_detect.vhd was successful.
+# Compile of dp_shiftreg.vhd was successful.
+# Compile of dp_fifo_info.vhd was successful.
+# Compile of dp_fifo_core.vhd was successful.
+# Compile of dp_fifo_sc.vhd was successful.
+# Compile of dp_fifo_fill.vhd was successful with warnings.
+# Compile of dp_fifo_fill_reg.vhd was successful.
+# Compile of dp_fifo_dc.vhd was successful.
+# Compile of dp_fifo_dc_mixed_widths.vhd was successful.
+# Compile of dp_fifo_fill_core.vhd was successful.
+# Compile of dp_fifo_fill_sc.vhd was successful.
+# Compile of dp_fifo_fill_dc.vhd was successful.
+# Compile of dp_fifo_to_mm.vhd was successful.
+# Compile of dp_fifo_to_mm_reg.vhd was successful.
+# Compile of dp_fifo_from_mm.vhd was successful.
+# Compile of dp_fifo_from_mm_reg.vhd was successful.
+# Compile of mms_dp_fifo_to_mm.vhd was successful.
+# Compile of mms_dp_fifo_from_mm.vhd was successful.
+# Compile of mms_dp_fifo_fill.vhd was successful.
+# Compile of dp_mux.vhd was successful with warnings.
+# Compile of dp_demux.vhd was successful with warnings.
+# Compile of dp_loopback.vhd was successful.
+# Compile of dp_concat.vhd was successful.
+# Compile of dp_split.vhd was successful.
+# Compile of dp_split_reg.vhd was successful.
+# Compile of mms_dp_split.vhd was successful.
+# Compile of dp_pad_insert.vhd was successful.
+# Compile of dp_pad_remove.vhd was successful.
+# Compile of dp_block_gen.vhd was successful.
+# Compile of dp_bsn_source.vhd was successful.
+# Compile of dp_bsn_source_reg.vhd was successful.
+# Compile of mms_dp_bsn_source.vhd was successful.
+# Compile of dp_bsn_scheduler.vhd was successful.
+# Compile of dp_bsn_scheduler_reg.vhd was successful.
+# Compile of mms_dp_bsn_scheduler.vhd was successful.
+# Compile of dp_bsn_delay.vhd was successful.
+# Compile of dp_bsn_align.vhd was successful.
+# Compile of dp_bsn_align_reg.vhd was successful.
+# Compile of mms_dp_bsn_align.vhd was successful.
+# Compile of dp_frame_rd.vhd was successful.
+# Compile of dp_frame_fsn.vhd was successful.
+# Compile of dp_frame_tx.vhd was successful.
+# Compile of dp_frame_rx.vhd was successful.
+# Compile of dp_frame_status.vhd was successful.
+# Compile of dp_frame.vhd was successful.
+# Compile of dp_unframe.vhd was successful.
+# Compile of dp_repack_legacy.vhd was successful.
+# Compile of dp_repack_data.vhd was successful.
+# Compile of dp_frame_repack.vhd was successful.
+# Compile of dp_frame_scheduler.vhd was successful.
+# Compile of dp_packet_enc.vhd was successful.
+# Compile of dp_packet_enc_channel_lo.vhd was successful.
+# Compile of dp_packet_dec.vhd was successful.
+# Compile of dp_packet_dec_channel_lo.vhd was successful.
+# Compile of dp_gap.vhd was successful.
+# Compile of dp_mon.vhd was successful.
+# Compile of dp_bsn_monitor.vhd was successful.
+# Compile of dp_bsn_monitor_reg.vhd was successful.
+# Compile of mms_dp_bsn_monitor.vhd was successful.
+# Compile of dp_distribute.vhd was successful.
+# Compile of dp_ram_from_mm.vhd was successful.
+# Compile of dp_ram_from_mm_reg.vhd was successful.
+# Compile of mms_dp_ram_from_mm.vhd was successful.
+# Compile of dp_ram_to_mm.vhd was successful.
+# Compile of dp_hdr_insert.vhd was successful.
+# Compile of dp_hdr_remove.vhd was successful.
+# Compile of dp_tail_remove.vhd was successful.
+# Compile of dp_frame_remove.vhd was successful.
+# Compile of dp_throttle.vhd was successful.
+# Compile of dp_throttle_reg.vhd was successful.
+# Compile of mms_dp_throttle.vhd was successful.
+# Compile of dp_packet_merge.vhd was successful.
+# Compile of mms_dp_packet_merge.vhd was successful.
+# Compile of dp_packet_unmerge.vhd was successful.
+# Compile of dp_offload_tx_legacy.vhd was successful.
+# Compile of dp_offload_tx_len_calc.vhd was successful.
+# Compile of dp_field_blk.vhd was successful.
+# Compile of dp_offload_tx.vhd was successful.
+# Compile of dp_offload_rx.vhd was successful.
+# Compile of dp_deinterleave.vhd was successful.
+# Compile of dp_reinterleave.vhd was successful.
+# Compile of dp_requantize.vhd was successful.
+# Compile of dp_wideband_sp_arr_scope.vhd was successful.
+# Compile of dp_wideband_wb_arr_scope.vhd was successful.
+# Compile of dp_throttle_sop.vhd was successful.
+# Compile of dp_barrel_shift.vhd was successful.
+# Compile of dp_shiftram.vhd was successful.
+# Compile of dp_src_out_timer.vhd was successful.
+# Compile of dp_sync_checker.vhd was successful.
+# Compile of dp_stream_player.vhd was successful.
+# Compile of dp_sosi_recorder.vhd was successful with warnings.
+# Compile of tb_dp_pkg.vhd was successful.
+# Compile of dp_phy_link.vhd was successful.
+# Compile of dp_stream_stimuli.vhd was successful.
+# Compile of dp_stream_verify.vhd was successful.
+# Compile of tb_dp_block_gen.vhd was successful.
+# Compile of tb_dp_bsn_align.vhd was successful.
+# Compile of tb_mms_dp_bsn_align.vhd was successful.
+# Compile of tb_dp_bsn_monitor.vhd was successful.
+# Compile of tb_dp_bsn_source.vhd was successful.
+# Compile of tb_dp_demux.vhd was successful.
+# Compile of tb2_dp_demux.vhd was successful.
+# Compile of tb3_dp_demux.vhd was successful.
+# Compile of tb_dp_concat.vhd was successful.
+# Compile of tb_dp_deinterleave.vhd was successful.
+# Compile of tb_dp_distribute.vhd was successful.
+# Compile of tb_dp_example_dut.vhd was successful.
+# Compile of tb_dp_fifo_fill.vhd was successful.
+# Compile of tb_mms_dp_fifo_fill.vhd was successful with warnings.
+# Compile of tb_dp_fifo_fill_sc.vhd was successful.
+# Compile of tb_dp_fifo_info.vhd was successful.
+# Compile of tb_dp_fifo_dc.vhd was successful.
+# Compile of tb_dp_fifo_dc_mixed_widths.vhd was successful.
+# Compile of tb_dp_fifo_sc.vhd was successful.
+# Compile of tb_dp_fifo_to_mm.vhd was successful.
+# Compile of tb_dp_flush.vhd was successful.
+# Compile of tb_dp_gap.vhd was successful.
+# Compile of tb_dp_hdr_insert_remove.vhd was successful.
+# Compile of tb_dp_frame_rd.vhd was successful.
+# Compile of tb_dp_frame_scheduler.vhd was successful.
+# Compile of tb_dp_latency_adapter.vhd was successful.
+# Compile of tb_dp_latency_fifo.vhd was successful.
+# Compile of tb_dp_mux.vhd was successful with warnings.
+# Compile of tb2_dp_mux.vhd was successful.
+# Compile of tb3_dp_mux.vhd was successful.
+# Compile of tb_dp_packet.vhd was successful.
+# Compile of tb_dp_packet_merge.vhd was successful.
+# Compile of tb_dp_packetizing.vhd was successful.
+# Compile of tb_dp_pad_insert_remove.vhd was successful.
+# Compile of tb_dp_pipeline.vhd was successful.
+# Compile of tb_dp_pipeline_ready.vhd was successful.
+# Compile of tb_dp_reinterleave.vhd was successful.
+# Compile of tb_dp_repack_legacy.vhd was successful.
+# Compile of tb_dp_repack_data.vhd was successful.
+# Compile of tb_dp_shiftreg.vhd was successful.
+# Compile of tb_dp_split.vhd was successful.
+# Compile of tb_dp_tail_remove.vhd was successful.
+# Compile of tb_dp_throttle_sop.vhd was successful.
+# Compile of tb_mms_dp_fields.vhd was successful.
+# Compile of tb_dp_sync_checker.vhd was successful.
+# Compile of tb_dp_xonoff.vhd was successful.
+# Compile of tb_mms_dp_xonoff.vhd was successful.
+# Compile of tb_tb_dp_block_gen.vhd was successful.
+# Compile of tb_tb_dp_bsn_align.vhd was successful.
+# Compile of tb_tb_dp_concat.vhd was successful.
+# Compile of tb_tb_dp_demux.vhd was successful.
+# Compile of tb_tb2_dp_demux.vhd was successful.
+# Compile of tb_tb3_dp_demux.vhd was successful.
+# Compile of tb_tb_dp_distribute.vhd was successful.
+# Compile of tb_tb_dp_example_dut.vhd was successful.
+# Compile of tb_tb_dp_flush.vhd was successful.
+# Compile of tb_tb_dp_fifo_info.vhd was successful.
+# Compile of tb_tb_dp_fifo_sc.vhd was successful.
+# Compile of tb_tb_dp_fifo_fill.vhd was successful.
+# Compile of tb_tb_dp_fifo_fill_sc.vhd was successful.
+# Compile of tb_tb_dp_fifo_dc.vhd was successful.
+# Compile of tb_tb_dp_fifo_dc_mixed_widths.vhd was successful.
+# Compile of tb_tb_dp_frame_scheduler.vhd was successful.
+# Compile of tb_tb_dp_latency_fifo.vhd was successful.
+# Compile of tb_tb_dp_mux.vhd was successful.
+# Compile of tb_tb2_dp_mux.vhd was successful.
+# Compile of tb_tb3_dp_mux.vhd was successful.
+# Compile of tb_tb_dp_pad_insert_remove.vhd was successful.
+# Compile of tb_tb_dp_packetizing.vhd was successful.
+# Compile of tb_tb_dp_packet.vhd was successful.
+# Compile of tb_tb_dp_packet_merge.vhd was successful.
+# Compile of tb_tb_dp_pipeline.vhd was successful.
+# Compile of tb_tb_dp_pipeline_ready.vhd was successful.
+# Compile of tb_tb_dp_repack_data.vhd was successful.
+# Compile of tb_tb_dp_split.vhd was successful.
+# Compile of tb_tb_dp_sync_checker.vhd was successful.
+# Compile of tb_tb_tb_dp_backpressure.vhd was successful.
+# 195 compiles, 0 failed with no errors.
+# [mk compile diag]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project diag
+# Compile of diag_pkg.vhd was successful.
+# Compile of diag_bypass.vhd was successful.
+# Compile of diag_tx_seq.vhd was successful.
+# Compile of diag_tx_frm.vhd was successful.
+# Compile of diag_rx_seq.vhd was successful.
+# Compile of diag_frm_generator.vhd was successful.
+# Compile of diag_frm_monitor.vhd was successful.
+# Compile of mms_diag_tx_seq.vhd was successful.
+# Compile of mms_diag_rx_seq.vhd was successful.
+# Compile of diag_wg.vhd was successful.
+# Compile of diag_wg_wideband.vhd was successful.
+# Compile of diag_wg_wideband_reg.vhd was successful.
+# Compile of mms_diag_wg_wideband.vhd was successful.
+# Compile of diag_data_buffer.vhd was successful.
+# Compile of mms_diag_data_buffer.vhd was successful.
+# Compile of diag_block_gen.vhd was successful.
+# Compile of diag_block_gen_reg.vhd was successful.
+# Compile of mms_diag_block_gen.vhd was successful.
+# Compile of tb_diag_pkg.vhd was successful.
+# Compile of tb_diag_wg.vhd was successful.
+# Compile of tb_diag_wg_wideband.vhd was successful.
+# Compile of tb_diag_tx_seq.vhd was successful.
+# Compile of tb_diag_rx_seq.vhd was successful.
+# Compile of tb_tb_diag_rx_seq.vhd was successful.
+# Compile of tb_diag_tx_frm.vhd was successful.
+# Compile of tb_diag_frm_generator.vhd was successful.
+# Compile of tb_diag_frm_monitor.vhd was successful.
+# Compile of tb_mms_diag_seq.vhd was successful.
+# Compile of tb_tb_mms_diag_seq.vhd was successful.
+# Compile of tb_diag_block_gen.vhd was successful.
+# Compile of tb_mms_diag_block_gen.vhd was successful.
+# Compile of tb_tb_mms_diag_block_gen.vhd was successful.
+# Compile of tb_diag_regression.vhd was successful.
+# 33 compiles, 0 failed with no errors.
+# [mk compile uth]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project uth
+# Compile of uth_pkg.vhd was successful.
+# Compile of uth_tx.vhd was successful.
+# Compile of uth_rx_tlen.vhd was successful.
+# Compile of uth_rx.vhd was successful.
+# Compile of uth_terminal_tx.vhd was successful.
+# Compile of uth_terminal_rx.vhd was successful.
+# Compile of uth_terminal_bidir.vhd was successful.
+# Compile of tb_uth.vhd was successful.
+# Compile of tb_uth_dp_packet.vhd was successful.
+# Compile of tb_uth_terminals.vhd was successful.
+# Compile of tb_tb_uth.vhd was successful.
+# Compile of tb_tb_uth_dp_packet.vhd was successful.
+# Compile of tb_tb_uth_terminals.vhd was successful.
+# Compile of tb_tb_tb_uth_regression.vhd was successful.
+# 14 compiles, 0 failed with no errors.
+# [mk compile ppsh]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ppsh
+# Compile of ppsh.vhd was successful.
+# Compile of mm_ppsh.vhd was successful.
+# Compile of ppsh_reg.vhd was successful.
+# Compile of mms_ppsh.vhd was successful.
+# Compile of tb_ppsh.vhd was successful.
+# Compile of tb_mms_ppsh.vhd was successful.
+# 6 compiles, 0 failed with no errors.
+# [mk compile i2c]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project i2c
+# Compile of i2c_pkg.vhd was successful.
+# Compile of i2c_bit.vhd was successful.
+# Compile of i2c_bit_scl_sense.vhd was successful.
+# Compile of i2c_byte.vhd was successful.
+# Compile of i2c_smbus_pkg.vhd was successful.
+# Compile of i2c_smbus.vhd was successful.
+# Compile of i2c_list_ctrl.vhd was successful.
+# Compile of i2c_commander_pkg.vhd was successful.
+# Compile of i2c_dev_max1617_pkg.vhd was successful.
+# Compile of i2c_dev_max6652_pkg.vhd was successful.
+# Compile of i2c_dev_ltc4260_pkg.vhd was successful.
+# Compile of i2c_dev_unb_pkg.vhd was successful.
+# Compile of i2c_dev_unb2_pkg.vhd was successful.
+# Compile of i2c_dev_adu_pkg.vhd was successful.
+# Compile of i2c_commander_aduh_pkg.vhd was successful.
+# Compile of i2c_commander_unbh_pkg.vhd was successful.
+# Compile of i2c_commander_reg.vhd was successful with warnings.
+# Compile of i2c_commander_ctrl.vhd was successful.
+# Compile of i2c_commander.vhd was successful.
+# Compile of i2c_mm.vhd was successful.
+# Compile of i2c_master.vhd was successful.
+# Compile of avs_i2c_master.vhd was successful.
+# Compile of i2c_commander_unb2_pmbus_pkg.vhd was successful.
+# Compile of i2c_commander_unb2_sens_pkg.vhd was successful.
+# Compile of i2c_slv_device.vhd was successful.
+# Compile of i2cslave.vhd was successful.
+# Compile of dev_pca9555.vhd was successful.
+# Compile of dev_max1618.vhd was successful.
+# Compile of dev_max6652.vhd was successful.
+# Compile of dev_ltc4260.vhd was successful.
+# Compile of dev_pmbus.vhd was successful.
+# Compile of tb_i2cslave.vhd was successful.
+# Compile of tb_i2c_master.vhd was successful.
+# Compile of tb_avs_i2c_master.vhd was successful.
+# Compile of tb_i2c_commander.vhd was successful.
+# Compile of tb_tb_i2c_commander.vhd was successful.
+# 36 compiles, 0 failed with no errors.
+# [mk compile diagnostics]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project diagnostics
+# Compile of diagnostics.vhd was successful.
+# Compile of diagnostics_reg.vhd was successful.
+# Compile of mm_rx_logger_trig.vhd was successful.
+# Compile of mm_rx_logger_reg.vhd was successful.
+# Compile of mm_rx_logger.vhd was successful.
+# Compile of mm_tx_framer_reg.vhd was successful.
+# Compile of mm_tx_framer.vhd was successful.
+# Compile of mms_diagnostics.vhd was successful.
+# Compile of tb_diagnostics_trnb_pkg.vhd was successful.
+# Compile of tb_diagnostics.vhd was successful.
+# Compile of tb_mm_tx_framer.vhd was successful.
+# 11 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_transceiver]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_transceiver
+# Compile of ip_stratixiv_gxb_reconfig_v91_2.vhd was successful.
+# Compile of ip_stratixiv_gxb_reconfig_v91_4.vhd was successful.
+# Compile of ip_stratixiv_gxb_reconfig_v91_8.vhd was successful.
+# Compile of ip_stratixiv_gxb_reconfig_v91_12.vhd was successful.
+# Compile of ip_stratixiv_gxb_reconfig_v91.vhd was successful.
+# Compile of ip_stratixiv_gxb_reconfig_v101_4.vhd was successful.
+# Compile of ip_stratixiv_gxb_reconfig_v101_8.vhd was successful.
+# Compile of ip_stratixiv_gxb_reconfig_v101_12.vhd was successful.
+# Compile of ip_stratixiv_gxb_reconfig_v101.vhd was successful.
+# Compile of ip_stratixiv_gxb_reconfig_v111_4.vhd was successful.
+# Compile of ip_stratixiv_gxb_reconfig_v111_16.vhd was successful.
+# Compile of ip_stratixiv_gxb_reconfig_v111.vhd was successful.
+# Compile of ip_stratixiv_hssi_gx_32b_generic.vhd was successful.
+# Compile of ip_stratixiv_hssi_tx_32b_generic.vhd was successful.
+# Compile of ip_stratixiv_hssi_rx_32b_generic.vhd was successful.
+# Compile of ip_stratixiv_hssi_gx_16b.vhd was successful.
+# Compile of ip_stratixiv_hssi_tx_16b.vhd was successful.
+# Compile of ip_stratixiv_hssi_rx_16b.vhd was successful.
+# 18 compiles, 0 failed with no errors.
+# [mk compile tech_transceiver]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_transceiver
+# Compile of sim_transceiver_serializer.vhd was successful.
+# Compile of sim_transceiver_deserializer.vhd was successful.
+# Compile of sim_transceiver_gx.vhd was successful.
+# Compile of tech_transceiver_component_pkg.vhd was successful.
+# Compile of tech_transceiver_rx_order.vhd was successful.
+# Compile of tech_transceiver_rx_align.vhd was successful.
+# Compile of tech_transceiver_rx_rst.vhd was successful.
+# Compile of tech_transceiver_tx_align.vhd was successful.
+# Compile of tech_transceiver_tx_rst.vhd was successful.
+# Compile of tech_transceiver_gx_stratixiv.vhd was successful.
+# Compile of tech_transceiver_gx.vhd was successful.
+# Compile of tech_transceiver_arria10_48.vhd was successful.
+# Compile of tb_sim_transceiver_serdes.vhd was successful.
+# 13 compiles, 0 failed with no errors.
+# [mk compile tr_nonbonded]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tr_nonbonded
+# Compile of tr_nonbonded.vhd was successful.
+# Compile of tr_nonbonded_reg.vhd was successful.
+# Compile of mms_tr_nonbonded.vhd was successful.
+# Compile of tb_tr_nonbonded.vhd was successful.
+# Compile of tb_tb_tr_nonbonded.vhd was successful.
+# 5 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_tse_sgmii_lvds]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_tse_sgmii_lvds
+# Compile of ip_stratixiv_tse_sgmii_lvds.vho was successful with warnings.
+# Compile of tb_ip_stratixiv_tse_sgmii_lvds.vhd was successful.
+# 2 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_tse_sgmii_gx]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_tse_sgmii_gx
+# Compile of ip_stratixiv_tse_sgmii_gx.vho was successful with warnings.
+# [mk compile tech_tse]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_tse
+# Compile of tech_tse_component_pkg.vhd was successful.
+# Compile of tech_tse_pkg.vhd was successful.
+# Compile of tech_tse_stratixiv.vhd was successful.
+# Compile of tech_tse_arria10.vhd was successful.
+# Compile of tech_tse_arria10_e3sge3.vhd was successful.
+# Compile of tech_tse.vhd was successful.
+# Compile of tb_tech_tse_pkg.vhd was successful.
+# Compile of tb_tech_tse.vhd was successful.
+# 8 compiles, 0 failed with no errors.
+# [mk compile eth]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project eth
+# Compile of eth_pkg.vhd was successful.
+# Compile of eth_checksum.vhd was successful.
+# Compile of eth_hdr_store.vhd was successful.
+# Compile of eth_hdr_status.vhd was successful.
+# Compile of eth_hdr_ctrl.vhd was successful.
+# Compile of eth_hdr.vhd was successful.
+# Compile of eth_crc_ctrl.vhd was successful.
+# Compile of eth_crc_word.vhd was successful.
+# Compile of eth_mm_registers.vhd was successful.
+# Compile of eth_mm_reg_frame.vhd was successful.
+# Compile of eth_frm_discard.vhd was successful.
+# Compile of eth_udp_channel.vhd was successful.
+# Compile of eth_buffer.vhd was successful.
+# Compile of eth_control.vhd was successful.
+# Compile of eth_ihl_to_20.vhd was successful.
+# Compile of eth.vhd was successful.
+# Compile of tb_eth_checksum.vhd was successful.
+# Compile of tb_eth_crc_ctrl.vhd was successful.
+# Compile of tb_eth_hdr.vhd was successful.
+# Compile of tb_eth.vhd was successful.
+# Compile of tb_tb_eth.vhd was successful.
+# Compile of tb_eth_udp_offload.vhd was successful.
+# Compile of tb_eth_ihl_to_20.vhd was successful.
+# Compile of tb_tb_tb_eth_regression.vhd was successful.
+# 24 compiles, 0 failed with no errors.
+# [mk compile numonyx_m25p128]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project numonyx_m25p128
+# Compile of StringLib.vhd was successful.
+# Compile of def.vhd was successful.
+# Compile of CUIcommandData.vhd was successful.
+# Compile of data.vhd was successful.
+# Compile of BlockLib.vhd was successful.
+# Compile of TimingData.vhd was successful.
+# Compile of MemoryLib.vhd was successful.
+# Compile of M25P128.vhd was successful with warnings.
+# 8 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_flash]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_flash
+# Compile of ip_stratixiv_asmi_parallel.vhd was successful.
+# Compile of ip_stratixiv_remote_update.vhd was successful.
+# 2 compiles, 0 failed with no errors.
+# [mk compile tech_flash]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_flash
+# Compile of tech_flash_component_pkg.vhd was successful.
+# Compile of tech_flash_asmi_parallel.vhd was successful.
+# Compile of tech_flash_remote_update.vhd was successful.
+# 3 compiles, 0 failed with no errors.
+# [mk compile remu]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project remu
+# Compile of remu_reg.vhd was successful.
+# Compile of mms_remu.vhd was successful.
+# 2 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_pll]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_pll
+# Compile of ip_stratixiv_pll_clk200.vhd was successful.
+# Compile of ip_stratixiv_pll_clk200_p6.vhd was successful.
+# 2 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_pll_clk25]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_pll_clk25
+# Compile of ip_stratixiv_pll_clk25.vhd was successful.
+# [mk compile tech_pll]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_pll
+# Compile of tech_pll_component_pkg.vhd was successful.
+# Compile of tech_pll_clk200.vhd was successful.
+# Compile of tech_pll_clk200_p6.vhd was successful.
+# Compile of tech_pll_xgmii_mac_clocks.vhd was successful.
+# Compile of tech_pll_clk25.vhd was successful.
+# Compile of tech_pll_clk125.vhd was successful.
+# 6 compiles, 0 failed with no errors.
+# [mk compile epcs]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project epcs
+# Compile of epcs_reg.vhd was successful.
+# Compile of mms_epcs.vhd was successful.
+# Compile of tb_mms_epcs.vhd was successful.
+# 3 compiles, 0 failed with no errors.
+# [mk compile unb1_board]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project unb1_board
+# Compile of unb1_board_pkg.vhd was successful.
+# Compile of unb1_board_system_info.vhd was successful.
+# Compile of unb1_board_system_info_reg.vhd was successful.
+# Compile of mms_unb1_board_system_info.vhd was successful.
+# Compile of unb1_board_clk_rst.vhd was successful.
+# Compile of unb1_board_clk200_pll.vhd was successful.
+# Compile of unb1_board_clk25_pll.vhd was successful.
+# Compile of unb1_board_wdi_extend.vhd was successful.
+# Compile of unb1_board_node_ctrl.vhd was successful.
+# Compile of unb1_board_sens_ctrl.vhd was successful.
+# Compile of unb1_board_sens.vhd was successful.
+# Compile of unb1_board_sens_reg.vhd was successful.
+# Compile of mms_unb1_board_sens.vhd was successful.
+# Compile of unb1_board_wdi_reg.vhd was successful.
+# Compile of ctrl_unb1_board.vhd was successful.
+# Compile of unb1_board_front_io.vhd was successful.
+# Compile of unb1_board_mesh_io.vhd was successful.
+# Compile of unb1_board_mesh_reorder_tx.vhd was successful.
+# Compile of unb1_board_mesh_reorder_rx.vhd was successful.
+# Compile of unb1_board_mesh_reorder_bidir.vhd was successful.
+# Compile of unb1_board_mesh_uth_terminals_bidir.vhd was successful.
+# Compile of unb1_board_back_io.vhd was successful.
+# Compile of unb1_board_back_select.vhd was successful.
+# Compile of unb1_board_back_reorder.vhd was successful.
+# Compile of unb1_board_back_uth_terminals_bidir.vhd was successful.
+# Compile of unb1_board_terminals_mesh.vhd was successful.
+# Compile of unb1_board_terminals_back.vhd was successful.
+# Compile of unb1_board_peripherals_pkg.vhd was successful.
+# Compile of node_unb1_fn_terminal_db.vhd was successful.
+# Compile of tb_unb1_board_pkg.vhd was successful.
+# Compile of tb_mms_unb1_board_sens.vhd was successful.
+# Compile of tb_unb1_board_clk200_pll.vhd was successful.
+# Compile of tb_unb1_board_node_ctrl.vhd was successful.
+# Compile of unb1_board_mesh_model_sosi.vhd was successful.
+# Compile of unb1_board_mesh_model_siso.vhd was successful.
+# Compile of unb1_board_mesh_model_sl.vhd was successful.
+# Compile of unb1_board_back_model_sosi.vhd was successful.
+# Compile of unb1_board_back_model_sl.vhd was successful.
+# Compile of tb_unb1_board_mesh_reorder_bidir.vhd was successful.
+# Compile of tb_tb_tb_unb1_board_regression.vhd was successful.
+# 40 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_mac_10g]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_mac_10g
+# /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+# [mk execute ip_stratixiv_mac_10g]
+# do /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+# /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package altera_mf_components
+# -- Compiling entity altera_avalon_st_handshake_clock_crosser_0001
+# -- Compiling architecture rtl of altera_avalon_st_handshake_clock_crosser_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_multiplexer_0003
+# -- Compiling architecture rtl of altera_merlin_multiplexer_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_demultiplexer_0006
+# -- Compiling architecture rtl of altera_merlin_demultiplexer_0006
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_demultiplexer_0005
+# -- Compiling architecture rtl of altera_merlin_demultiplexer_0005
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_multiplexer_0002
+# -- Compiling architecture rtl of altera_merlin_multiplexer_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_demultiplexer_0004
+# -- Compiling architecture rtl of altera_merlin_demultiplexer_0004
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_demultiplexer_0003
+# -- Compiling architecture rtl of altera_merlin_demultiplexer_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_multiplexer_0001
+# -- Compiling architecture rtl of altera_merlin_multiplexer_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_demultiplexer_0002
+# -- Compiling architecture rtl of altera_merlin_demultiplexer_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_demultiplexer_0001
+# -- Compiling architecture rtl of altera_merlin_demultiplexer_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_reset_controller_0001
+# -- Compiling architecture rtl of altera_reset_controller_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_traffic_limiter_0003
+# -- Compiling architecture rtl of altera_merlin_traffic_limiter_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_traffic_limiter_0002
+# -- Compiling architecture rtl of altera_merlin_traffic_limiter_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_traffic_limiter_0001
+# -- Compiling architecture rtl of altera_merlin_traffic_limiter_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_router_0006
+# -- Compiling architecture rtl of altera_merlin_router_0006
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_router_0005
+# -- Compiling architecture rtl of altera_merlin_router_0005
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_router_0004
+# -- Compiling architecture rtl of altera_merlin_router_0004
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_router_0003
+# -- Compiling architecture rtl of altera_merlin_router_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_router_0002
+# -- Compiling architecture rtl of altera_merlin_router_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_router_0001
+# -- Compiling architecture rtl of altera_merlin_router_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0017
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0017
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_master_agent_0003
+# -- Compiling architecture rtl of altera_merlin_master_agent_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0016
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0016
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0015
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0015
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0014
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0014
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0013
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0013
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0012
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0012
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0011
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0011
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0010
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0010
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0009
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0009
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0008
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0008
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0007
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0007
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_master_agent_0002
+# -- Compiling architecture rtl of altera_merlin_master_agent_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0006
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0006
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0005
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0005
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_sc_fifo_0004
+# -- Compiling architecture rtl of altera_avalon_sc_fifo_0004
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0004
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0004
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_sc_fifo_0003
+# -- Compiling architecture rtl of altera_avalon_sc_fifo_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0003
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0002
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_sc_fifo_0002
+# -- Compiling architecture rtl of altera_avalon_sc_fifo_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_sc_fifo_0001
+# -- Compiling architecture rtl of altera_avalon_sc_fifo_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity altera_merlin_slave_agent_0001
+# -- Compiling architecture rtl of altera_merlin_slave_agent_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_master_agent_0001
+# -- Compiling architecture rtl of altera_merlin_master_agent_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_slave_translator_0007
+# -- Compiling architecture rtl of altera_merlin_slave_translator_0007
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_slave_translator_0006
+# -- Compiling architecture rtl of altera_merlin_slave_translator_0006
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_slave_translator_0005
+# -- Compiling architecture rtl of altera_merlin_slave_translator_0005
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_slave_translator_0004
+# -- Compiling architecture rtl of altera_merlin_slave_translator_0004
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_slave_translator_0003
+# -- Compiling architecture rtl of altera_merlin_slave_translator_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_slave_translator_0002
+# -- Compiling architecture rtl of altera_merlin_slave_translator_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_master_translator_0003
+# -- Compiling architecture rtl of altera_merlin_master_translator_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_slave_translator_0001
+# -- Compiling architecture rtl of altera_merlin_slave_translator_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_master_translator_0002
+# -- Compiling architecture rtl of altera_merlin_master_translator_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity timing_adapter_0011
+# -- Compiling architecture rtl of timing_adapter_0011
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package altera_mf_components
+# -- Loading package sgate_pack
+# -- Compiling entity altera_avalon_dc_fifo_0002
+# -- Compiling architecture rtl of altera_avalon_dc_fifo_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity timing_adapter_0010
+# -- Compiling architecture rtl of timing_adapter_0010
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package altera_mf_components
+# -- Loading package sgate_pack
+# -- Compiling entity altera_avalon_dc_fifo_0001
+# -- Compiling architecture rtl of altera_avalon_dc_fifo_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity timing_adapter_0009
+# -- Compiling architecture rtl of timing_adapter_0009
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_st_splitter_0005
+# -- Compiling architecture rtl of altera_avalon_st_splitter_0005
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity timing_adapter_0008
+# -- Compiling architecture rtl of timing_adapter_0008
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_st_delay_0002
+# -- Compiling architecture rtl of altera_avalon_st_delay_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity error_adapter_0003
+# -- Compiling architecture rtl of error_adapter_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_st_delay_0001
+# -- Compiling architecture rtl of altera_avalon_st_delay_0001
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module altera_avalon_st_pipeline_stage
+#
+# Top level modules:
+# altera_avalon_st_pipeline_stage
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module altera_avalon_st_pipeline_base
+#
+# Top level modules:
+# altera_avalon_st_pipeline_base
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity timing_adapter_0007
+# -- Compiling architecture rtl of timing_adapter_0007
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_st_splitter_0004
+# -- Compiling architecture rtl of altera_avalon_st_splitter_0004
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity timing_adapter_0006
+# -- Compiling architecture rtl of timing_adapter_0006
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity timing_adapter_0005
+# -- Compiling architecture rtl of timing_adapter_0005
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_st_splitter_0003
+# -- Compiling architecture rtl of altera_avalon_st_splitter_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity timing_adapter_0004
+# -- Compiling architecture rtl of timing_adapter_0004
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_st_splitter_0002
+# -- Compiling architecture rtl of altera_avalon_st_splitter_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity timing_adapter_0003
+# -- Compiling architecture rtl of timing_adapter_0003
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity timing_adapter_0002
+# -- Compiling architecture rtl of timing_adapter_0002
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity error_adapter_0002
+# -- Compiling architecture rtl of error_adapter_0002
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module altera_avalon_st_pipeline_stage
+#
+# Top level modules:
+# altera_avalon_st_pipeline_stage
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module altera_avalon_st_pipeline_base
+#
+# Top level modules:
+# altera_avalon_st_pipeline_base
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity timing_adapter_0001
+# -- Compiling architecture rtl of timing_adapter_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_st_splitter_0001
+# -- Compiling architecture rtl of altera_avalon_st_splitter_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_st_pipeline_stage_0001
+# -- Compiling architecture rtl of altera_avalon_st_pipeline_stage_0001
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package sgate_pack
+# -- Compiling entity multiplexer_0001
+# -- Compiling architecture rtl of multiplexer_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity error_adapter_0001
+# -- Compiling architecture rtl of error_adapter_0001
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_avalon_mm_bridge_0001
+# -- Compiling architecture rtl of altera_avalon_mm_bridge_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Compiling entity altera_merlin_master_translator_0001
+# -- Compiling architecture rtl of altera_merlin_master_translator_0001
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity ip_stratixiv_mac_10g
+# -- Compiling architecture rtl of ip_stratixiv_mac_10g
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control
+# -- Compiling architecture rtl of ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control
+# -- Compiling architecture rtl of ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity ip_stratixiv_mac_10g_tx_eth_frame_decoder
+# -- Compiling architecture rtl of ip_stratixiv_mac_10g_tx_eth_frame_decoder
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity ip_stratixiv_mac_10g_rx_eth_frame_decoder
+# -- Compiling architecture rtl of ip_stratixiv_mac_10g_rx_eth_frame_decoder
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity ip_stratixiv_mac_10g_tx_eth_crc_inserter
+# -- Compiling architecture rtl of ip_stratixiv_mac_10g_tx_eth_crc_inserter
+# Model Technology ModelSim SE-64 vcom 6.6c Compiler 2010.08 Aug 23 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity ip_stratixiv_mac_10g_rx_eth_crc_checker
+# -- Compiling architecture rtl of ip_stratixiv_mac_10g_rx_eth_crc_checker
+# [mk compile tech_mac_10g]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_mac_10g
+# Compile of tech_mac_10g_component_pkg.vhd was successful.
+# Compile of tech_mac_10g_stratixiv.vhd was successful.
+# Compile of tech_mac_10g_arria10.vhd was successful.
+# Compile of tech_mac_10g_arria10_e3sge3.vhd was successful.
+# Compile of tech_mac_10g.vhd was successful.
+# Compile of tb_tech_mac_10g_pkg.vhd was successful.
+# Compile of tb_tech_mac_10g_setup.vhd was successful.
+# Compile of tb_tech_mac_10g_transmitter.vhd was successful.
+# Compile of tb_tech_mac_10g_receiver.vhd was successful.
+# Compile of tb_tech_mac_10g_link_connect.vhd was successful.
+# Compile of tb_tech_mac_10g_verify_rx_at_eop.vhd was successful.
+# Compile of tb_tech_mac_10g_verify_rx_pkt_cnt.vhd was successful.
+# Compile of tb_tech_mac_10g_simulation_end.vhd was successful.
+# Compile of tb_tech_mac_10g.vhd was successful.
+# Compile of tb_tb_tech_mac_10g.vhd was successful.
+# 15 compiles, 0 failed with no errors.
+# [mk compile tech_10gbase_r]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_10gbase_r
+# Compile of sim_10gbase_r.vhd was successful.
+# Compile of tech_10gbase_r_component_pkg.vhd was successful.
+# Compile of tech_10gbase_r_arria10.vhd was successful.
+# Compile of tech_10gbase_r_arria10_e3sge3.vhd was successful.
+# Compile of tech_10gbase_r.vhd was successful.
+# Compile of tb_tech_10gbase_r.vhd was successful.
+# 6 compiles, 0 failed with no errors.
+# [mk compile ip_stratixiv_phy_xaui]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ip_stratixiv_phy_xaui
+# /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+# [mk execute ip_stratixiv_phy_xaui]
+# do /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+# /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package altera_xcvr_functions
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package altera_xcvr_xaui_sv_unit
+# -- Compiling module altera_xcvr_xaui
+#
+# Top level modules:
+# altera_xcvr_xaui
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package hxaui_csr_h
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module hxaui_csr
+# -- Importing package hxaui_csr_h
+#
+# Top level modules:
+# hxaui_csr
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_mgmt2dec_phyreconfig
+#
+# Top level modules:
+# alt_xcvr_mgmt2dec_phyreconfig
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_mgmt2dec_xaui
+#
+# Top level modules:
+# alt_xcvr_mgmt2dec_xaui
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_pma_ch_controller_tgx
+#
+# Top level modules:
+# alt_pma_ch_controller_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_pma_controller_tgx
+#
+# Top level modules:
+# alt_pma_controller_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_reset_ctrl_lego
+#
+# Top level modules:
+# alt_reset_ctrl_lego
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_reset_ctrl_tgx_cdrauto
+#
+# Top level modules:
+# alt_reset_ctrl_tgx_cdrauto
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_resync
+#
+# Top level modules:
+# alt_xcvr_resync
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package alt_xcvr_csr_common_h
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_csr_common
+# -- Importing package alt_xcvr_csr_common_h
+#
+# Top level modules:
+# alt_xcvr_csr_common
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package alt_xcvr_csr_pcs8g_h
+# -- Importing package alt_xcvr_csr_common_h
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_csr_pcs8g
+# -- Importing package alt_xcvr_csr_common_h
+# -- Importing package alt_xcvr_csr_pcs8g_h
+#
+# Top level modules:
+# alt_xcvr_csr_pcs8g
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module csr_mux
+# -- Compiling module csr_indexed_write_mux
+# -- Compiling module csr_indexed_read_only_reg
+#
+# Top level modules:
+# csr_indexed_write_mux
+# csr_indexed_read_only_reg
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_mgmt2dec
+#
+# Top level modules:
+# alt_xcvr_mgmt2dec
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module altera_wait_generate
+#
+# Top level modules:
+# altera_wait_generate
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module hxaui_alt4gxb_alt4gxb_dksa
+# -- Compiling module hxaui_alt4gxb
+#
+# Top level modules:
+# hxaui_alt4gxb
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module hxaui
+#
+# Top level modules:
+# hxaui
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module siv_xcvr_xaui
+#
+# Top level modules:
+# siv_xcvr_xaui
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package alt_xcvr_reconfig_h
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_siv
+#
+# Top level modules:
+# alt_xcvr_reconfig_siv
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_analog
+#
+# Top level modules:
+# alt_xcvr_reconfig_analog
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_analog_tgx
+#
+# Top level modules:
+# alt_xcvr_reconfig_analog_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_offset_cancellation
+#
+# Top level modules:
+# alt_xcvr_reconfig_offset_cancellation
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_offset_cancellation_tgx
+#
+# Top level modules:
+# alt_xcvr_reconfig_offset_cancellation_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_eyemon_tgx
+#
+# Top level modules:
+# alt_xcvr_reconfig_eyemon_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_dfe_tgx
+#
+# Top level modules:
+# alt_xcvr_reconfig_dfe_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_basic_tgx
+#
+# Top level modules:
+# alt_xcvr_reconfig_basic_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_mutex_acq
+#
+# Top level modules:
+# alt_mutex_acq
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_dprio
+#
+# Top level modules:
+# alt_dprio
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_arbiter
+#
+# Top level modules:
+# alt_xcvr_arbiter
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_m2s
+#
+# Top level modules:
+# alt_xcvr_m2s
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# do /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+# /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package altera_xcvr_functions
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package alt_pma_functions
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package altera_xcvr_xaui_sv_unit
+# -- Compiling module altera_xcvr_xaui
+#
+# Top level modules:
+# altera_xcvr_xaui
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package hxaui_csr_h
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module hxaui_csr
+# -- Importing package hxaui_csr_h
+#
+# Top level modules:
+# hxaui_csr
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_mgmt2dec_phyreconfig
+#
+# Top level modules:
+# alt_xcvr_mgmt2dec_phyreconfig
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_mgmt2dec_xaui
+#
+# Top level modules:
+# alt_xcvr_mgmt2dec_xaui
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_pma_ch_controller_tgx
+#
+# Top level modules:
+# alt_pma_ch_controller_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_pma_controller_tgx
+#
+# Top level modules:
+# alt_pma_controller_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_reset_ctrl_lego
+#
+# Top level modules:
+# alt_reset_ctrl_lego
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_reset_ctrl_tgx_cdrauto
+#
+# Top level modules:
+# alt_reset_ctrl_tgx_cdrauto
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_resync
+#
+# Top level modules:
+# alt_xcvr_resync
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package alt_xcvr_csr_common_h
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_csr_common
+# -- Importing package alt_xcvr_csr_common_h
+#
+# Top level modules:
+# alt_xcvr_csr_common
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package alt_xcvr_csr_pcs8g_h
+# -- Importing package alt_xcvr_csr_common_h
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_csr_pcs8g
+# -- Importing package alt_xcvr_csr_common_h
+# -- Importing package alt_xcvr_csr_pcs8g_h
+#
+# Top level modules:
+# alt_xcvr_csr_pcs8g
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module csr_mux
+# -- Compiling module csr_indexed_write_mux
+# -- Compiling module csr_indexed_read_only_reg
+#
+# Top level modules:
+# csr_indexed_write_mux
+# csr_indexed_read_only_reg
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_mgmt2dec
+#
+# Top level modules:
+# alt_xcvr_mgmt2dec
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module altera_wait_generate
+#
+# Top level modules:
+# altera_wait_generate
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module sxaui
+#
+# Top level modules:
+# sxaui
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module siv_xcvr_low_latency_phy_nr
+#
+# Top level modules:
+# siv_xcvr_low_latency_phy_nr
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module siv_xcvr_xaui
+#
+# Top level modules:
+# siv_xcvr_xaui
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt4gxb
+#
+# Top level modules:
+# alt4gxb
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling package alt_xcvr_reconfig_h
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# --none--
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_siv
+#
+# Top level modules:
+# alt_xcvr_reconfig_siv
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_analog
+#
+# Top level modules:
+# alt_xcvr_reconfig_analog
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_analog_tgx
+#
+# Top level modules:
+# alt_xcvr_reconfig_analog_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_offset_cancellation
+#
+# Top level modules:
+# alt_xcvr_reconfig_offset_cancellation
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_offset_cancellation_tgx
+#
+# Top level modules:
+# alt_xcvr_reconfig_offset_cancellation_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_eyemon_tgx
+#
+# Top level modules:
+# alt_xcvr_reconfig_eyemon_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_dfe_tgx
+#
+# Top level modules:
+# alt_xcvr_reconfig_dfe_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_reconfig_basic_tgx
+#
+# Top level modules:
+# alt_xcvr_reconfig_basic_tgx
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_mutex_acq
+#
+# Top level modules:
+# alt_mutex_acq
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_dprio
+#
+# Top level modules:
+# alt_dprio
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_arbiter
+#
+# Top level modules:
+# alt_xcvr_arbiter
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+# -- Compiling module alt_xcvr_m2s
+#
+# Top level modules:
+# alt_xcvr_m2s
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Model Technology ModelSim SE-64 vlog 6.6c Compiler 2010.08 Aug 23 2010
+#
+# Top level modules:
+# Compile of ip_stratixiv_phy_xaui_0.vhd was successful.
+# Compile of ip_stratixiv_phy_xaui_1.vhd was successful.
+# Compile of ip_stratixiv_phy_xaui_2.vhd was successful.
+# Compile of ip_stratixiv_phy_xaui_soft.vhd was successful.
+# Compile of tb_ip_stratixiv_phy_xaui.vhd was successful.
+# Compile of tb_ip_stratixiv_phy_xaui_ppm.vhd was successful.
+# 6 compiles, 0 failed with no errors.
+# [mk compile tech_xaui]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_xaui
+# Compile of sim_xaui.vhd was successful.
+# Compile of tech_xaui_component_pkg.vhd was successful.
+# Compile of tech_xaui_align_dly.vhd was successful.
+# Compile of tech_xaui_stratixiv.vhd was successful.
+# Compile of tech_xaui.vhd was successful.
+# 5 compiles, 0 failed with no errors.
+# [mk compile tech_eth_10g]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tech_eth_10g
+# Compile of tech_eth_10g_stratixiv.vhd was successful.
+# Compile of tech_eth_10g_arria10.vhd was successful.
+# Compile of tech_eth_10g_arria10_e3sge3.vhd was successful.
+# Compile of tech_eth_10g_clocks.vhd was successful.
+# Compile of tech_eth_10g.vhd was successful.
+# Compile of tb_tech_eth_10g.vhd was successful.
+# Compile of tb_tech_eth_10g_ppm.vhd was successful.
+# Compile of tb_tb_tech_eth_10g.vhd was successful.
+# 8 compiles, 0 failed with no errors.
+# [mk compile mdio]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project mdio
+# Compile of mdio_pkg.vhd was successful.
+# Compile of mdio_mm.vhd was successful.
+# Compile of mdio_ctlr.vhd was successful.
+# Compile of mdio_phy_reg.vhd was successful.
+# Compile of mdio_phy.vhd was successful.
+# Compile of mdio_vitesse_vsc8486_pkg.vhd was successful.
+# Compile of mdio.vhd was successful.
+# Compile of avs_mdio.vhd was successful.
+# Compile of mmd_slave.vhd was successful.
+# Compile of tb_mdio.vhd was successful.
+# Compile of tb_mdio_phy.vhd was successful.
+# Compile of tb_mdio_phy_reg.vhd was successful.
+# Compile of tb_mdio_phy_ctlr.vhd was successful.
+# 13 compiles, 0 failed with no errors.
+# [mk compile tr_xaui]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tr_xaui
+# Compile of tr_xaui_deframer.vhd was successful.
+# Compile of tr_xaui_framer.vhd was successful.
+# Compile of tr_xaui_mdio.vhd was successful.
+# Compile of tr_xaui.vhd was successful.
+# Compile of mms_tr_xaui.vhd was successful.
+# Compile of tb_tr_xaui_deframer.vhd was successful.
+# Compile of tb_tr_xaui_framer.vhd was successful.
+# Compile of tb_tr_xaui.vhd was successful.
+# Compile of tb_tb_tr_xaui.vhd was successful.
+# 9 compiles, 0 failed with no errors.
+# [mk compile tr_10GbE]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project tr_10GbE
+# Compile of tr_10GbE.vhd was successful.
+# Compile of tb_tr_10GbE.vhd was successful.
+# Compile of tb_tb_tr_10GbE.vhd was successful.
+# 3 compiles, 0 failed with no errors.
+# [mk compile compaandesign_com_common_common_1]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project compaandesign_com_common_common_1
+# Compile of hw_node_pkg.vhd was successful.
+# [mk compile compaandesign_com_common_altera_1]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project compaandesign_com_common_altera_1
+# Compile of fsl_v20.vhd was successful.
+# [mk compile compaandesign_com_common_hwnode_1]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project compaandesign_com_common_hwnode_1
+# Compile of controller.vhd was successful.
+# Compile of counter.vhd was successful.
+# Compile of it_mod.vhd was successful.
+# Compile of it_mul.vhd was successful.
+# Compile of parameters.vhd was successful.
+# Compile of read_mux.vhd was successful.
+# Compile of read_mmux.vhd was successful.
+# Compile of write_demux.vhd was successful.
+# 8 compiles, 0 failed with no errors.
+# [mk compile compaandesign_com_ipcore2rtl_functions_1]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project compaandesign_com_ipcore2rtl_functions_1
+# Compile of compaan_outlinedproc0.vhd was successful.
+# Compile of compaan_outlinedproc0_pipeline.vhd was successful.
+# Compile of transformer.vhd was successful.
+# Compile of transformer_pipeline.vhd was successful.
+# Compile of compaan_outlinedproc1.vhd was successful.
+# Compile of compaan_outlinedproc1_pipeline.vhd was successful.
+# 6 compiles, 0 failed with no errors.
+# [mk compile compaandesign_com_ipcore2rtl_hwn_nd_3_1]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project compaandesign_com_ipcore2rtl_hwn_nd_3_1
+# Compile of ipcore2rtl_hwn_nd_3_execution_unit.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_3_eval_logic_rd.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_3_eval_logic_wr.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_3.vhd was successful.
+# 4 compiles, 0 failed with no errors.
+# [mk compile compaandesign_com_ipcore2rtl_hwn_nd_1_1]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project compaandesign_com_ipcore2rtl_hwn_nd_1_1
+# Compile of ipcore2rtl_hwn_nd_1_execution_unit.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_1_eval_logic_rd.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_1_eval_logic_wr.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_1.vhd was successful.
+# 4 compiles, 0 failed with no errors.
+# [mk compile compaandesign_com_ipcore2rtl_register_rf_1]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project compaandesign_com_ipcore2rtl_register_rf_1
+# Compile of register_rf.vhd was successful.
+# [mk compile compaandesign_com_ipcore2rtl_hwn_nd_2_1]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project compaandesign_com_ipcore2rtl_hwn_nd_2_1
+# Compile of ipcore2rtl_hwn_nd_2_execution_unit.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_2_eval_logic_rd.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_2_eval_logic_wr.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_2.vhd was successful.
+# 4 compiles, 0 failed with no errors.
+# [mk compile ipcore]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ipcore
+# Compile of ipcore.vhd was successful.
+# Compile of ipcore2rtl_ed_1_ip_wrapper.vhd was successful.
+# Compile of ipcore2rtl_ed_2_ip_wrapper.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_1_ip_wrapper.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_2_ip_wrapper.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_3_ip_wrapper.vhd was successful.
+# Compile of ipcore2rtl_register_rf_ip_wrapper.vhd was successful.
+# Compile of system_ext_TB.vhd was successful.
+# 8 compiles, 0 failed with no errors.
+# [mk compile compaan_unb1_10g_app]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project compaan_unb1_10g_app
+# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is shoshkov@dop233.
+# Compile of compaan_unb1_10g_pkg.vhd was successful.
+# Compile of compaan_design.vhd was successful.
+# Compile of mmm_compaan_unb1_10g_app.vhd was successful.
+# Compile of compaan_unb1_10g_app.vhd was successful.
+# Compile of mmm_compaan_unb1_10g_bg_db.vhd was successful with warnings.
+# Compile of compaan_unb1_10g_bg_db.vhd was successful.
+# Compile of tb_compaan_unb1_10g_app.vhd was successful.
+# 7 compiles, 0 failed with no errors.
+# compaan_unb1_10g_app
+vsim -do /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/tools/modelsim/commands.do work.tb_compaan_unb1_10g_app
+# vsim -do /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/tools/modelsim/commands.do work.tb_compaan_unb1_10g_app
+# ** Error: (vsim-19) Failed to access library 'compaan_lib' at "compaan_lib".
+# No such file or directory. (errno = ENOENT)
+# ** Note: (vsim-3812) Design is being optimized...
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_sc.vhd(67): (vopt-8617) Possible component instance "u0 : ip_arria10_fifo_sc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_sc.vhd(73): (vopt-8617) Possible component instance "u0 : ip_arria10_e3sge3_fifo_sc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_dc.vhd(69): (vopt-8617) Possible component instance "u0 : ip_arria10_fifo_dc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_dc.vhd(75): (vopt-8617) Possible component instance "u0 : ip_arria10_e3sge3_fifo_dc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_sc.vhd(67): (vopt-8617) Possible component instance "u0 : ip_arria10_fifo_sc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_sc.vhd(73): (vopt-8617) Possible component instance "u0 : ip_arria10_e3sge3_fifo_sc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_dc.vhd(69): (vopt-8617) Possible component instance "u0 : ip_arria10_fifo_dc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_dc.vhd(75): (vopt-8617) Possible component instance "u0 : ip_arria10_e3sge3_fifo_dc" is not bound.
+# ** Warning: nofile(36): in protected region
+# ** Warning: nofile(36): in protected region
+# ** Warning: nofile(36): in protected region
+# ** Warning: nofile(36): in protected region
+# ** Error: /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/base/dp/src/vhdl/dp_fifo_core.vhd(98): (vopt-1144) Value -2 is out of std.standard.natural range 0 to 2147483647.
+# ** Error: /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/base/dp/src/vhdl/dp_fifo_core.vhd(168): (vopt-1144) Value -2 is out of std.standard.natural range 0 to 2147483647.
+# ** Error: Vopt Compiler exiting
+# Error loading design
+mk compile ipcore
+# [mk compile ipcore]
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project ipcore
+# Compile of ipcore.vhd was successful.
+# Compile of ipcore2rtl_ed_1_ip_wrapper.vhd was successful.
+# Compile of ipcore2rtl_ed_2_ip_wrapper.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_1_ip_wrapper.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_2_ip_wrapper.vhd was successful.
+# Compile of ipcore2rtl_hwn_nd_3_ip_wrapper.vhd was successful.
+# Compile of ipcore2rtl_register_rf_ip_wrapper.vhd was successful.
+# Compile of system_ext_TB.vhd was successful.
+# 8 compiles, 0 failed with no errors.
+# reading /home/software/Mentor/modeltech/linux_x86_64/../modelsim.ini
+# Loading project compaan_unb1_10g_app
+# compaan_unb1_10g_app
+vsim -do /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/tools/modelsim/commands.do work.tb_compaan_unb1_10g_app
+# vsim -do /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/tools/modelsim/commands.do work.tb_compaan_unb1_10g_app
+# ** Error: (vsim-19) Failed to access library 'compaan_lib' at "compaan_lib".
+# No such file or directory. (errno = ENOENT)
+# ** Note: (vsim-3812) Design is being optimized...
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_sc.vhd(67): (vopt-8617) Possible component instance "u0 : ip_arria10_fifo_sc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_sc.vhd(73): (vopt-8617) Possible component instance "u0 : ip_arria10_e3sge3_fifo_sc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_dc.vhd(69): (vopt-8617) Possible component instance "u0 : ip_arria10_fifo_dc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_dc.vhd(75): (vopt-8617) Possible component instance "u0 : ip_arria10_e3sge3_fifo_dc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_sc.vhd(67): (vopt-8617) Possible component instance "u0 : ip_arria10_fifo_sc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_sc.vhd(73): (vopt-8617) Possible component instance "u0 : ip_arria10_e3sge3_fifo_sc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_dc.vhd(69): (vopt-8617) Possible component instance "u0 : ip_arria10_fifo_dc" is not bound.
+# ** Warning: [1] /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/fifo/tech_fifo_dc.vhd(75): (vopt-8617) Possible component instance "u0 : ip_arria10_e3sge3_fifo_dc" is not bound.
+# ** Warning: nofile(36): in protected region
+# ** Warning: nofile(36): in protected region
+# ** Warning: nofile(36): in protected region
+# ** Warning: nofile(36): in protected region
+# Loading std.standard
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.math_real(body)
+# Loading common_lib.common_pkg(body)
+# Loading dp_lib.dp_stream_pkg(body)
+# Loading unb1_board_lib.unb1_board_pkg(body)
+# Loading std.textio(body)
+# Loading ieee.std_logic_textio(body)
+# Loading common_lib.tb_common_pkg(body)
+# Loading common_lib.common_str_pkg(body)
+# Loading common_lib.common_mem_pkg(body)
+# Loading common_lib.common_network_layers_pkg(body)
+# Loading common_lib.common_interface_layers_pkg(body)
+# Loading unb1_board_lib.unb1_board_peripherals_pkg(body)
+# Loading tech_tse_lib.tech_tse_pkg(body)
+# Loading eth_lib.eth_pkg(body)
+# Loading diag_lib.diag_pkg(body)
+# Loading common_lib.common_field_pkg(body)
+# Loading technology_lib.technology_pkg(body)
+# Loading work.tb_compaan_unb1_10g_app(tb)#1
+# Loading technology_lib.technology_select_pkg
+# Loading tech_mac_10g_lib.tech_mac_10g_component_pkg(body)
+# Loading i2c_lib.i2c_pkg(body)
+# Loading common_lib.tb_common_mem_pkg(body)
+# Loading common_lib.common_network_total_header_pkg(body)
+# Loading mm_lib.mm_file_pkg(body)
+# Loading mm_lib.mm_file_unb_pkg(body)
+# Loading common_lib.common_lfsr_sequences_pkg(body)
+# Loading dp_lib.tb_dp_pkg(body)
+# Loading tech_tse_lib.tb_tech_tse_pkg(body)
+# Loading work.compaan_unb1_10g_bg_db(str)#1
+# Loading mdio_lib.mdio_pkg(body)
+# Loading mdio_lib.mdio_vitesse_vsc8486_pkg(body)
+# Loading tr_10gbe_lib.tr_10gbe(str)#1
+# Loading dp_lib.dp_fifo_dc(str)#1
+# Loading dp_lib.dp_fifo_core(str)#1
+# Loading tech_fifo_lib.tech_fifo_component_pkg
+# Loading common_lib.common_fifo_dc(str)#1
+# Loading tech_fifo_lib.tech_fifo_dc(str)#1
+# Loading ip_stratixiv_fifo_lib.ip_stratixiv_fifo_dc(syn)#1
+# Loading ieee.std_logic_arith(body)
+# Loading ieee.std_logic_unsigned(body)
+# Loading altera_mf.altera_device_families(body)
+# Loading altera_mf.altera_mf_hint_evaluation(body)
+# Loading altera_mf.dcfifo(behavior)#1
+# Loading altera_mf.dcfifo_mixed_widths(behavior)#1
+# Loading altera_mf.dcfifo_async(behavior)#1
+# Loading altera_mf.dcfifo_dffpipe(behavior)#1
+# Loading altera_mf.dcfifo_dffpipe(behavior)#2
+# Loading altera_mf.dcfifo_dffpipe(behavior)#3
+# Loading altera_mf.dcfifo_fefifo(behavior)#1
+# Loading altera_mf.dcfifo_sync(behavior)#1
+# Loading altera_mf.dcfifo_low_latency(behavior)#1
+# Loading dp_lib.dp_latency_adapter(rtl)#1
+# Loading dp_lib.dp_hold_input(rtl)#1
+# Loading tech_xaui_lib.tech_xaui_component_pkg(body)
+# Loading tech_eth_10g_lib.tech_eth_10g(str)#1
+# Loading ip_stratixiv_mac_10g_lib.ip_stratixiv_mac_10g(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_mm_bridge_0001(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.ip_stratixiv_mac_10g_tx_eth_pkt_backpressure_control(rtl)#1
+# Loading sgate.sgate_pack(body)
+# Loading ip_stratixiv_mac_10g_lib.multiplexer_0001(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_pipeline_stage_0001(rtl)#1
+# Loading sv_std.std
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_pipeline_stage(fast)
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_pipeline_base(fast)
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_pipeline_stage(fast__1)
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_pipeline_base(fast__1)
+# Loading ip_stratixiv_mac_10g_lib.ip_stratixiv_mac_10g_rx_eth_pkt_backpressure_control(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.ip_stratixiv_mac_10g_rx_eth_frame_decoder(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_pipeline_stage(fast__2)
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_pipeline_base(fast__2)
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_pipeline_stage(fast__3)
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_pipeline_base(fast__3)
+# Loading ip_stratixiv_mac_10g_lib.ip_stratixiv_mac_10g_rx_eth_crc_checker(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_pipeline_stage(fast__4)
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_pipeline_base(fast__4)
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_delay_0001(rtl)#1
+# Loading altera_mf.altera_mf_components
+# Loading ieee.std_logic_signed(body)
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_dc_fifo_0001(rtl)#1
+# Loading altera_mf.altera_common_conversion(body)
+# Loading altera_mf.altsyncram(translated)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_dc_fifo_0002(rtl)#1
+# Loading altera_mf.altsyncram(translated)#2
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0001(rtl)#1
+# Loading sgate.oper_add(sim_arch)#2
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_sc_fifo_0001(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_sc_fifo_0002(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0002(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0003(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_sc_fifo_0003(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0004(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_sc_fifo_0004(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0005(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0006(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0007(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0008(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0009(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0010(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0011(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0012(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0013(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0014(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0015(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0016(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_slave_agent_0017(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_router_0003(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_router_0005(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_traffic_limiter_0001(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_traffic_limiter_0002(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_traffic_limiter_0003(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_demultiplexer_0002(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_multiplexer_0001(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_demultiplexer_0003(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_demultiplexer_0004(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_multiplexer_0002(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_demultiplexer_0005(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_demultiplexer_0006(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_merlin_multiplexer_0003(rtl)#1
+# Loading ip_stratixiv_mac_10g_lib.altera_avalon_st_handshake_clock_crosser_0001(rtl)#1
+# Loading dp_lib.dp_latency_increase(rtl)#2
+# Loading dp_lib.dp_latency_adapter(rtl)#2
+# Loading dp_lib.dp_latency_increase(rtl)#3
+# Loading tech_xaui_lib.sim_xaui(wrap)#1
+# Loading common_lib.common_mem_mux(rtl)#1
+# Loading tr_xaui_lib.tr_xaui_mdio(str)#1
+# Loading mdio_lib.mdio_ctlr(rtl)#1
+# Loading common_lib.common_fifo_dc(str)#2
+# Loading diag_lib.mms_diag_block_gen(rtl)#1
+# Loading tech_memory_lib.tech_memory_component_pkg
+# Loading common_lib.common_ram_crw_crw(str)#1
+# Loading tech_memory_lib.tech_memory_ram_crw_crw(str)#1
+# Loading ip_stratixiv_ram_lib.ip_stratixiv_ram_crw_crw(syn)#1
+# Loading altera_mf.altsyncram(translated)#3
+# Loading common_lib.common_pipeline(rtl)#1
+# Loading common_lib.common_pipeline(rtl)#2
+# Loading dp_lib.dp_fifo_sc(str)#3
+# Loading common_lib.common_fifo_sc(str)#3
+# Loading tech_fifo_lib.tech_fifo_sc(str)#3
+# Loading ip_stratixiv_fifo_lib.ip_stratixiv_fifo_sc(syn)#3
+# Loading altera_mf.scfifo(behavior)#4
+# Loading dp_lib.dp_offload_tx(str)#1
+# Loading dp_lib.dp_split(rtl)#1
+# Loading dp_lib.dp_field_blk(str)#1
+# Loading dp_lib.dp_repack_data(str)#1
+# Loading dp_lib.dp_repack_in(rtl)#1
+# Loading dp_lib.dp_repack_out(rtl)#1
+# Loading mm_lib.mm_fields(str)#1
+# Loading common_lib.common_reg_cross_domain(rtl)#2
+# Loading common_lib.common_spulse(rtl)#2
+# Loading dp_lib.dp_fifo_fill(rtl)#2
+# Loading dp_lib.dp_fifo_sc(str)#2
+# Loading dp_lib.dp_fifo_core(str)#4
+# Loading common_lib.common_fifo_sc(str)#2
+# Loading tech_fifo_lib.tech_fifo_sc(str)#2
+# Loading ip_stratixiv_fifo_lib.ip_stratixiv_fifo_sc(syn)#2
+# Loading altera_mf.scfifo(behavior)#2
+# Loading dp_lib.dp_latency_adapter(rtl)#6
+# Loading dp_lib.dp_field_blk(str)#2
+# Loading dp_lib.dp_repack_data(str)#2
+# Loading dp_lib.dp_repack_in(rtl)#2
+# Loading dp_lib.dp_repack_out(rtl)#2
+# Loading dp_lib.dp_tail_remove(str)#1
+# Loading dp_lib.dp_shiftreg(rtl)#1
+# Loading dp_lib.mms_dp_bsn_monitor(str)#1
+# Loading common_lib.common_mem_mux(rtl)#3
+# Loading common_lib.common_reg_r_w_dc(str)#2
+# Loading dp_lib.dp_bsn_monitor(rtl)#1
+# Loading common_lib.common_counter(rtl)#1
+# Loading diag_lib.diag_data_buffer(rtl)#1
+# Loading tech_memory_lib.tech_memory_ram_crwk_crw(str)#1
+# Loading ip_stratixiv_ram_lib.ip_stratixiv_ram_crwk_crw(syn)#1
+# Loading common_lib.common_reg_r_w_dc(str)#3
+# Loading tech_flash_lib.tech_flash_component_pkg(body)
+# Loading tech_pll_lib.tech_pll_component_pkg
+# Loading i2c_lib.i2c_smbus_pkg
+# Loading i2c_lib.i2c_dev_max1617_pkg
+# Loading i2c_lib.i2c_dev_ltc4260_pkg
+# Loading unb1_board_lib.ctrl_unb1_board(str)#1
+# Loading unb1_board_lib.unb1_board_clk200_pll(stratix4)#1
+# Loading tech_pll_lib.tech_pll_clk200(str)#1
+# Loading altera_mf.mf_pllpack(body)
+# Loading altera_mf.altpll(behavior)#1
+# Loading altera_mf.mf_stratixiii_pll(vital_pll)#1
+# Loading altera_mf.altpll(behavior)#3
+# Loading altera_mf.mf_stratixiii_pll(vital_pll)#3
+# Loading unb1_board_lib.unb1_board_node_ctrl(str)#1
+# Loading common_lib.common_counter(rtl)#4
+# Loading unb1_board_lib.mms_unb1_board_system_info(str)#1
+# Loading tech_memory_lib.tech_memory_ram_crw_crw(str)#2
+# Loading ip_stratixiv_flash_lib.ip_stratixiv_remote_update_rmtupdt_jol(rtl)#1
+# Loading lpm.lpm_components
+# Loading lpm.lpm_common_conversion(body)
+# Loading lpm.lpm_counter(lpm_syn)#1
+# Loading lpm.lpm_counter(lpm_syn)#2
+# Loading ieee.vital_timing(body)
+# Loading ieee.vital_primitives(body)
+# Loading stratixiv.stratixiv_atom_pack(body)
+# Loading stratixiv.stratixiv_rublock(architecture_rublock)#1
+# Loading remu_lib.remu_reg(rtl)#1
+# Loading common_lib.common_reg_cross_domain(rtl)#6
+# Loading epcs_lib.mms_epcs(str)#1
+# Loading epcs_lib.epcs_reg(rtl)#1
+# Loading common_lib.common_fifo_dc_mixed_widths(str)#1
+# Loading tech_fifo_lib.tech_fifo_dc_mixed_widths(str)#1
+# Loading ip_stratixiv_fifo_lib.ip_stratixiv_fifo_dc_mixed_widths(syn)#1
+# Loading altera_mf.dcfifo_mixed_widths(behavior)#3
+# Loading dp_lib.dp_latency_adapter(rtl)#7
+# Loading common_lib.common_fifo_dc_mixed_widths(str)#2
+# Loading numonyx_m25p128_lib.def
+# Loading numonyx_m25p128_lib.cuicommanddata(body)
+# Loading numonyx_m25p128_lib.data
+# Loading numonyx_m25p128_lib.timingdata
+# Loading numonyx_m25p128_lib.stringlib(body)
+# Loading numonyx_m25p128_lib.blocklib(body)
+# Loading ip_stratixiv_flash_lib.ip_stratixiv_asmi_parallel_altasmi_parallel_15a2(rtl)#1
+# Loading altera_mf.a_graycounter(behavior)#1
+# Loading altera_mf.a_graycounter(behavior)#2
+# Loading lpm.lpm_compare(lpm_syn)#1
+# Loading lpm.lpm_compare_unsigned(lpm_syn)#1
+# Loading lpm.lpm_counter(lpm_syn)#3
+# Loading altera_mf.scfifo(behavior)#3
+# Loading stratixiv.stratixiv_asmiblock(architecture_asmiblock)#1
+# Loading tech_iobuf_lib.tech_iobuf_component_pkg
+# Loading ppsh_lib.mms_ppsh(str)#1
+# Loading altera_mf.altddio_in(behave)#1
+# Loading common_lib.common_interval_monitor(rtl)#1
+# Loading common_lib.common_pipeline(rtl)#3
+# Loading ppsh_lib.ppsh_reg(rtl)#1
+# Loading i2c_lib.i2c_smbus(rtl)#1
+# Loading work.mmm_compaan_unb1_10g_bg_db(str)#1
+# Loading work.compaan_unb1_10g_app(str)#1
+# Loading dp_lib.dp_fifo_sc(str)#4
+# Loading common_lib.common_fifo_sc(str)#4
+# Loading tech_fifo_lib.tech_fifo_sc(str)#4
+# Loading ip_stratixiv_fifo_lib.ip_stratixiv_fifo_sc(syn)#4
+# Loading altera_mf.scfifo(behavior)#5
+# Loading dp_lib.dp_latency_adapter(rtl)#8
+# Loading work.compaan_design(structure)#1
+# Loading ipcore_lib.ipcore2rtl_hwn_nd_1_ip_wrapper(structure)#1
+# Loading compaandesign_com_common_common_1_lib.hw_node_pkg(body)
+# Loading compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib.ipcore2rtl_hwn_nd_1(rtl)#1
+# Loading compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib.ipcore2rtl_eval_logic_rd_hwn_nd_1(rtl)#1
+# Loading compaandesign_com_common_hwnode_1_lib.counter(rtl)#2
+# Loading ipcore_lib.ipcore2rtl_hwn_nd_2_ip_wrapper(structure)#1
+# Loading compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib.ipcore2rtl_hwn_nd_2(rtl)#1
+# Loading compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib.ipcore2rtl_eval_logic_rd_hwn_nd_2(rtl)#1
+# Loading ipcore_lib.ipcore2rtl_hwn_nd_3_ip_wrapper(structure)#1
+# Loading compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib.ipcore2rtl_hwn_nd_3(rtl)#1
+# Loading compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib.ipcore2rtl_eval_logic_rd_hwn_nd_3(rtl)#1
+# Loading compaandesign_com_common_altera_1_lib.fsl_v20(imp)#1
+# Loading common_lib.common_fifo_sc(str)#5
+# Loading tech_fifo_lib.tech_fifo_sc(str)#5
+# Loading ip_stratixiv_fifo_lib.ip_stratixiv_fifo_sc(syn)#5
+# Loading altera_mf.scfifo(behavior)#6
+# Loading dp_lib.dp_block_gen(rtl)#1
+# Loading work.mmm_compaan_unb1_10g_app(str)#1
+# ** Warning: (vsim-8607) nofile(36): Non-positive replication multiplier inside concat. Replication will be ignored.
+# ** Warning: (vsim-8607) nofile(36): Non-positive replication multiplier inside concat. Replication will be ignored.
+# ** Warning: (vsim-8684) No drivers exist on inout port /tb_compaan_unb1_10g_app/u_lcu/u_front_io/si_fn_0_cntrl(0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/si_fn_0_cntrl(0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on inout port /tb_compaan_unb1_10g_app/u_lcu/u_front_io/si_fn_1_cntrl(2 downto 0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/si_fn_1_cntrl(2 downto 0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on inout port /tb_compaan_unb1_10g_app/u_lcu/u_front_io/si_fn_2_cntrl(2 downto 0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/si_fn_2_cntrl(2 downto 0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on inout port /tb_compaan_unb1_10g_app/u_lcu/u_front_io/si_fn_3_cntrl(2 downto 0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/si_fn_3_cntrl(2 downto 0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.sync, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.sync.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(31), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(31).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(30), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(30).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(29), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(29).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(28), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(28).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(27), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(27).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(26), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(26).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(25), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(25).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(24), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(24).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(23), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(23).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(22), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(22).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(21), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(21).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(20), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(20).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(19), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(19).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(18), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(18).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(17), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(17).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(16), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(16).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(5), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(5).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(4), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(4).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(3), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(3).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(2), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(2).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(1), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(1).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(767), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(767).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(766), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(766).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(765), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(765).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(764), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(764).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(763), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(763).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(762), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(762).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(761), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(761).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(760), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(760).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(759), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(759).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(758), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(758).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(757), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(757).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(756), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(756).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(755), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(755).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(754), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(754).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(753), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(753).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(752), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(752).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(751), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(751).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(750), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(750).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(749), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(749).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(748), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(748).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(747), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(747).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(746), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(746).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(745), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(745).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(744), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(744).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(743), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(743).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(742), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(742).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(741), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(741).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(740), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(740).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(739), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(739).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(738), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(738).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(737), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(737).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(736), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(736).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(735), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(735).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(734), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(734).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(733), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(733).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(732), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(732).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(731), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(731).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(730), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(730).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(729), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(729).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(728), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(728).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(727), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(727).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(726), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(726).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(725), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(725).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(724), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(724).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(723), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(723).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(722), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(722).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(721), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(721).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(720), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(720).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(719), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(719).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(718), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(718).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(717), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(717).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(716), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(716).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(715), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(715).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(714), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(714).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(713), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(713).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(712), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(712).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(711), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(711).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(710), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(710).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(709), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(709).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(708), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(708).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(707), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(707).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(706), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(706).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(705), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(705).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(704), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(704).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(703), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(703).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(702), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(702).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(701), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(701).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(700), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(700).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(699), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(699).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(698), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(698).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(697), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(697).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(696), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(696).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(695), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(695).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(694), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(694).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(693), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(693).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(692), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(692).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(691), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(691).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(690), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(690).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(689), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(689).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(688), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(688).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(687), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(687).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(686), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(686).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(685), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(685).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(684), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(684).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(683), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(683).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(682), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(682).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(681), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(681).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(680), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(680).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(679), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(679).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(678), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(678).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(677), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(677).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(676), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(676).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(675), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(675).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(674), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(674).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(673), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(673).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(672), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(672).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(671), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(671).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(670), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(670).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(669), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(669).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(668), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(668).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(667), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(667).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(666), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(666).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(665), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(665).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(664), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(664).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(663), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(663).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(662), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(662).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(661), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(661).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(660), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(660).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(659), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(659).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(658), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(658).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(657), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(657).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(656), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(656).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(655), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(655).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(654), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(654).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(653), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(653).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(652), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(652).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(651), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(651).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(650), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(650).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(649), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(649).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(648), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(648).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(647), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(647).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(646), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(646).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(645), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(645).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(644), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(644).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(643), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(643).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(642), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(642).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(641), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(641).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(640), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(640).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(639), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(639).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(638), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(638).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(637), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(637).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(636), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(636).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(635), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(635).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(634), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(634).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(633), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(633).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(632), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(632).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(631), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(631).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(630), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(630).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(629), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(629).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(628), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(628).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(627), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(627).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(626), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(626).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(625), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(625).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(624), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(624).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(623), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(623).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(622), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(622).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(621), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(621).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(620), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(620).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(619), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(619).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(618), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(618).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(617), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(617).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(616), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(616).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(615), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(615).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(614), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(614).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(613), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(613).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(612), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(612).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(611), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(611).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(610), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(610).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(609), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(609).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(608), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(608).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(607), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(607).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(606), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(606).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(605), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(605).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(604), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(604).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(603), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(603).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(602), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(602).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(601), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(601).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(600), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(600).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(599), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(599).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(598), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(598).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(597), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(597).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(596), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(596).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(595), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(595).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(594), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(594).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(593), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(593).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(592), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(592).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(591), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(591).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(590), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(590).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(589), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(589).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(588), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(588).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(587), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(587).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(586), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(586).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(585), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(585).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(584), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(584).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(583), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(583).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(582), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(582).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(581), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(581).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(580), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(580).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(579), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(579).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(578), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(578).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(577), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(577).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(576), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(576).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(575), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(575).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(574), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(574).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(573), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(573).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(572), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(572).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(571), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(571).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(570), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(570).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(569), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(569).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(568), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(568).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(567), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(567).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(566), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(566).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(565), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(565).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(564), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(564).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(563), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(563).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(562), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(562).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(561), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(561).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(560), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(560).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(559), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(559).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(558), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(558).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(557), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(557).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(556), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(556).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(555), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(555).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(554), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(554).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(553), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(553).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(552), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(552).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(551), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(551).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(550), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(550).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(549), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(549).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(548), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(548).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(547), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(547).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(546), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(546).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(545), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(545).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(544), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(544).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(543), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(543).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(542), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(542).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(541), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(541).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(540), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(540).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(539), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(539).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(538), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(538).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(537), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(537).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(536), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(536).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(535), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(535).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(534), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(534).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(533), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(533).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(532), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(532).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(531), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(531).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(530), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(530).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(529), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(529).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(528), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(528).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(527), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(527).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(526), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(526).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(525), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(525).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(524), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(524).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(523), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(523).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(522), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(522).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(521), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(521).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(520), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(520).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(519), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(519).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(518), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(518).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(517), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(517).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(516), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(516).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(515), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(515).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(514), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(514).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(513), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(513).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(512), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(512).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(511), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(511).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(510), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(510).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(509), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(509).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(508), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(508).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(507), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(507).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(506), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(506).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(505), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(505).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(504), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(504).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(503), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(503).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(502), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(502).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(501), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(501).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(500), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(500).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(499), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(499).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(498), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(498).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(497), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(497).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(496), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(496).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(495), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(495).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(494), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(494).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(493), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(493).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(492), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(492).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(491), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(491).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(490), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(490).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(489), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(489).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(488), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(488).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(487), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(487).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(486), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(486).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(485), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(485).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(484), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(484).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(483), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(483).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(482), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(482).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(481), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(481).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(480), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(480).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(479), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(479).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(478), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(478).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(477), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(477).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(476), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(476).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(475), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(475).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(474), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(474).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(473), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(473).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(472), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(472).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(471), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(471).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(470), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(470).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(469), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(469).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(468), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(468).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(467), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(467).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(466), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(466).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(465), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(465).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(464), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(464).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(463), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(463).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(462), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(462).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(461), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(461).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(460), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(460).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(459), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(459).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(458), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(458).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(457), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(457).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(456), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(456).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(455), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(455).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(454), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(454).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(453), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(453).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(452), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(452).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(451), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(451).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(450), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(450).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(449), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(449).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(448), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(448).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(447), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(447).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(446), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(446).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(445), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(445).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(444), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(444).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(443), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(443).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(442), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(442).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(441), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(441).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(440), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(440).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(439), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(439).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(438), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(438).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(437), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(437).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(436), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(436).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(435), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(435).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(434), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(434).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(433), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(433).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(432), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(432).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(431), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(431).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(430), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(430).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(429), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(429).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(428), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(428).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(427), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(427).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(426), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(426).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(425), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(425).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(424), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(424).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(423), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(423).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(422), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(422).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(421), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(421).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(420), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(420).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(419), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(419).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(418), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(418).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(417), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(417).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(416), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(416).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(415), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(415).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(414), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(414).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(413), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(413).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(412), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(412).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(411), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(411).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(410), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(410).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(409), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(409).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(408), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(408).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(407), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(407).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(406), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(406).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(405), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(405).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(404), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(404).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(403), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(403).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(402), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(402).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(401), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(401).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(400), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(400).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(399), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(399).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(398), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(398).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(397), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(397).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(396), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(396).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(395), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(395).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(394), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(394).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(393), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(393).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(392), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(392).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(391), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(391).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(390), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(390).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(389), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(389).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(388), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(388).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(387), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(387).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(386), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(386).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(385), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(385).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(384), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(384).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(383), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(383).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(382), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(382).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(381), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(381).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(380), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(380).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(379), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(379).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(378), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(378).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(377), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(377).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(376), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(376).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(375), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(375).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(374), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(374).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(373), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(373).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(372), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(372).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(371), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(371).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(370), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(370).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(369), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(369).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(368), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(368).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(367), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(367).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(366), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(366).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(365), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(365).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(364), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(364).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(363), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(363).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(362), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(362).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(361), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(361).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(360), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(360).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(359), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(359).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(358), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(358).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(357), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(357).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(356), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(356).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(355), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(355).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(354), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(354).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(353), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(353).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(352), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(352).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(351), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(351).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(350), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(350).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(349), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(349).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(348), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(348).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(347), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(347).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(346), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(346).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(345), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(345).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(344), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(344).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(343), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(343).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(342), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(342).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(341), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(341).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(340), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(340).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(339), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(339).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(338), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(338).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(337), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(337).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(336), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(336).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(335), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(335).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(334), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(334).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(333), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(333).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(332), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(332).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(331), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(331).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(330), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(330).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(329), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(329).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(328), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(328).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(327), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(327).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(326), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(326).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(325), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(325).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(324), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(324).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(323), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(323).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(322), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(322).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(321), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(321).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(320), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(320).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(319), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(319).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(318), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(318).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(317), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(317).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(316), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(316).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(315), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(315).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(314), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(314).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(313), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(313).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(312), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(312).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(311), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(311).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(310), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(310).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(309), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(309).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(308), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(308).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(307), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(307).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(306), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(306).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(305), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(305).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(304), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(304).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(303), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(303).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(302), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(302).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(301), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(301).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(300), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(300).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(299), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(299).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(298), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(298).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(297), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(297).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(296), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(296).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(295), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(295).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(294), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(294).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(293), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(293).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(292), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(292).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(291), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(291).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(290), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(290).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(289), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(289).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(288), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(288).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(287), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(287).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(286), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(286).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(285), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(285).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(284), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(284).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(283), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(283).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(282), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(282).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(281), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(281).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(280), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(280).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(279), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(279).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(278), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(278).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(277), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(277).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(276), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(276).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(275), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(275).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(274), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(274).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(273), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(273).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(272), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(272).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(271), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(271).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(270), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(270).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(269), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(269).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(268), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(268).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(267), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(267).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(266), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(266).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(265), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(265).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(264), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(264).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(263), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(263).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(262), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(262).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(261), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(261).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(260), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(260).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(259), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(259).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(258), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(258).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(257), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(257).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(256), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(256).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(255), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(255).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(254), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(254).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(253), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(253).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(252), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(252).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(251), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(251).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(250), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(250).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(249), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(249).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(248), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(248).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(247), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(247).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(246), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(246).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(245), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(245).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(244), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(244).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(243), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(243).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(242), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(242).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(241), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(241).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(240), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(240).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(239), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(239).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(238), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(238).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(237), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(237).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(236), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(236).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(235), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(235).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(234), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(234).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(233), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(233).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(232), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(232).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(231), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(231).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(230), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(230).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(229), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(229).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(228), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(228).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(227), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(227).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(226), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(226).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(225), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(225).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(224), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(224).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(223), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(223).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(222), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(222).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(221), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(221).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(220), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(220).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(219), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(219).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(218), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(218).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(217), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(217).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(216), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(216).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(215), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(215).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(214), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(214).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(213), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(213).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(212), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(212).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(211), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(211).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(210), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(210).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(209), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(209).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(208), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(208).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(207), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(207).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(206), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(206).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(205), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(205).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(204), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(204).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(203), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(203).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(202), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(202).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(201), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(201).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(200), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(200).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(199), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(199).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(198), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(198).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(197), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(197).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(196), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(196).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(195), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(195).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(194), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(194).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(193), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(193).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(192), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(192).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(191), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(191).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(190), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(190).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(189), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(189).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(188), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(188).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(187), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(187).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(186), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(186).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(185), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(185).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(184), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(184).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(183), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(183).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(182), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(182).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(181), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(181).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(180), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(180).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(179), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(179).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(178), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(178).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(177), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(177).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(176), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(176).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(175), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(175).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(174), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(174).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(173), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(173).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(172), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(172).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(171), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(171).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(170), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(170).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(169), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(169).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(168), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(168).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(167), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(167).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(166), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(166).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(165), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(165).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(164), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(164).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(163), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(163).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(162), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(162).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(161), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(161).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(160), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(160).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(159), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(159).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(158), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(158).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(157), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(157).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(156), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(156).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(155), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(155).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(154), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(154).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(153), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(153).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(152), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(152).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(151), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(151).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(150), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(150).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(149), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(149).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(148), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(148).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(147), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(147).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(146), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(146).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(145), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(145).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(144), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(144).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(143), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(143).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(142), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(142).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(141), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(141).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(140), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(140).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(139), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(139).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(138), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(138).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(137), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(137).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(136), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(136).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(135), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(135).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(134), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(134).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(133), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(133).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(132), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(132).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(131), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(131).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(130), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(130).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(129), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(129).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(128), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(128).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(127), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(127).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(126), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(126).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(125), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(125).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(124), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(124).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(123), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(123).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(122), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(122).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(121), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(121).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(120), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(120).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(119), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(119).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(118), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(118).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(117), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(117).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(116), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(116).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(115), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(115).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(114), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(114).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(113), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(113).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(112), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(112).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(111), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(111).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(110), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(110).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(109), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(109).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(108), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(108).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(107), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(107).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(106), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(106).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(105), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(105).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(104), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(104).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(103), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(103).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(102), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(102).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(101), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(101).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(100), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(100).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(99), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(99).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(98), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(98).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(97), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(97).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(96), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(96).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(95), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(95).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(94), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(94).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(93), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(93).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(92), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(92).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(91), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(91).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(90), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(90).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(89), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(89).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(88), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(88).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(87), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(87).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(86), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(86).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(85), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(85).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(84), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(84).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(83), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(83).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(82), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(82).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(81), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(81).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(80), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(80).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(79), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(79).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(78), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(78).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(77), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(77).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(76), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(76).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(75), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(75).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(74), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(74).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(73), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(73).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(72), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(72).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(71), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(71).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(70), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(70).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(69), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(69).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(68), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(68).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(67), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(67).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(66), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(66).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(65), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(65).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(64), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(64).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(31), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(31).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(30), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(30).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(29), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(29).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(28), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(28).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(27), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(27).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(26), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(26).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(25), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(25).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(24), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(24).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(23), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(23).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(22), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(22).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(21), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(21).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(20), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(20).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(19), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(19).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(18), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(18).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(17), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(17).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(16), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(16).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(5), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(5).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(4), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(4).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(3), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(3).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(2), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(2).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(1), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(1).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(31), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(31).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(30), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(30).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(29), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(29).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(28), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(28).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(27), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(27).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(26), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(26).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(25), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(25).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(24), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(24).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(23), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(23).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(22), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(22).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(21), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(21).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(20), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(20).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(19), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(19).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(18), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(18).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(17), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(17).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(16), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(16).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(5), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(5).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(4), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(4).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(3), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(3).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(2), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(2).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(1), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(1).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(5), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(5).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(4), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(4).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(3), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(3).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(31), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(31).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(30), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(30).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(29), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(29).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(28), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(28).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(27), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(27).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(26), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(26).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(25), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(25).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(24), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(24).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(23), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(23).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(22), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(22).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(21), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(21).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(20), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(20).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(19), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(19).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(18), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(18).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(17), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(17).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(16), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(16).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(5), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(5).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(4), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(4).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(3), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(3).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(2), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(2).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(1), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(1).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(31), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(31).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(30), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(30).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(29), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(29).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(28), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(28).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(27), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(27).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(26), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(26).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(25), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(25).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(24), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(24).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(23), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(23).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(22), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(22).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(21), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(21).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(20), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(20).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(19), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(19).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(18), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(18).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(17), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(17).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(16), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(16).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/reg_eth10g_miso.rdval, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/reg_eth10g_miso.rdval.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/reg_eth10g_miso.waitrequest, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/reg_eth10g_miso.waitrequest.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/reg_eth10g_miso.rddata(71 downto 0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/reg_eth10g_miso.rddata(71 downto 0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/serial_tx_arr, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/serial_tx_arr.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.waitrequest, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.waitrequest.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(71), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(71).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(70), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(70).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(69), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(69).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(68), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(68).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(67), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(67).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(66), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(66).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(65), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(65).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(64), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(64).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_remu/u_remu/gen_ip_stratixiv/u0/ip_stratixiv_remote_update_rmtupdt_jol_component/sd1/regout has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/stratixii_asmiblock2/data0out has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.waitrequest, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.waitrequest.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(71), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(71).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(70), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(70).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(69), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(69).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(68), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(68).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(67), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(67).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(66), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(66).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(65), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(65).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(64), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(64).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.waitrequest, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.waitrequest.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(71), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(71).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(70), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(70).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(69), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(69).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(68), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(68).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(67), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(67).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(66), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(66).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(65), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(65).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(64), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(64).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/rom_unb_system_info_miso.rddata(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/eth_sgout, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/eth_txp.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/u_inst_mmm_compaan_unb1_10g_bg_db/pout_wdi, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_lcu/pout_wdi.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_lcu/eth_sgout, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/eth_txp.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_lcu/si_fn_3_tx(3 downto 0) has no driver.
+# This port will contribute value (X) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on inout port /tb_compaan_unb1_10g_app/u_dut/u_front_io/si_fn_0_cntrl(0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/si_fn_0_cntrl(0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on inout port /tb_compaan_unb1_10g_app/u_dut/u_front_io/si_fn_1_cntrl(2 downto 0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/si_fn_1_cntrl(2 downto 0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on inout port /tb_compaan_unb1_10g_app/u_dut/u_front_io/si_fn_2_cntrl(2 downto 0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/si_fn_2_cntrl(2 downto 0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on inout port /tb_compaan_unb1_10g_app/u_dut/u_front_io/si_fn_3_cntrl(2 downto 0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/si_fn_3_cntrl(2 downto 0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.sync, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.sync.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(31), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(31).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(30), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(30).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(29), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(29).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(28), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(28).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(27), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(27).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(26), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(26).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(25), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(25).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(24), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(24).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(23), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(23).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(22), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(22).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(21), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(21).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(20), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(20).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(19), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(19).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(18), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(18).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(17), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(17).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(16), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(16).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(5), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(5).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(4), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(4).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(3), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(3).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(2), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(2).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(1), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(1).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.bsn(0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.bsn(0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(767), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(767).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(766), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(766).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(765), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(765).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(764), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(764).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(763), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(763).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(762), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(762).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(761), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(761).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(760), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(760).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(759), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(759).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(758), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(758).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(757), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(757).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(756), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(756).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(755), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(755).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(754), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(754).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(753), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(753).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(752), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(752).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(751), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(751).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(750), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(750).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(749), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(749).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(748), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(748).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(747), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(747).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(746), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(746).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(745), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(745).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(744), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(744).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(743), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(743).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(742), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(742).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(741), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(741).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(740), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(740).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(739), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(739).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(738), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(738).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(737), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(737).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(736), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(736).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(735), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(735).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(734), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(734).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(733), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(733).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(732), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(732).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(731), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(731).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(730), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(730).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(729), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(729).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(728), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(728).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(727), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(727).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(726), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(726).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(725), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(725).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(724), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(724).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(723), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(723).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(722), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(722).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(721), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(721).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(720), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(720).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(719), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(719).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(718), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(718).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(717), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(717).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(716), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(716).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(715), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(715).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(714), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(714).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(713), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(713).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(712), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(712).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(711), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(711).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(710), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(710).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(709), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(709).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(708), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(708).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(707), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(707).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(706), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(706).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(705), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(705).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(704), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(704).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(703), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(703).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(702), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(702).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(701), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(701).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(700), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(700).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(699), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(699).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(698), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(698).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(697), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(697).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(696), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(696).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(695), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(695).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(694), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(694).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(693), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(693).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(692), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(692).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(691), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(691).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(690), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(690).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(689), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(689).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(688), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(688).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(687), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(687).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(686), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(686).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(685), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(685).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(684), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(684).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(683), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(683).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(682), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(682).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(681), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(681).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(680), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(680).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(679), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(679).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(678), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(678).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(677), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(677).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(676), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(676).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(675), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(675).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(674), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(674).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(673), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(673).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(672), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(672).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(671), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(671).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(670), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(670).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(669), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(669).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(668), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(668).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(667), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(667).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(666), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(666).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(665), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(665).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(664), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(664).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(663), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(663).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(662), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(662).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(661), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(661).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(660), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(660).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(659), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(659).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(658), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(658).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(657), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(657).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(656), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(656).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(655), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(655).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(654), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(654).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(653), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(653).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(652), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(652).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(651), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(651).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(650), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(650).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(649), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(649).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(648), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(648).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(647), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(647).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(646), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(646).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(645), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(645).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(644), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(644).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(643), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(643).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(642), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(642).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(641), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(641).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(640), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(640).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(639), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(639).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(638), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(638).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(637), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(637).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(636), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(636).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(635), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(635).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(634), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(634).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(633), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(633).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(632), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(632).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(631), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(631).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(630), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(630).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(629), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(629).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(628), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(628).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(627), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(627).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(626), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(626).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(625), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(625).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(624), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(624).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(623), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(623).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(622), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(622).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(621), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(621).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(620), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(620).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(619), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(619).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(618), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(618).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(617), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(617).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(616), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(616).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(615), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(615).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(614), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(614).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(613), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(613).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(612), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(612).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(611), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(611).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(610), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(610).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(609), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(609).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(608), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(608).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(607), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(607).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(606), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(606).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(605), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(605).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(604), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(604).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(603), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(603).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(602), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(602).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(601), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(601).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(600), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(600).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(599), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(599).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(598), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(598).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(597), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(597).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(596), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(596).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(595), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(595).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(594), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(594).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(593), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(593).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(592), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(592).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(591), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(591).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(590), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(590).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(589), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(589).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(588), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(588).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(587), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(587).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(586), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(586).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(585), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(585).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(584), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(584).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(583), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(583).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(582), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(582).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(581), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(581).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(580), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(580).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(579), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(579).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(578), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(578).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(577), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(577).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(576), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(576).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(575), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(575).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(574), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(574).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(573), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(573).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(572), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(572).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(571), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(571).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(570), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(570).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(569), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(569).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(568), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(568).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(567), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(567).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(566), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(566).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(565), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(565).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(564), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(564).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(563), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(563).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(562), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(562).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(561), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(561).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(560), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(560).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(559), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(559).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(558), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(558).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(557), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(557).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(556), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(556).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(555), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(555).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(554), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(554).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(553), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(553).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(552), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(552).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(551), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(551).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(550), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(550).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(549), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(549).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(548), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(548).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(547), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(547).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(546), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(546).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(545), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(545).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(544), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(544).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(543), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(543).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(542), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(542).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(541), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(541).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(540), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(540).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(539), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(539).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(538), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(538).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(537), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(537).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(536), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(536).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(535), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(535).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(534), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(534).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(533), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(533).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(532), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(532).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(531), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(531).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(530), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(530).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(529), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(529).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(528), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(528).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(527), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(527).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(526), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(526).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(525), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(525).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(524), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(524).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(523), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(523).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(522), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(522).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(521), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(521).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(520), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(520).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(519), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(519).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(518), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(518).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(517), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(517).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(516), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(516).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(515), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(515).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(514), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(514).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(513), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(513).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(512), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(512).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(511), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(511).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(510), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(510).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(509), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(509).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(508), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(508).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(507), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(507).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(506), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(506).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(505), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(505).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(504), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(504).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(503), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(503).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(502), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(502).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(501), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(501).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(500), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(500).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(499), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(499).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(498), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(498).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(497), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(497).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(496), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(496).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(495), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(495).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(494), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(494).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(493), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(493).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(492), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(492).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(491), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(491).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(490), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(490).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(489), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(489).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(488), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(488).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(487), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(487).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(486), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(486).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(485), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(485).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(484), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(484).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(483), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(483).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(482), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(482).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(481), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(481).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(480), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(480).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(479), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(479).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(478), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(478).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(477), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(477).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(476), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(476).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(475), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(475).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(474), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(474).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(473), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(473).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(472), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(472).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(471), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(471).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(470), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(470).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(469), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(469).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(468), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(468).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(467), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(467).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(466), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(466).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(465), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(465).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(464), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(464).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(463), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(463).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(462), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(462).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(461), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(461).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(460), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(460).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(459), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(459).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(458), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(458).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(457), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(457).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(456), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(456).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(455), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(455).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(454), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(454).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(453), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(453).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(452), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(452).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(451), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(451).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(450), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(450).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(449), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(449).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(448), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(448).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(447), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(447).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(446), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(446).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(445), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(445).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(444), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(444).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(443), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(443).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(442), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(442).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(441), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(441).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(440), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(440).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(439), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(439).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(438), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(438).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(437), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(437).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(436), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(436).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(435), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(435).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(434), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(434).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(433), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(433).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(432), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(432).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(431), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(431).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(430), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(430).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(429), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(429).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(428), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(428).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(427), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(427).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(426), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(426).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(425), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(425).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(424), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(424).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(423), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(423).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(422), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(422).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(421), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(421).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(420), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(420).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(419), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(419).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(418), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(418).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(417), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(417).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(416), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(416).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(415), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(415).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(414), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(414).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(413), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(413).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(412), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(412).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(411), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(411).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(410), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(410).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(409), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(409).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(408), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(408).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(407), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(407).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(406), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(406).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(405), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(405).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(404), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(404).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(403), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(403).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(402), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(402).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(401), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(401).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(400), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(400).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(399), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(399).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(398), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(398).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(397), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(397).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(396), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(396).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(395), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(395).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(394), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(394).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(393), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(393).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(392), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(392).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(391), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(391).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(390), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(390).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(389), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(389).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(388), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(388).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(387), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(387).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(386), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(386).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(385), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(385).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(384), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(384).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(383), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(383).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(382), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(382).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(381), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(381).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(380), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(380).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(379), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(379).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(378), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(378).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(377), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(377).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(376), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(376).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(375), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(375).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(374), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(374).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(373), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(373).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(372), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(372).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(371), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(371).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(370), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(370).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(369), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(369).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(368), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(368).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(367), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(367).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(366), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(366).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(365), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(365).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(364), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(364).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(363), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(363).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(362), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(362).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(361), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(361).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(360), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(360).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(359), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(359).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(358), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(358).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(357), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(357).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(356), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(356).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(355), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(355).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(354), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(354).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(353), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(353).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(352), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(352).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(351), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(351).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(350), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(350).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(349), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(349).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(348), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(348).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(347), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(347).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(346), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(346).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(345), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(345).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(344), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(344).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(343), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(343).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(342), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(342).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(341), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(341).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(340), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(340).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(339), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(339).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(338), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(338).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(337), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(337).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(336), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(336).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(335), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(335).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(334), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(334).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(333), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(333).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(332), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(332).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(331), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(331).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(330), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(330).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(329), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(329).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(328), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(328).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(327), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(327).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(326), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(326).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(325), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(325).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(324), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(324).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(323), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(323).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(322), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(322).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(321), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(321).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(320), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(320).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(319), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(319).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(318), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(318).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(317), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(317).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(316), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(316).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(315), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(315).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(314), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(314).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(313), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(313).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(312), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(312).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(311), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(311).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(310), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(310).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(309), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(309).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(308), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(308).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(307), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(307).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(306), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(306).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(305), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(305).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(304), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(304).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(303), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(303).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(302), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(302).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(301), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(301).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(300), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(300).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(299), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(299).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(298), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(298).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(297), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(297).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(296), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(296).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(295), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(295).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(294), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(294).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(293), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(293).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(292), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(292).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(291), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(291).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(290), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(290).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(289), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(289).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(288), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(288).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(287), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(287).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(286), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(286).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(285), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(285).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(284), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(284).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(283), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(283).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(282), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(282).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(281), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(281).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(280), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(280).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(279), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(279).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(278), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(278).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(277), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(277).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(276), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(276).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(275), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(275).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(274), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(274).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(273), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(273).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(272), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(272).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(271), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(271).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(270), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(270).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(269), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(269).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(268), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(268).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(267), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(267).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(266), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(266).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(265), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(265).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(264), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(264).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(263), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(263).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(262), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(262).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(261), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(261).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(260), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(260).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(259), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(259).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(258), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(258).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(257), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(257).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(256), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(256).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(255), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(255).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(254), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(254).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(253), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(253).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(252), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(252).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(251), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(251).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(250), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(250).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(249), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(249).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(248), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(248).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(247), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(247).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(246), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(246).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(245), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(245).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(244), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(244).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(243), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(243).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(242), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(242).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(241), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(241).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(240), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(240).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(239), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(239).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(238), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(238).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(237), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(237).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(236), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(236).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(235), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(235).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(234), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(234).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(233), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(233).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(232), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(232).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(231), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(231).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(230), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(230).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(229), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(229).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(228), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(228).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(227), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(227).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(226), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(226).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(225), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(225).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(224), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(224).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(223), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(223).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(222), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(222).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(221), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(221).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(220), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(220).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(219), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(219).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(218), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(218).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(217), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(217).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(216), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(216).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(215), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(215).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(214), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(214).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(213), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(213).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(212), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(212).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(211), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(211).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(210), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(210).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(209), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(209).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(208), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(208).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(207), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(207).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(206), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(206).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(205), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(205).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(204), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(204).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(203), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(203).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(202), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(202).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(201), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(201).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(200), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(200).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(199), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(199).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(198), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(198).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(197), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(197).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(196), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(196).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(195), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(195).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(194), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(194).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(193), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(193).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(192), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(192).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(191), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(191).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(190), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(190).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(189), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(189).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(188), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(188).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(187), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(187).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(186), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(186).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(185), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(185).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(184), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(184).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(183), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(183).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(182), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(182).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(181), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(181).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(180), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(180).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(179), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(179).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(178), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(178).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(177), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(177).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(176), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(176).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(175), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(175).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(174), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(174).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(173), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(173).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(172), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(172).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(171), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(171).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(170), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(170).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(169), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(169).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(168), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(168).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(167), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(167).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(166), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(166).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(165), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(165).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(164), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(164).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(163), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(163).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(162), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(162).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(161), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(161).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(160), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(160).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(159), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(159).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(158), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(158).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(157), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(157).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(156), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(156).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(155), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(155).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(154), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(154).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(153), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(153).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(152), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(152).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(151), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(151).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(150), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(150).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(149), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(149).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(148), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(148).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(147), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(147).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(146), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(146).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(145), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(145).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(144), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(144).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(143), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(143).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(142), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(142).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(141), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(141).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(140), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(140).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(139), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(139).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(138), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(138).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(137), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(137).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(136), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(136).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(135), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(135).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(134), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(134).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(133), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(133).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(132), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(132).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(131), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(131).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(130), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(130).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(129), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(129).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(128), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(128).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(127), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(127).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(126), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(126).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(125), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(125).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(124), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(124).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(123), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(123).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(122), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(122).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(121), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(121).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(120), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(120).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(119), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(119).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(118), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(118).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(117), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(117).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(116), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(116).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(115), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(115).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(114), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(114).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(113), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(113).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(112), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(112).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(111), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(111).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(110), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(110).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(109), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(109).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(108), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(108).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(107), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(107).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(106), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(106).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(105), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(105).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(104), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(104).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(103), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(103).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(102), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(102).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(101), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(101).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(100), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(100).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(99), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(99).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(98), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(98).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(97), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(97).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(96), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(96).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(95), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(95).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(94), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(94).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(93), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(93).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(92), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(92).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(91), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(91).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(90), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(90).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(89), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(89).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(88), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(88).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(87), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(87).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(86), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(86).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(85), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(85).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(84), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(84).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(83), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(83).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(82), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(82).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(81), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(81).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(80), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(80).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(79), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(79).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(78), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(78).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(77), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(77).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(76), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(76).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(75), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(75).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(74), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(74).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(73), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(73).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(72), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(72).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(71), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(71).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(70), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(70).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(69), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(69).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(68), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(68).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(67), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(67).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(66), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(66).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(65), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(65).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.data(64), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.data(64).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(31), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(31).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(30), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(30).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(29), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(29).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(28), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(28).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(27), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(27).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(26), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(26).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(25), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(25).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(24), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(24).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(23), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(23).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(22), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(22).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(21), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(21).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(20), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(20).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(19), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(19).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(18), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(18).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(17), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(17).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(16), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(16).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(5), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(5).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(4), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(4).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(3), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(3).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(2), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(2).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(1), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(1).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.re(0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.re(0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(31), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(31).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(30), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(30).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(29), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(29).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(28), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(28).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(27), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(27).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(26), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(26).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(25), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(25).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(24), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(24).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(23), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(23).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(22), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(22).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(21), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(21).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(20), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(20).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(19), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(19).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(18), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(18).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(17), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(17).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(16), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(16).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(5), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(5).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(4), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(4).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(3), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(3).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(2), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(2).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(1), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(1).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.im(0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.im(0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(5), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(5).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(4), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(4).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.empty(3), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.empty(3).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(31), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(31).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(30), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(30).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(29), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(29).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(28), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(28).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(27), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(27).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(26), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(26).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(25), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(25).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(24), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(24).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(23), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(23).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(22), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(22).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(21), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(21).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(20), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(20).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(19), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(19).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(18), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(18).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(17), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(17).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(16), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(16).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(5), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(5).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(4), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(4).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(3), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(3).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(2), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(2).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(1), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(1).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.channel(0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.channel(0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(31), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(31).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(30), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(30).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(29), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(29).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(28), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(28).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(27), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(27).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(26), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(26).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(25), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(25).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(24), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(24).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(23), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(23).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(22), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(22).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(21), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(21).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(20), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(20).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(19), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(19).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(18), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(18).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(17), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(17).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(16), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(16).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(15), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(15).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(14), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(14).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(13), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(13).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(12), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(12).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(11), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(11).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(10), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(10).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(9), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(9).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(8), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(8).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(7), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(7).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/rx_src_out.err(6), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/rx_mac_src_out.err(6).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/reg_eth10g_miso.rdval, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/reg_eth10g_miso.rdval.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/reg_eth10g_miso.waitrequest, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/reg_eth10g_miso.waitrequest.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/reg_eth10g_miso.rddata(71 downto 0), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/reg_eth10g_miso.rddata(71 downto 0).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/serial_tx_arr, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/serial_tx_arr.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/par_load/sync_num, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/sl_sync_num.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/par_load/parameters_rd, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/sl_parameters_rd.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/par_load/parameters_wr, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/sl_parameters_wr.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/par_load/sync_num, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/sl_sync_num.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/par_load/parameters_rd, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/sl_parameters_rd.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/par_load/parameters_wr, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/sl_parameters_wr.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/par_load/sync_num, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/sl_sync_num.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/par_load/parameters_rd, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/sl_parameters_rd.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/par_load/parameters_wr, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/sl_parameters_wr.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_1/ipcore2rtl_ed_1/fsl_rst has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_1/ipcore2rtl_ed_1/fsl_s_control has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_1/ipcore2rtl_ed_1/fsl_full has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_1/ipcore2rtl_ed_1/fsl_has_data has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_1/ipcore2rtl_ed_1/fsl_control_irq has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_2/ipcore2rtl_ed_2/fsl_rst has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_2/ipcore2rtl_ed_2/fsl_s_control has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_2/ipcore2rtl_ed_2/fsl_full has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_2/ipcore2rtl_ed_2/fsl_has_data has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_2/ipcore2rtl_ed_2/fsl_control_irq has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/snk_out.xon, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/compaan_snk_out.xon.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/test_stop(2 downto 0) has no driver.
+# This port will contribute value (X) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/test_error(2 downto 0) has no driver.
+# This port will contribute value (X) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/test_fifo_full(1 downto 0) has no driver.
+# This port will contribute value (X) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/test_block_rd(2 downto 0) has no driver.
+# This port will contribute value (X) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.waitrequest, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.waitrequest.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(71), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(71).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(70), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(70).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(69), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(69).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(68), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(68).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(67), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(67).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(66), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(66).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(65), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(65).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(64), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(64).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/rom_miso.rddata(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_remu/u_remu/gen_ip_stratixiv/u0/ip_stratixiv_remote_update_rmtupdt_jol_component/sd1/regout has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/stratixii_asmiblock2/data0out has no driver.
+# This port will contribute value (U) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.waitrequest, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.waitrequest.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(71), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(71).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(70), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(70).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(69), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(69).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(68), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(68).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(67), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(67).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(66), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(66).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(65), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(65).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(64), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(64).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/dpmm_data_miso.rddata(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/reg_dpmm_data_miso.rddata(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.waitrequest, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.waitrequest.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(71), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(71).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(70), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(70).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(69), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(69).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(68), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(68).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(67), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(67).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(66), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(66).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(65), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(65).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(64), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(64).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(63), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(63).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(62), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(62).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(61), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(61).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(60), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(60).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(59), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(59).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(58), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(58).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(57), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(57).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(56), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(56).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(55), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(55).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(54), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(54).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(53), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(53).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(52), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(52).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(51), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(51).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(50), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(50).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(49), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(49).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(48), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(48).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(47), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(47).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(46), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(46).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(45), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(45).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(44), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(44).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(43), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(43).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(42), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(42).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(41), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(41).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(40), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(40).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(39), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(39).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(38), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(38).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(37), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(37).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(36), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(36).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(35), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(35).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(34), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(34).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(33), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(33).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/rom_unb_system_info_miso.rddata(32), and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/rom_unb_system_info_miso.rddata(32).
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/eth_sgout, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/eth_txp.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/u_inst_mmm_compaan_unb1_10g_app/pout_wdi, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/u_dut/pout_wdi.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8684) No drivers exist on out port /tb_compaan_unb1_10g_app/u_dut/eth_sgout, and its initial value is not used.
+# Therefore, simulation behavior may occur that is not in compliance with
+# the VHDL standard as the initial values come from the base signal /tb_compaan_unb1_10g_app/eth_txp.
+# Region: /tb_compaan_unb1_10g_app
+# ** Warning: (vsim-8683) Uninitialized out port /tb_compaan_unb1_10g_app/u_dut/si_fn_3_tx(3 downto 0) has no driver.
+# This port will contribute value (X) to the signal network.
+# Region: /tb_compaan_unb1_10g_app
+# Break key hit
+# Break key hit
+# Break key hit
+# do /home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/tools/modelsim/commands.do
+# Loading general HDL library commands...
+as 10
+run -all
+# [0 ns ] $UNB/Software/python/sim/sim.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_COMPAAN.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_TR_XAUI.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_TR_10GBE.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_MDIO_2.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_MDIO_1.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_MDIO_0.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_BG.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DIAG_BG.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DIAG_DATA_BUFFER.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DP_OFFLOAD_RX_HDR_DAT.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DP_OFFLOAD_TX_HDR_OVR.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DP_OFFLOAD_TX.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_BSN_MONITOR.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_REMU.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_EPCS.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_ETH1G_TSE.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_AVS_ETH_0_MMS_REG.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_ETH1G_RAM.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_PIO_PPS.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_UNB_SENS.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_ROM_SYSTEM_INFO.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_PIO_SYSTEM_INFO.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_WDI.ctrl: Created
+# ** Warning: NUMERIC_STD.">": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_sens
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_sens/u_unb1_board_sens/u_i2c_smbus
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_sens/u_unb1_board_sens/u_i2c_smbus
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_sens/u_unb1_board_sens/u_i2c_smbus/byte
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_ppsh/u_ppsh
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_ppsh/u_ppsh/u_capture_cnt
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr5/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr5/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr5/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr5/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_system_info/u_unb1_board_system_info
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_unb1_board_node_ctrl/u_common_pulser_us_ms_s/u_common_pulser_us
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_diag_data_buffer/gen_db/gen_stream(0)/u_diag_data_buffer/u_reg/gen_cross
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_diag_data_buffer/gen_db/gen_stream(0)/u_diag_data_buffer
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(3)/u_mon
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(3)/u_reg/u_reg/gen_cross
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(2)/u_mon
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(2)/u_reg/u_reg/gen_cross
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(1)/u_mon
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(1)/u_reg/u_reg/gen_cross
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(0)/u_mon
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(0)/u_reg/u_reg/gen_cross
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_rx/gen_dp_field_blk(0)/u_dp_field_blk/u_mm_fields_slv/u_common_reg_r_w_dc/gen_cross
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_rx/gen_nof_streams(0)/u_dp_split
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_2/ipcore2rtl_ed_2/u_dp_fifo_core/u_dp_fifo_core/u_ready_latency/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_2/ipcore2rtl_ed_2/u_dp_fifo_core/u_dp_fifo_core/u_ready_latency/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_2/ipcore2rtl_ed_2/u_dp_fifo_core/u_dp_fifo_core/gen_common_fifo_sc/u_common_fifo_sc
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_2/ipcore2rtl_ed_2/u_dp_fifo_core/u_dp_fifo_core
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_1/ipcore2rtl_ed_1/u_dp_fifo_core/u_dp_fifo_core/u_ready_latency/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_1/ipcore2rtl_ed_1/u_dp_fifo_core/u_dp_fifo_core/u_ready_latency/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_1/ipcore2rtl_ed_1/u_dp_fifo_core/u_dp_fifo_core/gen_common_fifo_sc/u_common_fifo_sc
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_ed_1/ipcore2rtl_ed_1/u_dp_fifo_core/u_dp_fifo_core
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_wr/gen_cntr_wr(0)/cntr_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_wr/cntr_mr0
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_wr
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_rd/gen_cntr_rd(0)/cntr_rd
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_rd/cntr_mr0
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_rd
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_wr/gen_cntr_wr(0)/cntr_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_wr/cntr_mr0
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_wr
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_rd/gen_cntr_rd(0)/cntr_rd
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_rd/cntr_mr0
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_rd
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_wr/gen_cntr_wr(0)/cntr_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_wr/cntr_mr0
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_wr
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_rd/gen_cntr_rd(0)/cntr_rd
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_rd/cntr_mr0
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_rd
+# ** Error: (vsim-86) numstd_conv_unsigned_nuA: NATURAL arg value is negative (-2147483648)
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_fifo_out/u_dp_fifo_core/u_ready_latency/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_fifo_out/u_dp_fifo_core/u_ready_latency/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_fifo_out/u_dp_fifo_core/gen_common_fifo_sc/u_common_fifo_sc
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_fifo_out/u_dp_fifo_core
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_fifo_in/u_dp_fifo_core/u_ready_latency/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_fifo_in/u_dp_fifo_core/u_ready_latency/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_fifo_in/u_dp_fifo_core/gen_common_fifo_sc/u_common_fifo_sc
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_fifo_in/u_dp_fifo_core
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_fifo_fill/dp_fifo_sc/u_dp_fifo_core/gen_common_fifo_sc/u_common_fifo_sc
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_fifo_fill/dp_fifo_sc/u_dp_fifo_core
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_mm_fields_slv/u_common_reg_r_w_dc/gen_cross
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_packet_merge(0)/u_dp_packet_merge/gen_dp_latency_adapter/u_dp_latency_adapter/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_packet_merge(0)/u_dp_packet_merge/gen_dp_latency_adapter/u_dp_latency_adapter/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_split(0)/u_dp_split
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_dp_fifo_sc(0)/u_dp_fifo_sc/u_dp_fifo_core/gen_common_fifo_sc/u_common_fifo_sc
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_dp_fifo_sc(0)/u_dp_fifo_sc/u_dp_fifo_core
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/u_tx_dp_latency_adapter/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/u_tx_dp_latency_adapter/gen_fifo
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core
+# [0 ns ] $UNB/Software/python/sim/sim.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_TR_XAUI.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_TR_10GBE.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_MDIO_2.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_MDIO_1.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_MDIO_0.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_DATA_BUFFER.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_DATA_BUFFER.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DP_OFFLOAD_RX_HDR_DAT.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DP_OFFLOAD_TX_HDR_OVR.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DP_OFFLOAD_TX.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_BSN_MONITOR.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_REMU.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_EPCS.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_ETH1G_TSE.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_AVS_ETH_0_MMS_REG.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_ETH1G_RAM.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_PIO_PPS.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_UNB_SENS.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_ROM_SYSTEM_INFO.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_PIO_SYSTEM_INFO.ctrl: Created
+# [0 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_WDI.ctrl: Created
+# ** Warning: NUMERIC_STD.">": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_sens
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_sens/u_unb1_board_sens/u_i2c_smbus
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_sens/u_unb1_board_sens/u_i2c_smbus
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_sens/u_unb1_board_sens/u_i2c_smbus/byte
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_ppsh/u_ppsh
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_ppsh/u_ppsh/u_capture_cnt
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr5/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr5/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr5/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr5/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_epcs_to_user/gen_mixed
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed/u_fifo_mw/u_fifo/gen_ip_stratixiv/u0/dcfifo_mixed_widths_component/lowlatency_fifo/lowlatency
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_fifo_user_to_epcs/gen_mixed
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_system_info/u_unb1_board_system_info
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_unb1_board_node_ctrl/u_common_pulser_us_ms_s/u_common_pulser_us
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_diag_data_buffer/gen_db/gen_stream(0)/u_diag_data_buffer/u_reg/gen_cross
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_diag_data_buffer/gen_db/gen_stream(0)/u_diag_data_buffer
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(3)/u_mon
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(3)/u_reg/u_reg/gen_cross
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(2)/u_mon
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(2)/u_reg/u_reg/gen_cross
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(1)/u_mon
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(1)/u_reg/u_reg/gen_cross
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(0)/u_mon
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(0)/u_reg/u_reg/gen_cross
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_rx/gen_dp_field_blk(0)/u_dp_field_blk/u_mm_fields_slv/u_common_reg_r_w_dc/gen_cross
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_rx/gen_nof_streams(0)/u_dp_split
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_fifo_fill/dp_fifo_sc/u_dp_fifo_core/gen_common_fifo_sc/u_common_fifo_sc
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_fifo_fill/dp_fifo_sc/u_dp_fifo_core
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_mm_fields_slv/u_common_reg_r_w_dc/gen_cross
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_packet_merge(0)/u_dp_packet_merge/gen_dp_latency_adapter/u_dp_latency_adapter/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_packet_merge(0)/u_dp_packet_merge/gen_dp_latency_adapter/u_dp_latency_adapter/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_split(0)/u_dp_split
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/gen_dp_fifo_sc(0)/u_dp_fifo_sc/u_dp_fifo_core/gen_common_fifo_sc/u_common_fifo_sc
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/gen_dp_fifo_sc(0)/u_dp_fifo_sc/u_dp_fifo_core
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_dc_rx(0)/u_dp_fifo_dc_rx/u_dp_fifo_core
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/u_tx_dp_latency_adapter/gen_fifo
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/u_tx_dp_latency_adapter/gen_fifo
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core/gen_common_fifo_dc/u_common_fifo_dc/u_fifo/gen_ip_stratixiv/u0/dcfifo_component/dcfifo_mw/lowlatency_fifo/lowlatency
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 0 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_dp_fifo_fill_dc(0)/u_dp_fifo_fill_dc/u_dp_fifo_fill_core/gen_dp_fifo_dc/u_dp_fifo_dc/u_dp_fifo_core
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_sens/u_unb1_board_sens/u_i2c_smbus
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_ppsh/u_ppsh
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(3)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(2)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(1)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(0)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_rx/gen_nof_streams(0)/u_dp_split
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_wr/cntr_mr0
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_rd/cntr_mr0
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_wr/cntr_mr0
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_rd/cntr_mr0
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_wr/cntr_mr0
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_rd/cntr_mr0
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_split(0)/u_dp_split
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy_reg/u_cross_domain_hdr
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_sens/u_unb1_board_sens/u_i2c_smbus
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_ppsh/u_ppsh
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(3)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(2)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(1)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(0)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_rx/gen_nof_streams(0)/u_dp_split
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_split(0)/u_dp_split
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy_reg/u_cross_domain_hdr
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add0_372/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_002/altera_merlin_traffic_limiter_0003_altera_merlin_traffic_limiter_limiter_002_add1_375/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add0_380/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter_001/altera_merlin_traffic_limiter_0002_altera_merlin_traffic_limiter_limiter_001_add1_383/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add0_313/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/limiter/altera_merlin_traffic_limiter_0001_altera_merlin_traffic_limiter_limiter_add1_317/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1026/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_1028/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add0_996/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add0_117/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_pauselen/altera_avalon_dc_fifo_0002_altera_avalon_dc_fifo_rxtx_dc_fifo_pauselen_add1_124/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add0_46/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 1 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rxtx_dc_fifo_link_fault_status/altera_avalon_dc_fifo_0001_altera_avalon_dc_fifo_rxtx_dc_fifo_link_fault_status_add1_53/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_rx/gen_nof_streams(0)/u_dp_split
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_wr/gen_cntr_wr(0)/cntr_wr
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_rd/gen_cntr_rd(0)/cntr_rd
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_wr/gen_cntr_wr(0)/cntr_wr
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_rd/gen_cntr_rd(0)/cntr_rd
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_wr/gen_cntr_wr(0)/cntr_wr
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_rd
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_rd/gen_cntr_rd(0)/cntr_rd
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_split(0)/u_dp_split
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs/u_asmi_parallel/gen_ip_stratixiv/u0/ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component/cmpr4/l1/u1
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_rx/gen_nof_streams(0)/u_dp_split
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_split(0)/u_dp_split
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1106/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0010_altera_merlin_slave_agent_tx_eth_pause_ctrl_gen_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0009_altera_merlin_slave_agent_tx_eth_packet_underflow_control_avalon_slave_0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0008_altera_merlin_slave_agent_tx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0007_altera_merlin_slave_agent_tx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0006_altera_merlin_slave_agent_tx_eth_address_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0005_altera_merlin_slave_agent_tx_eth_crc_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0004_altera_merlin_slave_agent_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1108/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0003_altera_merlin_slave_agent_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1032/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0002_altera_merlin_slave_agent_rx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add2_1080/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 2 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/tx_bridge_s0_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0001_altera_merlin_slave_agent_tx_bridge_s0_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1000/g1
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(0)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(1)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(2)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_bsn_monitor/gen_stream(3)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_wr/gen_cntr_wr(0)/cntr_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_3_ip/ipcore2rtl_hwn_nd_3_ip_wrapper_ip/eval_rd/gen_cntr_rd(0)/cntr_rd
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_wr/gen_cntr_wr(0)/cntr_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_2_ip/ipcore2rtl_hwn_nd_2_ip_wrapper_ip/eval_rd/gen_cntr_rd(0)/cntr_rd
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_wr/gen_cntr_wr(0)/cntr_wr
+# ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/gen_compaan/g_compaan_design/u_compaan_design/ipcore2rtl_hwn_nd_1_ip/ipcore2rtl_hwn_nd_1_ip_wrapper_ip/eval_rd/gen_cntr_rd(0)/cntr_rd
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(0)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(1)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(2)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_bsn_monitor/gen_stream(3)/u_reg/u_reg/gen_cross/gen_rd/u_in_vector
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 4 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_epcs
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 4 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy_reg/u_cross_domain_hdr
+# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 4 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_epcs
+# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
+# Time: 0 fs Iteration: 4 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/gen_mdio/u_tr_xaui_mdio/gen_nof_xaui(0)/u_mdio_phy_reg/u_cross_domain_hdr
+# ** Note: Stratix IV PLL was reset
+# Time: 0 fs Iteration: 5 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/gen_pll/u_unb1_board_clk200_pll/gen_0/u_st_pll/gen_ip_stratixiv/u0/altpll_component/stratixiii_altpll/m4
+# ** Note: Stratix IV PLL was reset
+# Time: 0 fs Iteration: 5 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/gen_clk25_pll/u_unb1_board_clk25_pll/u_pll/gen_ip_stratixiv/u0/altpll_component/stratixiii_altpll/m4
+# ** Note: Stratix IV PLL was reset
+# Time: 0 fs Iteration: 5 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/gen_pll/u_unb1_board_clk200_pll/gen_0/u_st_pll/gen_ip_stratixiv/u0/altpll_component/stratixiii_altpll/m4
+# ** Note: Stratix IV PLL was reset
+# Time: 0 fs Iteration: 5 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/gen_clk25_pll/u_unb1_board_clk25_pll/u_pll/gen_ip_stratixiv/u0/altpll_component/stratixiii_altpll/m4
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 6 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 6 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 6 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 6 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 fs Iteration: 6 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_mms_diag_block_gen/gen_bg/gen_streams(0)/u_diag_block_gen
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_dut/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0011_altera_merlin_slave_agent_rx_eth_crc_pad_rem_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0012_altera_merlin_slave_agent_rx_eth_frame_decoder_avalom_mm_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0013_altera_merlin_slave_agent_rx_eth_crc_checker_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0014_altera_merlin_slave_agent_rx_eth_lane_decoder_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0015_altera_merlin_slave_agent_rx_eth_packet_overflow_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0016_altera_merlin_slave_agent_rx_eth_pkt_backpressure_control_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 fs Iteration: 7 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_tr_10gbe/u_tech_eth_10g/gen_ip_stratixiv/u0/gen_mac(0)/u_tech_mac_10g/gen_ip_stratixiv/u0/u_ip_mac_10g/rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent/altera_merlin_slave_agent_0017_altera_merlin_slave_agent_rx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_altera_merlin_burst_uncompressor_uncompressor_add1_1030/g1
+# ** Note: Stratix IV PLL locked to incoming clock
+# Time: 300 ns Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/gen_clk25_pll/u_unb1_board_clk25_pll/u_pll/gen_ip_stratixiv/u0/altpll_component/stratixiii_altpll/m4
+# ** Note: Stratix IV PLL locked to incoming clock
+# Time: 300 ns Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/gen_clk25_pll/u_unb1_board_clk25_pll/u_pll/gen_ip_stratixiv/u0/altpll_component/stratixiii_altpll/m4
+# ** Note: Stratix IV PLL locked to incoming clock
+# Time: 402500 ps Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/gen_pll/u_unb1_board_clk200_pll/gen_0/u_st_pll/gen_ip_stratixiv/u0/altpll_component/stratixiii_altpll/m4
+# ** Note: Stratix IV PLL locked to incoming clock
+# Time: 402500 ps Iteration: 3 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/gen_pll/u_unb1_board_clk200_pll/gen_0/u_st_pll/gen_ip_stratixiv/u0/altpll_component/stratixiii_altpll/m4
+# [22940 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x0000016D to address 0x00000001
+# [22980 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x0000000A to address 0x00000002
+# [23020 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x00000BB8 to address 0x00000003
+# [23060 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x00000000 to address 0x00000004
+# [23100 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x000001FF to address 0x00000005
+# [23140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x0000000A to address 0x00000006
+# [23180 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x00000000 to address 0x00000007
+# [23920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0x8608000A to address 0x0000001C
+# ** Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2046296054 is not in bounds of NATURAL.
+# Time: 23920 ns Iteration: 9 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_inst_mmm_compaan_unb1_10g_bg_db/gen_mm_file_io/u_mm_file_reg_dp_offload_tx_hdr_dat
+# [24700 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0x00000022 to address 0x0000001D
+# [25440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0x4306C700 to address 0x0000001E
+# [26180 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0x00000007 to address 0x0000001F
+# ** Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2147483648 is not in bounds of NATURAL.
+# Time: 26242500 ps Iteration: 10 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_mm_fields_slv/u_common_reg_r_w_dc/gen_cross
+# [26920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0xC0A80166 to address 0x00000010
+# ** Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -1062731418 is not in bounds of NATURAL.
+# Time: 26920 ns Iteration: 9 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_inst_mmm_compaan_unb1_10g_bg_db/gen_mm_file_io/u_mm_file_reg_dp_offload_tx_hdr_dat
+# [27660 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0xC0A80102 to address 0x0000000F
+# ** Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -1062731518 is not in bounds of NATURAL.
+# Time: 27660 ns Iteration: 9 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_inst_mmm_compaan_unb1_10g_bg_db/gen_mm_file_io/u_mm_file_reg_dp_offload_tx_hdr_dat
+# [28400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0x00006C9C to address 0x00000011
+# [29140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0x8608000B to address 0x0000001C
+# ** Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2046296054 is not in bounds of NATURAL.
+# Time: 29140 ns Iteration: 9 Instance: /tb_compaan_unb1_10g_app/u_dut/u_inst_mmm_compaan_unb1_10g_app/gen_mm_file_io/u_mm_file_reg_dp_offload_tx_hdr_dat
+# [29880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0x00000022 to address 0x0000001D
+# [30620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0x4306C700 to address 0x0000001E
+# [31340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0x00000007 to address 0x0000001F
+# ** Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2147483648 is not in bounds of NATURAL.
+# Time: 31402500 ps Iteration: 10 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_mm_fields_slv/u_common_reg_r_w_dc/gen_cross
+# [32080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0xC0A80167 to address 0x00000010
+# ** Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -1062731418 is not in bounds of NATURAL.
+# Time: 32080 ns Iteration: 9 Instance: /tb_compaan_unb1_10g_app/u_dut/u_inst_mmm_compaan_unb1_10g_app/gen_mm_file_io/u_mm_file_reg_dp_offload_tx_hdr_dat
+# [32820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0xC0A80102 to address 0x0000000F
+# ** Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -1062731518 is not in bounds of NATURAL.
+# Time: 32820 ns Iteration: 9 Instance: /tb_compaan_unb1_10g_app/u_dut/u_inst_mmm_compaan_unb1_10g_app/gen_mm_file_io/u_mm_file_reg_dp_offload_tx_hdr_dat
+# [33560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_REG_DP_OFFLOAD_TX_HDR_DAT.ctrl: Writing 0x00006C9B to address 0x00000011
+# [34300 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x0000016D to address 0x00000001
+# [34340 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x0000000A to address 0x00000002
+# [34380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x00000BB8 to address 0x00000003
+# [34400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x00000000 to address 0x00000004
+# [34420 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x000001FF to address 0x00000005
+# [34440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x0000000A to address 0x00000006
+# [34460 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x00000000 to address 0x00000007
+# [35240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000000 to address 0x00000000
+# [35280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000001 to address 0x00000001
+# [35320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000002 to address 0x00000002
+# [35360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000003 to address 0x00000003
+# [35380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000004 to address 0x00000004
+# [35400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000005 to address 0x00000005
+# [35440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000006 to address 0x00000006
+# [35460 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000007 to address 0x00000007
+# [35500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000008 to address 0x00000008
+# [35520 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000009 to address 0x00000009
+# [35540 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000000A to address 0x0000000A
+# [35560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000000B to address 0x0000000B
+# [35580 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000000C to address 0x0000000C
+# [35600 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000000D to address 0x0000000D
+# [35620 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000000E to address 0x0000000E
+# [35640 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000000F to address 0x0000000F
+# [35680 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000010 to address 0x00000010
+# [35720 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000011 to address 0x00000011
+# [35760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000012 to address 0x00000012
+# [35800 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000013 to address 0x00000013
+# [35820 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000014 to address 0x00000014
+# [35860 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000015 to address 0x00000015
+# [35880 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000016 to address 0x00000016
+# [35900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000017 to address 0x00000017
+# [35920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000018 to address 0x00000018
+# [35940 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000019 to address 0x00000019
+# [35980 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000001A to address 0x0000001A
+# [36020 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000001B to address 0x0000001B
+# [36040 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000001C to address 0x0000001C
+# [36060 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000001D to address 0x0000001D
+# [36100 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000001E to address 0x0000001E
+# [36120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000001F to address 0x0000001F
+# [36160 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000020 to address 0x00000020
+# [36200 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000021 to address 0x00000021
+# [36240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000022 to address 0x00000022
+# [36280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000023 to address 0x00000023
+# [36320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000024 to address 0x00000024
+# [36360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000025 to address 0x00000025
+# [36400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000026 to address 0x00000026
+# [36420 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000027 to address 0x00000027
+# [36440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000028 to address 0x00000028
+# [36460 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000029 to address 0x00000029
+# [36500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000002A to address 0x0000002A
+# [36520 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000002B to address 0x0000002B
+# [36560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000002C to address 0x0000002C
+# [36600 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000002D to address 0x0000002D
+# [36640 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000002E to address 0x0000002E
+# [36660 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000002F to address 0x0000002F
+# [36680 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000030 to address 0x00000030
+# [36720 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000031 to address 0x00000031
+# [36740 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000032 to address 0x00000032
+# [36760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000033 to address 0x00000033
+# [36800 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000034 to address 0x00000034
+# [36820 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000035 to address 0x00000035
+# [36840 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000036 to address 0x00000036
+# [36860 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000037 to address 0x00000037
+# [36880 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000038 to address 0x00000038
+# [36900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000039 to address 0x00000039
+# [36940 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000003A to address 0x0000003A
+# [36960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000003B to address 0x0000003B
+# [36980 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000003C to address 0x0000003C
+# [37000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000003D to address 0x0000003D
+# [37020 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000003E to address 0x0000003E
+# [37060 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000003F to address 0x0000003F
+# [37080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000040 to address 0x00000040
+# [37120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000041 to address 0x00000041
+# [37140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000042 to address 0x00000042
+# [37160 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000043 to address 0x00000043
+# [37200 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000044 to address 0x00000044
+# [37220 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000045 to address 0x00000045
+# [37240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000046 to address 0x00000046
+# [37260 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000047 to address 0x00000047
+# [37280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000048 to address 0x00000048
+# [37300 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000049 to address 0x00000049
+# [37320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000004A to address 0x0000004A
+# [37360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000004B to address 0x0000004B
+# [37380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000004C to address 0x0000004C
+# [37400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000004D to address 0x0000004D
+# [37420 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000004E to address 0x0000004E
+# [37460 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000004F to address 0x0000004F
+# [37480 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000050 to address 0x00000050
+# [37500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000051 to address 0x00000051
+# [37540 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000052 to address 0x00000052
+# [37560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000053 to address 0x00000053
+# [37580 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000054 to address 0x00000054
+# [37600 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000055 to address 0x00000055
+# [37620 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000056 to address 0x00000056
+# [37640 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000057 to address 0x00000057
+# [37680 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000058 to address 0x00000058
+# [37700 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000059 to address 0x00000059
+# [37720 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000005A to address 0x0000005A
+# [37740 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000005B to address 0x0000005B
+# [37760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000005C to address 0x0000005C
+# [37780 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000005D to address 0x0000005D
+# [37800 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000005E to address 0x0000005E
+# [37840 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000005F to address 0x0000005F
+# [37880 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000060 to address 0x00000060
+# [37920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000061 to address 0x00000061
+# [37960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000062 to address 0x00000062
+# [37980 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000063 to address 0x00000063
+# [38000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000064 to address 0x00000064
+# [38020 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000065 to address 0x00000065
+# [38040 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000066 to address 0x00000066
+# [38080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000067 to address 0x00000067
+# [38120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000068 to address 0x00000068
+# [38160 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000069 to address 0x00000069
+# [38180 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000006A to address 0x0000006A
+# [38200 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000006B to address 0x0000006B
+# [38220 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000006C to address 0x0000006C
+# [38260 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000006D to address 0x0000006D
+# [38300 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000006E to address 0x0000006E
+# [38340 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000006F to address 0x0000006F
+# [38380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000070 to address 0x00000070
+# [38420 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000071 to address 0x00000071
+# [38440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000072 to address 0x00000072
+# [38480 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000073 to address 0x00000073
+# [38500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000074 to address 0x00000074
+# [38520 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000075 to address 0x00000075
+# [38560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000076 to address 0x00000076
+# [38580 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000077 to address 0x00000077
+# [38620 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000078 to address 0x00000078
+# [38660 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000079 to address 0x00000079
+# [38700 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000007A to address 0x0000007A
+# [38740 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000007B to address 0x0000007B
+# [38760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000007C to address 0x0000007C
+# [38800 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000007D to address 0x0000007D
+# [38840 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000007E to address 0x0000007E
+# [38880 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000007F to address 0x0000007F
+# [38900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000080 to address 0x00000080
+# [38920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000081 to address 0x00000081
+# [38940 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000082 to address 0x00000082
+# [38960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000083 to address 0x00000083
+# [38980 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000084 to address 0x00000084
+# [39000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000085 to address 0x00000085
+# [39020 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000086 to address 0x00000086
+# [39040 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000087 to address 0x00000087
+# [39080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000088 to address 0x00000088
+# [39100 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000089 to address 0x00000089
+# [39120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000008A to address 0x0000008A
+# [39140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000008B to address 0x0000008B
+# [39160 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000008C to address 0x0000008C
+# [39200 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000008D to address 0x0000008D
+# [39220 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000008E to address 0x0000008E
+# [39240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000008F to address 0x0000008F
+# [39260 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000090 to address 0x00000090
+# [39280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000091 to address 0x00000091
+# [39300 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000092 to address 0x00000092
+# [39320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000093 to address 0x00000093
+# [39340 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000094 to address 0x00000094
+# [39360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000095 to address 0x00000095
+# [39380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000096 to address 0x00000096
+# [39400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000097 to address 0x00000097
+# [39420 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000098 to address 0x00000098
+# [39440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000099 to address 0x00000099
+# [39480 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000009A to address 0x0000009A
+# [39520 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000009B to address 0x0000009B
+# [39560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000009C to address 0x0000009C
+# [39600 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000009D to address 0x0000009D
+# [39620 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000009E to address 0x0000009E
+# [39640 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000009F to address 0x0000009F
+# [39680 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000A0 to address 0x000000A0
+# [39720 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000A1 to address 0x000000A1
+# [39760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000A2 to address 0x000000A2
+# [39780 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000A3 to address 0x000000A3
+# [39820 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000A4 to address 0x000000A4
+# [39840 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000A5 to address 0x000000A5
+# [39860 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000A6 to address 0x000000A6
+# [39900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000A7 to address 0x000000A7
+# [39920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000A8 to address 0x000000A8
+# [39940 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000A9 to address 0x000000A9
+# [39960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000AA to address 0x000000AA
+# [40000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000AB to address 0x000000AB
+# [40020 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000AC to address 0x000000AC
+# [40040 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000AD to address 0x000000AD
+# [40080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000AE to address 0x000000AE
+# [40120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000AF to address 0x000000AF
+# [40140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000B0 to address 0x000000B0
+# [40180 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000B1 to address 0x000000B1
+# [40220 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000B2 to address 0x000000B2
+# [40260 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000B3 to address 0x000000B3
+# [40280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000B4 to address 0x000000B4
+# [40300 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000B5 to address 0x000000B5
+# [40320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000B6 to address 0x000000B6
+# [40340 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000B7 to address 0x000000B7
+# [40380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000B8 to address 0x000000B8
+# [40420 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000B9 to address 0x000000B9
+# [40440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000BA to address 0x000000BA
+# [40460 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000BB to address 0x000000BB
+# [40480 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000BC to address 0x000000BC
+# [40500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000BD to address 0x000000BD
+# [40520 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000BE to address 0x000000BE
+# [40540 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000BF to address 0x000000BF
+# [40560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000C0 to address 0x000000C0
+# [40580 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000C1 to address 0x000000C1
+# [40620 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000C2 to address 0x000000C2
+# [40660 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000C3 to address 0x000000C3
+# [40680 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000C4 to address 0x000000C4
+# [40700 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000C5 to address 0x000000C5
+# [40720 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000C6 to address 0x000000C6
+# [40760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000C7 to address 0x000000C7
+# [40780 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000C8 to address 0x000000C8
+# [40820 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000C9 to address 0x000000C9
+# [40860 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000CA to address 0x000000CA
+# [40900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000CB to address 0x000000CB
+# [40920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000CC to address 0x000000CC
+# [40940 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000CD to address 0x000000CD
+# [40960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000CE to address 0x000000CE
+# [41000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000CF to address 0x000000CF
+# [41040 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000D0 to address 0x000000D0
+# [41080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000D1 to address 0x000000D1
+# [41120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000D2 to address 0x000000D2
+# [41140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000D3 to address 0x000000D3
+# [41160 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000D4 to address 0x000000D4
+# [41180 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000D5 to address 0x000000D5
+# [41220 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000D6 to address 0x000000D6
+# [41240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000D7 to address 0x000000D7
+# [41260 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000D8 to address 0x000000D8
+# [41280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000D9 to address 0x000000D9
+# [41300 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000DA to address 0x000000DA
+# [41320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000DB to address 0x000000DB
+# [41340 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000DC to address 0x000000DC
+# [41380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000DD to address 0x000000DD
+# [41400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000DE to address 0x000000DE
+# [41440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000DF to address 0x000000DF
+# [41460 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000E0 to address 0x000000E0
+# [41500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000E1 to address 0x000000E1
+# [41540 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000E2 to address 0x000000E2
+# [41580 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000E3 to address 0x000000E3
+# [41620 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000E4 to address 0x000000E4
+# [41640 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000E5 to address 0x000000E5
+# [41680 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000E6 to address 0x000000E6
+# [41700 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000E7 to address 0x000000E7
+# [41740 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000E8 to address 0x000000E8
+# [41780 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000E9 to address 0x000000E9
+# [41820 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000EA to address 0x000000EA
+# [41860 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000EB to address 0x000000EB
+# [41880 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000EC to address 0x000000EC
+# [41900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000ED to address 0x000000ED
+# [41920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000EE to address 0x000000EE
+# [41960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000EF to address 0x000000EF
+# [41980 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000F0 to address 0x000000F0
+# [42000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000F1 to address 0x000000F1
+# [42020 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000F2 to address 0x000000F2
+# [42060 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000F3 to address 0x000000F3
+# [42080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000F4 to address 0x000000F4
+# [42100 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000F5 to address 0x000000F5
+# [42120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000F6 to address 0x000000F6
+# [42140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000F7 to address 0x000000F7
+# [42180 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000F8 to address 0x000000F8
+# [42200 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000F9 to address 0x000000F9
+# [42240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000FA to address 0x000000FA
+# [42260 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000FB to address 0x000000FB
+# [42300 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000FC to address 0x000000FC
+# [42320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000FD to address 0x000000FD
+# [42360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000FE to address 0x000000FE
+# [42380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000000FF to address 0x000000FF
+# [42420 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000100 to address 0x00000100
+# [42440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000101 to address 0x00000101
+# [42460 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000102 to address 0x00000102
+# [42500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000103 to address 0x00000103
+# [42520 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000104 to address 0x00000104
+# [42560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000105 to address 0x00000105
+# [42580 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000106 to address 0x00000106
+# [42600 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000107 to address 0x00000107
+# [42640 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000108 to address 0x00000108
+# [42660 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000109 to address 0x00000109
+# [42680 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000010A to address 0x0000010A
+# [42720 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000010B to address 0x0000010B
+# [42740 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000010C to address 0x0000010C
+# [42760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000010D to address 0x0000010D
+# [42800 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000010E to address 0x0000010E
+# [42840 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000010F to address 0x0000010F
+# [42860 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000110 to address 0x00000110
+# [42900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000111 to address 0x00000111
+# [42920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000112 to address 0x00000112
+# [42940 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000113 to address 0x00000113
+# [42960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000114 to address 0x00000114
+# [42980 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000115 to address 0x00000115
+# [43000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000116 to address 0x00000116
+# [43040 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000117 to address 0x00000117
+# [43080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000118 to address 0x00000118
+# [43100 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000119 to address 0x00000119
+# [43120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000011A to address 0x0000011A
+# [43140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000011B to address 0x0000011B
+# [43160 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000011C to address 0x0000011C
+# [43200 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000011D to address 0x0000011D
+# [43240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000011E to address 0x0000011E
+# [43260 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000011F to address 0x0000011F
+# [43300 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000120 to address 0x00000120
+# [43320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000121 to address 0x00000121
+# [43340 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000122 to address 0x00000122
+# [43360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000123 to address 0x00000123
+# [43380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000124 to address 0x00000124
+# [43400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000125 to address 0x00000125
+# [43420 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000126 to address 0x00000126
+# [43460 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000127 to address 0x00000127
+# [43500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000128 to address 0x00000128
+# [43540 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000129 to address 0x00000129
+# [43560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000012A to address 0x0000012A
+# [43600 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000012B to address 0x0000012B
+# [43640 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000012C to address 0x0000012C
+# [43660 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000012D to address 0x0000012D
+# [43700 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000012E to address 0x0000012E
+# [43740 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000012F to address 0x0000012F
+# [43780 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000130 to address 0x00000130
+# [43800 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000131 to address 0x00000131
+# [43820 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000132 to address 0x00000132
+# [43860 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000133 to address 0x00000133
+# [43900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000134 to address 0x00000134
+# [43940 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000135 to address 0x00000135
+# [43960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000136 to address 0x00000136
+# [44000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000137 to address 0x00000137
+# [44020 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000138 to address 0x00000138
+# [44040 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000139 to address 0x00000139
+# [44060 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000013A to address 0x0000013A
+# [44080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000013B to address 0x0000013B
+# [44120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000013C to address 0x0000013C
+# [44160 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000013D to address 0x0000013D
+# [44180 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000013E to address 0x0000013E
+# [44200 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000013F to address 0x0000013F
+# [44220 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000140 to address 0x00000140
+# [44240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000141 to address 0x00000141
+# [44280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000142 to address 0x00000142
+# [44320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000143 to address 0x00000143
+# [44340 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000144 to address 0x00000144
+# [44360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000145 to address 0x00000145
+# [44400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000146 to address 0x00000146
+# [44420 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000147 to address 0x00000147
+# [44440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000148 to address 0x00000148
+# [44480 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000149 to address 0x00000149
+# [44500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000014A to address 0x0000014A
+# [44520 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000014B to address 0x0000014B
+# [44540 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000014C to address 0x0000014C
+# [44560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000014D to address 0x0000014D
+# [44580 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000014E to address 0x0000014E
+# [44600 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000014F to address 0x0000014F
+# [44620 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000150 to address 0x00000150
+# [44660 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000151 to address 0x00000151
+# [44700 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000152 to address 0x00000152
+# [44740 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000153 to address 0x00000153
+# [44760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000154 to address 0x00000154
+# [44800 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000155 to address 0x00000155
+# [44840 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000156 to address 0x00000156
+# [44880 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000157 to address 0x00000157
+# [44900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000158 to address 0x00000158
+# [44920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000159 to address 0x00000159
+# [44960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000015A to address 0x0000015A
+# [45000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000015B to address 0x0000015B
+# [45040 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000015C to address 0x0000015C
+# [45080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000015D to address 0x0000015D
+# [45120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000015E to address 0x0000015E
+# [45140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000015F to address 0x0000015F
+# [45160 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000160 to address 0x00000160
+# [45200 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000161 to address 0x00000161
+# [45240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000162 to address 0x00000162
+# [45260 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000163 to address 0x00000163
+# [45280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000164 to address 0x00000164
+# [45300 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000165 to address 0x00000165
+# [45320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000166 to address 0x00000166
+# [45340 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000167 to address 0x00000167
+# [45360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000168 to address 0x00000168
+# [45380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000169 to address 0x00000169
+# [45400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000016A to address 0x0000016A
+# [45420 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000016B to address 0x0000016B
+# [45440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000016C to address 0x0000016C
+# [45480 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000016D to address 0x0000016D
+# [45500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000016E to address 0x0000016E
+# [45520 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000016F to address 0x0000016F
+# [45560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000170 to address 0x00000170
+# [45580 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000171 to address 0x00000171
+# [45600 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000172 to address 0x00000172
+# [45620 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000173 to address 0x00000173
+# [45640 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000174 to address 0x00000174
+# [45660 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000175 to address 0x00000175
+# [45680 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000176 to address 0x00000176
+# [45700 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000177 to address 0x00000177
+# [45720 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000178 to address 0x00000178
+# [45740 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000179 to address 0x00000179
+# [45760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000017A to address 0x0000017A
+# [45780 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000017B to address 0x0000017B
+# [45800 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000017C to address 0x0000017C
+# [45820 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000017D to address 0x0000017D
+# [45840 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000017E to address 0x0000017E
+# [45860 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000017F to address 0x0000017F
+# [45900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000180 to address 0x00000180
+# [45940 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000181 to address 0x00000181
+# [45960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000182 to address 0x00000182
+# [46000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000183 to address 0x00000183
+# [46040 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000184 to address 0x00000184
+# [46060 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000185 to address 0x00000185
+# [46100 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000186 to address 0x00000186
+# [46140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000187 to address 0x00000187
+# [46160 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000188 to address 0x00000188
+# [46180 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000189 to address 0x00000189
+# [46200 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000018A to address 0x0000018A
+# [46220 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000018B to address 0x0000018B
+# [46240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000018C to address 0x0000018C
+# [46260 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000018D to address 0x0000018D
+# [46280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000018E to address 0x0000018E
+# [46300 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000018F to address 0x0000018F
+# [46320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000190 to address 0x00000190
+# [46340 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000191 to address 0x00000191
+# [46360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000192 to address 0x00000192
+# [46380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000193 to address 0x00000193
+# [46400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000194 to address 0x00000194
+# [46440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000195 to address 0x00000195
+# [46480 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000196 to address 0x00000196
+# [46500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000197 to address 0x00000197
+# [46520 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000198 to address 0x00000198
+# [46560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x00000199 to address 0x00000199
+# [46580 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000019A to address 0x0000019A
+# [46600 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000019B to address 0x0000019B
+# [46640 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000019C to address 0x0000019C
+# [46660 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000019D to address 0x0000019D
+# [46680 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000019E to address 0x0000019E
+# [46720 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x0000019F to address 0x0000019F
+# [46760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001A0 to address 0x000001A0
+# [46800 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001A1 to address 0x000001A1
+# [46840 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001A2 to address 0x000001A2
+# [46880 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001A3 to address 0x000001A3
+# [46900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001A4 to address 0x000001A4
+# [46920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001A5 to address 0x000001A5
+# [46960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001A6 to address 0x000001A6
+# [47000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001A7 to address 0x000001A7
+# [47040 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001A8 to address 0x000001A8
+# [47060 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001A9 to address 0x000001A9
+# [47080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001AA to address 0x000001AA
+# [47100 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001AB to address 0x000001AB
+# [47120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001AC to address 0x000001AC
+# [47140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001AD to address 0x000001AD
+# [47180 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001AE to address 0x000001AE
+# [47220 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001AF to address 0x000001AF
+# [47240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001B0 to address 0x000001B0
+# [47260 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001B1 to address 0x000001B1
+# [47280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001B2 to address 0x000001B2
+# [47320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001B3 to address 0x000001B3
+# [47360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001B4 to address 0x000001B4
+# [47380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001B5 to address 0x000001B5
+# [47400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001B6 to address 0x000001B6
+# [47440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001B7 to address 0x000001B7
+# [47480 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001B8 to address 0x000001B8
+# [47500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001B9 to address 0x000001B9
+# [47520 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001BA to address 0x000001BA
+# [47540 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001BB to address 0x000001BB
+# [47560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001BC to address 0x000001BC
+# [47580 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001BD to address 0x000001BD
+# [47620 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001BE to address 0x000001BE
+# [47640 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001BF to address 0x000001BF
+# [47680 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001C0 to address 0x000001C0
+# [47720 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001C1 to address 0x000001C1
+# [47760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001C2 to address 0x000001C2
+# [47800 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001C3 to address 0x000001C3
+# [47820 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001C4 to address 0x000001C4
+# [47840 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001C5 to address 0x000001C5
+# [47860 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001C6 to address 0x000001C6
+# [47900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001C7 to address 0x000001C7
+# [47920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001C8 to address 0x000001C8
+# [47940 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001C9 to address 0x000001C9
+# [47960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001CA to address 0x000001CA
+# [48000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001CB to address 0x000001CB
+# [48020 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001CC to address 0x000001CC
+# [48040 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001CD to address 0x000001CD
+# [48080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001CE to address 0x000001CE
+# [48100 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001CF to address 0x000001CF
+# [48120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001D0 to address 0x000001D0
+# [48140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001D1 to address 0x000001D1
+# [48180 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001D2 to address 0x000001D2
+# [48200 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001D3 to address 0x000001D3
+# [48220 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001D4 to address 0x000001D4
+# [48240 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001D5 to address 0x000001D5
+# [48280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001D6 to address 0x000001D6
+# [48320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001D7 to address 0x000001D7
+# [48360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001D8 to address 0x000001D8
+# [48380 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001D9 to address 0x000001D9
+# [48400 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001DA to address 0x000001DA
+# [48440 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001DB to address 0x000001DB
+# [48480 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001DC to address 0x000001DC
+# [48500 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001DD to address 0x000001DD
+# [48520 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001DE to address 0x000001DE
+# [48540 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001DF to address 0x000001DF
+# [48560 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001E0 to address 0x000001E0
+# [48580 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001E1 to address 0x000001E1
+# [48600 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001E2 to address 0x000001E2
+# [48620 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001E3 to address 0x000001E3
+# [48660 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001E4 to address 0x000001E4
+# [48680 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001E5 to address 0x000001E5
+# [48700 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001E6 to address 0x000001E6
+# [48740 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001E7 to address 0x000001E7
+# [48760 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001E8 to address 0x000001E8
+# [48800 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001E9 to address 0x000001E9
+# [48820 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001EA to address 0x000001EA
+# [48860 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001EB to address 0x000001EB
+# [48880 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001EC to address 0x000001EC
+# [48900 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001ED to address 0x000001ED
+# [48920 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001EE to address 0x000001EE
+# [48940 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001EF to address 0x000001EF
+# [48960 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001F0 to address 0x000001F0
+# [48980 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001F1 to address 0x000001F1
+# [49000 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001F2 to address 0x000001F2
+# [49020 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001F3 to address 0x000001F3
+# [49060 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001F4 to address 0x000001F4
+# [49080 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001F5 to address 0x000001F5
+# [49100 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001F6 to address 0x000001F6
+# [49120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001F7 to address 0x000001F7
+# [49140 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001F8 to address 0x000001F8
+# [49160 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001F9 to address 0x000001F9
+# [49200 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001FA to address 0x000001FA
+# [49220 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001FB to address 0x000001FB
+# [49260 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001FC to address 0x000001FC
+# [49280 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001FD to address 0x000001FD
+# [49320 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001FE to address 0x000001FE
+# [49360 ns ] $UNB/Software/python/sim/UNB_0_FN_2_RAM_DIAG_BG.ctrl: Writing 0x000001FF to address 0x000001FF
+# [50120 ns ] $UNB/Software/python/sim/UNB_0_FN_2_REG_DIAG_BG.ctrl: Writing 0x00000001 to address 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 50202500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 50202500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [50620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000000: 0x00000000
+# [50700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000001: 0x00000000
+# [50780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000002: 0x00000000
+# [50860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000003: 0x00000000
+# [50940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000004: 0x00000000
+# [51020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000005: 0x00000000
+# [51100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000006: 0x00000000
+# [51180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000007: 0x00000000
+# [51260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000008: 0x00000000
+# [51340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000009: 0x00000000
+# [51420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000000A: 0x00000000
+# [51500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000000B: 0x00000000
+# [51580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000000C: 0x00000000
+# [51660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000000D: 0x00000000
+# [51740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000000E: 0x00000000
+# [51820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000000F: 0x00000000
+# [51900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000010: 0x00000000
+# [51980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000011: 0x00000000
+# [52060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000012: 0x00000000
+# [52140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000013: 0x00000000
+# [52220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000014: 0x00000000
+# [52300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000015: 0x00000000
+# [52380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000016: 0x00000000
+# [52460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000017: 0x00000000
+# [52540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000018: 0x00000000
+# [52600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000019: 0x00000000
+# [52680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000001A: 0x00000000
+# ** Warning: NUMERIC_STD.">": metavalue detected, returning FALSE
+# Time: 52700 ns Iteration: 11 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_ctrl_unb1_board/u_mms_unb1_board_sens
+# ** Warning: NUMERIC_STD.">": metavalue detected, returning FALSE
+# Time: 52700 ns Iteration: 11 Instance: /tb_compaan_unb1_10g_app/u_dut/u_ctrl_unb1_board/u_mms_unb1_board_sens
+# [52760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000001B: 0x00000000
+# [52840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000001C: 0x00000000
+# [52920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000001D: 0x00000000
+# [53000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000001E: 0x00000000
+# [53080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000001F: 0x00000000
+# [53160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000020: 0x00000000
+# [53240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000021: 0x00000000
+# [53320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000022: 0x00000000
+# [53400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000023: 0x00000000
+# [53480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000024: 0x00000000
+# [53560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000025: 0x00000000
+# [53640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000026: 0x00000000
+# [53720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000027: 0x00000000
+# [53800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000028: 0x00000000
+# [53880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000029: 0x00000000
+# [53960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000002A: 0x00000000
+# [54040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000002B: 0x00000000
+# [54120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000002C: 0x00000000
+# [54200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000002D: 0x00000000
+# [54280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000002E: 0x00000000
+# [54360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000002F: 0x00000000
+# [54440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000030: 0x00000000
+# [54520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000031: 0x00000000
+# [54600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000032: 0x00000000
+# [54680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000033: 0x00000000
+# [54760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000034: 0x00000000
+# [54840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000035: 0x00000000
+# [54920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000036: 0x00000000
+# [55000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000037: 0x00000000
+# [55080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000038: 0x00000000
+# [55160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000039: 0x00000000
+# [55240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000003A: 0x00000000
+# [55320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000003B: 0x00000000
+# [55400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000003C: 0x00000000
+# [55480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000003D: 0x00000000
+# [55560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000003E: 0x00000000
+# [55640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000003F: 0x00000000
+# [55720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000040: 0x00000000
+# [55800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000041: 0x00000000
+# [55880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000042: 0x00000000
+# [55960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000043: 0x00000000
+# [56040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000044: 0x00000000
+# [56120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000045: 0x00000000
+# [56200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000046: 0x00000000
+# [56280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000047: 0x00000000
+# [56360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000048: 0x00000000
+# [56440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000049: 0x00000000
+# [56520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000004A: 0x00000000
+# [56600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000004B: 0x00000000
+# [56680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000004C: 0x00000000
+# [56760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000004D: 0x00000000
+# [56840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000004E: 0x00000000
+# [56920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000004F: 0x00000000
+# [57000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000050: 0x00000000
+# [57080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000051: 0x00000000
+# [57160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000052: 0x00000000
+# [57240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000053: 0x00000000
+# [57320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000054: 0x00000000
+# [57400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000055: 0x00000000
+# [57480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000056: 0x00000000
+# [57560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000057: 0x00000000
+# [57640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000058: 0x00000000
+# [57720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000059: 0x00000000
+# [57800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000005A: 0x00000000
+# [57880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000005B: 0x00000000
+# [57960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000005C: 0x00000000
+# [58040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000005D: 0x00000000
+# [58120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000005E: 0x00000000
+# [58200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000005F: 0x00000000
+# [58280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000060: 0x00000000
+# [58360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000061: 0x00000000
+# [58440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000062: 0x00000000
+# [58520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000063: 0x00000000
+# [58600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000064: 0x00000000
+# [58680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000065: 0x00000000
+# [58760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000066: 0x00000000
+# [58840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000067: 0x00000000
+# [58920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000068: 0x00000000
+# [59000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000069: 0x00000000
+# [59080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000006A: 0x00000000
+# [59160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000006B: 0x00000000
+# [59240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000006C: 0x00000000
+# [59320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000006D: 0x00000000
+# [59400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000006E: 0x00000000
+# [59480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000006F: 0x00000000
+# [59560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000070: 0x00000000
+# [59640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000071: 0x00000000
+# [59720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000072: 0x00000000
+# [59800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000073: 0x00000000
+# [59880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000074: 0x00000000
+# [59960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000075: 0x00000000
+# [60040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000076: 0x00000000
+# [60120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000077: 0x00000000
+# [60200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000078: 0x00000000
+# [60280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000079: 0x00000000
+# [60360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000007A: 0x00000000
+# [60440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000007B: 0x00000000
+# [60520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000007C: 0x00000000
+# [60600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000007D: 0x00000000
+# [60680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000007E: 0x00000000
+# [60760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000007F: 0x00000000
+# [60840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000080: 0x00000000
+# [60920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000081: 0x00000000
+# [61000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000082: 0x00000000
+# [61080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000083: 0x00000000
+# [61160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000084: 0x00000000
+# [61240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000085: 0x00000000
+# [61320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000086: 0x00000000
+# [61400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000087: 0x00000000
+# [61480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000088: 0x00000000
+# [61560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000089: 0x00000000
+# [61640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000008A: 0x00000000
+# [61720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000008B: 0x00000000
+# [61800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000008C: 0x00000000
+# [61880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000008D: 0x00000000
+# [61960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000008E: 0x00000000
+# [62040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000008F: 0x00000000
+# [62120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000090: 0x00000000
+# [62200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000091: 0x00000000
+# [62280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000092: 0x00000000
+# [62360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000093: 0x00000000
+# [62440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000094: 0x00000000
+# [62520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000095: 0x00000000
+# [62600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000096: 0x00000000
+# [62680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000097: 0x00000000
+# [62760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000098: 0x00000000
+# [62840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000099: 0x00000000
+# [62920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000009A: 0x00000000
+# [63000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000009B: 0x00000000
+# [63080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000009C: 0x00000000
+# [63160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000009D: 0x00000000
+# [63240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000009E: 0x00000000
+# [63320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000009F: 0x00000000
+# [63400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000A0: 0x00000000
+# [63480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000A1: 0x00000000
+# [63560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000A2: 0x00000000
+# [63640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000A3: 0x00000000
+# [63720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000A4: 0x00000000
+# [63800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000A5: 0x00000000
+# [63880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000A6: 0x00000000
+# [63960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000A7: 0x00000000
+# [64040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000A8: 0x00000000
+# [64120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000A9: 0x00000000
+# [64200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000AA: 0x00000000
+# [64280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000AB: 0x00000000
+# [64360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000AC: 0x00000000
+# [64440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000AD: 0x00000000
+# [64520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000AE: 0x00000000
+# [64600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000AF: 0x00000000
+# [64680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000B0: 0x00000000
+# [64760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000B1: 0x00000000
+# [64840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000B2: 0x00000000
+# [64920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000B3: 0x00000000
+# [65000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000B4: 0x00000000
+# [65060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000B5: 0x00000000
+# [65140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000B6: 0x00000000
+# [65220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000B7: 0x00000000
+# [65300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000B8: 0x00000000
+# [65380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000B9: 0x00000000
+# [65460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000BA: 0x00000000
+# [65540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000BB: 0x00000000
+# [65620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000BC: 0x00000000
+# [65700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000BD: 0x00000000
+# [65780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000BE: 0x00000000
+# [65860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000BF: 0x00000000
+# [65940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000C0: 0x00000000
+# [66020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000C1: 0x00000000
+# [66100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000C2: 0x00000000
+# [66180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000C3: 0x00000000
+# [66260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000C4: 0x00000000
+# [66340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000C5: 0x00000000
+# [66420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000C6: 0x00000000
+# [66500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000C7: 0x00000000
+# [66580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000C8: 0x00000000
+# [66660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000C9: 0x00000000
+# [66740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000CA: 0x00000000
+# [66820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000CB: 0x00000000
+# [66900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000CC: 0x00000000
+# [66980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000CD: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 67027500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 67027500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [67060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000CE: 0x00000000
+# [67140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000CF: 0x00000000
+# [67220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000D0: 0x00000000
+# [67300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000D1: 0x00000000
+# [67380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000D2: 0x00000000
+# [67460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000D3: 0x00000000
+# [67520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000D4: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 67582500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 67582500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [67600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000D5: 0x00000000
+# [67680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000D6: 0x00000000
+# [67760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000D7: 0x00000000
+# [67820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000D8: 0x00000000
+# [67900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000D9: 0x00000000
+# [67980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000DA: 0x00000000
+# [68060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000DB: 0x00000000
+# [68140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000DC: 0x00000000
+# [68220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000DD: 0x00000000
+# [68300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000DE: 0x0000006E
+# [68380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000DF: 0x00000000
+# [68460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000E0: 0x0000006F
+# [68540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000E1: 0x00000000
+# [68620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000E2: 0x00000070
+# [68700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000E3: 0x00000000
+# [68780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000E4: 0x00000071
+# [68860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000E5: 0x00000000
+# [68940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000E6: 0x00000072
+# [69020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000E7: 0x00000000
+# [69100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000E8: 0x00000073
+# [69180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000E9: 0x00000000
+# [69260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000EA: 0x00000074
+# [69340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000EB: 0x00000000
+# [69420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000EC: 0x00000075
+# [69500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000ED: 0x00000000
+# [69580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000EE: 0x00000076
+# [69660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000EF: 0x00000000
+# [69740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000F0: 0x00000077
+# [69820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000F1: 0x00000000
+# [69900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000F2: 0x00000078
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 69927500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [69980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000F3: 0x00000000
+# [70060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000F4: 0x00000079
+# [70140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000F5: 0x00000000
+# [70220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000F6: 0x0000007A
+# [70300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000F7: 0x00000000
+# [70380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000F8: 0x0000007B
+# [70460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000F9: 0x00000000
+# [70520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000FA: 0x0000007C
+# [70600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000FB: 0x00000000
+# [70680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000FC: 0x0000007D
+# [70760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000FD: 0x00000000
+# [70840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000FE: 0x0000007E
+# [70920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000000FF: 0x00000000
+# [71000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000100: 0x0000007F
+# [71080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000101: 0x00000000
+# [71160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000102: 0x00000080
+# [71240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000103: 0x00000000
+# [71320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000104: 0x00000081
+# [71380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000105: 0x00000000
+# [71460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000106: 0x00000082
+# [71540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000107: 0x00000000
+# [71620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000108: 0x00000083
+# [71700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000109: 0x00000000
+# [71780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000010A: 0x00000084
+# [71860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000010B: 0x00000000
+# [71940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000010C: 0x00000085
+# [72020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000010D: 0x00000000
+# [72100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000010E: 0x00000086
+# [72180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000010F: 0x00000000
+# [72260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000110: 0x00000087
+# [72340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000111: 0x00000000
+# [72420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000112: 0x00000088
+# [72500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000113: 0x00000000
+# [72580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000114: 0x00000089
+# [72660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000115: 0x00000000
+# [72740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000116: 0x0000008A
+# [72820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000117: 0x00000000
+# [72900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000118: 0x0000008B
+# [72980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000119: 0x00000000
+# [73060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000011A: 0x0000008C
+# [73140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000011B: 0x00000000
+# [73220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000011C: 0x0000008D
+# [73300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000011D: 0x00000000
+# [73380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000011E: 0x0000008E
+# [73460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000011F: 0x00000000
+# [73540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000120: 0x0000008F
+# [73620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000121: 0x00000000
+# [73700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000122: 0x00000090
+# [73780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000123: 0x00000000
+# [73860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000124: 0x00000091
+# [73940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000125: 0x00000000
+# [74020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000126: 0x00000092
+# [74100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000127: 0x00000000
+# [74180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000128: 0x00000093
+# [74260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000129: 0x00000000
+# [74340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000012A: 0x00000094
+# [74420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000012B: 0x00000000
+# [74500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000012C: 0x00000095
+# [74580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000012D: 0x00000000
+# [74660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000012E: 0x00000096
+# [74740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000012F: 0x00000000
+# [74820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000130: 0x00000097
+# [74900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000131: 0x00000000
+# [74980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000132: 0x00000098
+# [75060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000133: 0x00000000
+# [75140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000134: 0x00000099
+# [75220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000135: 0x00000000
+# [75300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000136: 0x0000009A
+# [75380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000137: 0x00000000
+# [75460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000138: 0x0000009B
+# [75540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000139: 0x00000000
+# [75620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000013A: 0x0000009C
+# [75700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000013B: 0x00000000
+# [75780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000013C: 0x0000009D
+# [75860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000013D: 0x00000000
+# [75940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000013E: 0x0000009E
+# [76020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000013F: 0x00000000
+# [76100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000140: 0x0000009F
+# [76180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000141: 0x00000000
+# [76260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000142: 0x000000A0
+# [76340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000143: 0x00000000
+# [76420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000144: 0x000000A1
+# [76500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000145: 0x00000000
+# [76580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000146: 0x000000A2
+# [76660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000147: 0x00000000
+# [76740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000148: 0x000000A3
+# [76800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000149: 0x00000000
+# [76880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000014A: 0x000000A4
+# [76960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000014B: 0x00000000
+# [77040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000014C: 0x000000A5
+# [77120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000014D: 0x00000000
+# [77200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000014E: 0x000000A6
+# [77280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000014F: 0x00000000
+# [77360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000150: 0x000000A7
+# [77440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000151: 0x00000000
+# [77520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000152: 0x000000A8
+# [77600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000153: 0x00000000
+# [77680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000154: 0x000000A9
+# [77760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000155: 0x00000000
+# [77840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000156: 0x000000AA
+# [77920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000157: 0x00000000
+# [78000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000158: 0x000000AB
+# [78080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000159: 0x00000000
+# [78160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000015A: 0x000000AC
+# [78240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000015B: 0x00000000
+# [78320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000015C: 0x000000AD
+# [78400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000015D: 0x00000000
+# [78480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000015E: 0x000000AE
+# [78560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000015F: 0x00000000
+# [78640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000160: 0x000000AF
+# [78720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000161: 0x00000000
+# [78800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000162: 0x000000B0
+# [78880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000163: 0x00000000
+# [78960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000164: 0x000000B1
+# [79040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000165: 0x00000000
+# [79120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000166: 0x000000B2
+# [79200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000167: 0x00000000
+# [79280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000168: 0x000000B3
+# [79360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000169: 0x00000000
+# [79440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000016A: 0x000000B4
+# [79520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000016B: 0x00000000
+# [79600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000016C: 0x000000B5
+# [79680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000016D: 0x00000000
+# [79760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000016E: 0x000000B6
+# [79840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000016F: 0x00000000
+# [79920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000170: 0x000000B7
+# [80000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000171: 0x00000000
+# [80080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000172: 0x000000B8
+# [80160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000173: 0x00000000
+# [80240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000174: 0x000000B9
+# [80320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000175: 0x00000000
+# [80400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000176: 0x000000BA
+# [80480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000177: 0x00000000
+# [80560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000178: 0x000000BB
+# [80640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000179: 0x00000000
+# [80720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000017A: 0x000000BC
+# [80800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000017B: 0x00000000
+# [80880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000017C: 0x000000BD
+# [80960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000017D: 0x00000000
+# [81040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000017E: 0x000000BE
+# [81120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000017F: 0x00000000
+# [81200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000180: 0x000000BF
+# [81280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000181: 0x00000000
+# [81360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000182: 0x000000C0
+# [81440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000183: 0x00000000
+# [81520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000184: 0x000000C1
+# [81600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000185: 0x00000000
+# [81680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000186: 0x000000C2
+# [81760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000187: 0x00000000
+# [81840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000188: 0x000000C3
+# [81920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000189: 0x00000000
+# [82000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000018A: 0x000000C4
+# [82080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000018B: 0x00000000
+# [82160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000018C: 0x000000C5
+# [82240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000018D: 0x00000000
+# [82320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000018E: 0x000000C6
+# [82400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000018F: 0x00000000
+# [82480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000190: 0x000000C7
+# [82560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000191: 0x00000000
+# [82640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000192: 0x000000C8
+# [82720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000193: 0x00000000
+# [82800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000194: 0x000000C9
+# [82880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000195: 0x00000000
+# [82960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000196: 0x000000CA
+# [83040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000197: 0x00000000
+# [83100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000198: 0x000000CB
+# [83180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000199: 0x00000000
+# [83260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000019A: 0x000000CC
+# [83340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000019B: 0x00000000
+# [83420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000019C: 0x000000CD
+# [83500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000019D: 0x00000000
+# [83580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000019E: 0x000000CE
+# [83660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000019F: 0x00000000
+# [83740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001A0: 0x000000CF
+# [83820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001A1: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 83852500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 83852500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [83900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001A2: 0x000000D0
+# [83980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001A3: 0x00000000
+# [84060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001A4: 0x000000D1
+# [84140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001A5: 0x00000000
+# [84220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001A6: 0x000000D2
+# [84300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001A7: 0x00000000
+# [84380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001A8: 0x000000D3
+# [84460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001A9: 0x00000000
+# [84540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001AA: 0x000000D4
+# [84620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001AB: 0x00000000
+# [84700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001AC: 0x000000D5
+# [84780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001AD: 0x00000000
+# [84860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001AE: 0x000000D6
+# [84940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001AF: 0x00000000
+# [85020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001B0: 0x000000D7
+# [85100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001B1: 0x00000000
+# [85180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001B2: 0x000000D8
+# [85260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001B3: 0x00000000
+# [85340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001B4: 0x000000D9
+# [85420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001B5: 0x00000000
+# [85500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001B6: 0x000000DA
+# [85580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001B7: 0x00000000
+# [85660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001B8: 0x000000DB
+# [85740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001B9: 0x00000000
+# [85820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001BA: 0x000000DC
+# [85900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001BB: 0x00000000
+# [85980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001BC: 0x000000DD
+# [86060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001BD: 0x00000000
+# [86140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001BE: 0x000000DE
+# [86220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001BF: 0x00000000
+# [86300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001C0: 0x000000DF
+# [86380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001C1: 0x00000000
+# [86460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001C2: 0x000000E0
+# [86540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001C3: 0x00000000
+# [86620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001C4: 0x000000E1
+# [86700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001C5: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 86742500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [86780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001C6: 0x000000E2
+# [86860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001C7: 0x00000000
+# [86940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001C8: 0x000000E3
+# [87020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001C9: 0x00000000
+# [87100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001CA: 0x000000E4
+# [87180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001CB: 0x00000000
+# [87260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001CC: 0x000000E5
+# [87340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001CD: 0x00000000
+# [87420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001CE: 0x000000E6
+# [87500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001CF: 0x00000000
+# [87580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001D0: 0x000000E7
+# [87660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001D1: 0x00000000
+# [87720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001D2: 0x000000E8
+# [87780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001D3: 0x00000000
+# [87860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001D4: 0x000000E9
+# [87940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001D5: 0x00000000
+# [88020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001D6: 0x000000EA
+# [88100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001D7: 0x00000000
+# [88180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001D8: 0x000000EB
+# [88240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001D9: 0x00000000
+# [88320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001DA: 0x000000EC
+# [88400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001DB: 0x00000000
+# [88480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001DC: 0x000000ED
+# [88560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001DD: 0x00000000
+# [88640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001DE: 0x000000EE
+# [88720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001DF: 0x00000000
+# [88800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001E0: 0x000000EF
+# [88860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001E1: 0x00000000
+# [88940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001E2: 0x000000F0
+# [89020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001E3: 0x00000000
+# [89100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001E4: 0x000000F1
+# [89180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001E5: 0x00000000
+# [89260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001E6: 0x000000F2
+# [89340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001E7: 0x00000000
+# [89420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001E8: 0x000000F3
+# [89500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001E9: 0x00000000
+# [89580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001EA: 0x000000F4
+# [89660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001EB: 0x00000000
+# [89740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001EC: 0x000000F5
+# [89820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001ED: 0x00000000
+# [89900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001EE: 0x000000F6
+# [89980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001EF: 0x00000000
+# [90060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001F0: 0x000000F7
+# [90140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001F1: 0x00000000
+# [90220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001F2: 0x000000F8
+# [90300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001F3: 0x00000000
+# [90380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001F4: 0x000000F9
+# [90460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001F5: 0x00000000
+# [90540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001F6: 0x000000FA
+# [90620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001F7: 0x00000000
+# [90700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001F8: 0x000000FB
+# [90780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001F9: 0x00000000
+# [90860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001FA: 0x000000FC
+# [90940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001FB: 0x00000000
+# [91020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001FC: 0x000000FD
+# [91100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001FD: 0x00000000
+# [91180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001FE: 0x000000FE
+# [91260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000001FF: 0x00000000
+# [91340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000200: 0x000000FF
+# [91420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000201: 0x00000000
+# [91500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000202: 0x00000100
+# [91580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000203: 0x00000000
+# [91660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000204: 0x00000101
+# [91740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000205: 0x00000000
+# [91820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000206: 0x00000102
+# [91900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000207: 0x00000000
+# [91980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000208: 0x00000103
+# [92060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000209: 0x00000000
+# [92140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000020A: 0x00000104
+# [92220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000020B: 0x00000000
+# [92300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000020C: 0x00000105
+# [92380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000020D: 0x00000000
+# [92460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000020E: 0x00000106
+# [92540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000020F: 0x00000000
+# [92620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000210: 0x00000107
+# [92700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000211: 0x00000000
+# [92780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000212: 0x00000108
+# [92860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000213: 0x00000000
+# [92940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000214: 0x00000109
+# [93020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000215: 0x00000000
+# [93100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000216: 0x0000010A
+# [93180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000217: 0x00000000
+# [93260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000218: 0x0000010B
+# [93340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000219: 0x00000000
+# [93420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000021A: 0x0000010C
+# [93500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000021B: 0x00000000
+# [93580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000021C: 0x0000010D
+# [93660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000021D: 0x00000000
+# [93740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000021E: 0x0000010E
+# [93820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000021F: 0x00000000
+# [93900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000220: 0x0000010F
+# [93980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000221: 0x00000000
+# [94060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000222: 0x00000110
+# [94140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000223: 0x00000000
+# [94220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000224: 0x00000111
+# [94300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000225: 0x00000000
+# [94380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000226: 0x00000112
+# [94460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000227: 0x00000000
+# [94540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000228: 0x00000113
+# [94620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000229: 0x00000000
+# [94700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000022A: 0x00000114
+# [94780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000022B: 0x00000000
+# [94860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000022C: 0x00000115
+# [94940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000022D: 0x00000000
+# [95020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000022E: 0x00000116
+# [95100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000022F: 0x00000000
+# [95180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000230: 0x00000117
+# [95260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000231: 0x00000000
+# [95340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000232: 0x00000118
+# [95420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000233: 0x00000000
+# [95500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000234: 0x00000119
+# [95580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000235: 0x00000000
+# [95660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000236: 0x0000011A
+# [95740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000237: 0x00000000
+# [95820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000238: 0x0000011B
+# [95900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000239: 0x00000000
+# [95980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000023A: 0x0000011C
+# [96060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000023B: 0x00000000
+# [96140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000023C: 0x0000011D
+# [96220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000023D: 0x00000000
+# [96300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000023E: 0x0000011E
+# [96380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000023F: 0x00000000
+# [96460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000240: 0x0000011F
+# [96540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000241: 0x00000000
+# [96620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000242: 0x00000120
+# [96700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000243: 0x00000000
+# [96780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000244: 0x00000121
+# [96860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000245: 0x00000000
+# [96940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000246: 0x00000122
+# [97020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000247: 0x00000000
+# [97100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000248: 0x00000123
+# [97180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000249: 0x00000000
+# [97260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000024A: 0x00000124
+# [97340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000024B: 0x00000000
+# [97420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000024C: 0x00000125
+# [97500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000024D: 0x00000000
+# [97580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000024E: 0x00000126
+# [97660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000024F: 0x00000000
+# [97740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000250: 0x00000127
+# [97820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000251: 0x00000000
+# [97900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000252: 0x00000128
+# [97980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000253: 0x00000000
+# [98060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000254: 0x00000129
+# [98140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000255: 0x00000000
+# [98220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000256: 0x0000012A
+# [98300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000257: 0x00000000
+# [98380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000258: 0x0000012B
+# [98460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000259: 0x00000000
+# [98540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000025A: 0x0000012C
+# [98620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000025B: 0x00000000
+# [98700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000025C: 0x0000012D
+# [98780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000025D: 0x00000000
+# [98860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000025E: 0x0000012E
+# [98940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000025F: 0x00000000
+# [99020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000260: 0x0000012F
+# [99100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000261: 0x00000000
+# [99180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000262: 0x00000130
+# [99260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000263: 0x00000000
+# [99340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000264: 0x00000131
+# [99420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000265: 0x00000000
+# [99500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000266: 0x00000132
+# [99580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000267: 0x00000000
+# [99660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000268: 0x00000133
+# [99740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000269: 0x00000000
+# [99820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000026A: 0x00000134
+# [99900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000026B: 0x00000000
+# [99980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000026C: 0x00000135
+# [100060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000026D: 0x00000000
+# [100140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000026E: 0x00000136
+# [100220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000026F: 0x00000000
+# [100300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000270: 0x00000137
+# [100380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000271: 0x00000000
+# [100460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000272: 0x00000138
+# [100540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000273: 0x00000000
+# [100620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000274: 0x00000139
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 100677500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 100677500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [100700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000275: 0x00000000
+# [100780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000276: 0x0000013A
+# [100860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000277: 0x00000000
+# [100940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000278: 0x0000013B
+# [101020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000279: 0x00000000
+# [101100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000027A: 0x0000013C
+# [101160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000027B: 0x00000000
+# [101240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000027C: 0x0000013D
+# [101320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000027D: 0x00000000
+# [101400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000027E: 0x0000013E
+# [101480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000027F: 0x00000000
+# [101560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000280: 0x0000013F
+# [101640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000281: 0x00000000
+# [101720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000282: 0x00000140
+# [101800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000283: 0x00000000
+# [101880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000284: 0x00000141
+# [101960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000285: 0x00000000
+# [102040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000286: 0x00000142
+# [102120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000287: 0x00000000
+# [102200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000288: 0x00000143
+# [102280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000289: 0x00000000
+# [102360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000028A: 0x00000144
+# [102440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000028B: 0x00000000
+# [102520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000028C: 0x00000145
+# [102600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000028D: 0x00000000
+# [102680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000028E: 0x00000146
+# [102760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000028F: 0x00000000
+# [102840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000290: 0x00000147
+# [102920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000291: 0x00000000
+# [103000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000292: 0x00000148
+# [103080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000293: 0x00000000
+# [103160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000294: 0x00000149
+# [103240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000295: 0x00000000
+# [103320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000296: 0x0000014A
+# [103400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000297: 0x00000000
+# [103480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000298: 0x0000014B
+# [103560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000299: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 103562500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [103640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000029A: 0x0000014C
+# [103720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000029B: 0x00000000
+# [103800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000029C: 0x0000014D
+# [103880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000029D: 0x00000000
+# [103960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000029E: 0x0000014E
+# [104040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000029F: 0x00000000
+# [104120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002A0: 0x0000014F
+# [104200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002A1: 0x00000000
+# [104280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002A2: 0x00000150
+# [104360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002A3: 0x00000000
+# [104440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002A4: 0x00000151
+# [104520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002A5: 0x00000000
+# [104600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002A6: 0x00000152
+# [104680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002A7: 0x00000000
+# [104760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002A8: 0x00000153
+# [104840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002A9: 0x00000000
+# [104920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002AA: 0x00000154
+# [105000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002AB: 0x00000000
+# [105080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002AC: 0x00000155
+# [105160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002AD: 0x00000000
+# [105240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002AE: 0x00000156
+# [105320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002AF: 0x00000000
+# [105400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002B0: 0x00000157
+# [105480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002B1: 0x00000000
+# [105560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002B2: 0x00000158
+# [105640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002B3: 0x00000000
+# [105720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002B4: 0x00000159
+# [105800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002B5: 0x00000000
+# [105880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002B6: 0x0000015A
+# [105960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002B7: 0x00000000
+# [106040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002B8: 0x0000015B
+# [106120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002B9: 0x00000000
+# [106200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002BA: 0x0000015C
+# [106280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002BB: 0x00000000
+# [106360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002BC: 0x0000015D
+# [106440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002BD: 0x00000000
+# [106520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002BE: 0x0000015E
+# [106600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002BF: 0x00000000
+# [106680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002C0: 0x0000015F
+# [106760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002C1: 0x00000000
+# [106840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002C2: 0x00000160
+# [106920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002C3: 0x00000000
+# [107000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002C4: 0x00000161
+# [107080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002C5: 0x00000000
+# [107160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002C6: 0x00000162
+# [107240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002C7: 0x00000000
+# [107320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002C8: 0x00000163
+# [107400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002C9: 0x00000000
+# [107480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002CA: 0x00000164
+# [107560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002CB: 0x00000000
+# [107640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002CC: 0x00000165
+# [107720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002CD: 0x00000000
+# [107800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002CE: 0x00000166
+# [107880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002CF: 0x00000000
+# [107960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002D0: 0x00000167
+# [108040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002D1: 0x00000000
+# [108120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002D2: 0x00000168
+# [108200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002D3: 0x00000000
+# [108280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002D4: 0x00000169
+# [108360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002D5: 0x00000000
+# [108440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002D6: 0x0000016A
+# [108520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002D7: 0x00000000
+# [108600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002D8: 0x0000016B
+# [108680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002D9: 0x00000000
+# [108760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002DA: 0x0000016C
+# [108840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002DB: 0x00000000
+# [108920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002DC: 0x00000000
+# [109000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002DD: 0x00000000
+# [109080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002DE: 0x0000016D
+# [109160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002DF: 0x00000000
+# [109240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002E0: 0x0000016E
+# [109320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002E1: 0x00000000
+# [109400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002E2: 0x0000016F
+# [109480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002E3: 0x00000000
+# [109560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002E4: 0x00000170
+# [109640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002E5: 0x00000000
+# [109720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002E6: 0x00000171
+# [109800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002E7: 0x00000000
+# [109880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002E8: 0x00000172
+# [109960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002E9: 0x00000000
+# [110040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002EA: 0x00000173
+# [110120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002EB: 0x00000000
+# [110200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002EC: 0x00000174
+# [110280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002ED: 0x00000000
+# [110360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002EE: 0x00000175
+# [110440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002EF: 0x00000000
+# [110520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002F0: 0x00000176
+# [110600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002F1: 0x00000000
+# [110680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002F2: 0x00000177
+# [110760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002F3: 0x00000000
+# [110840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002F4: 0x00000178
+# [110920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002F5: 0x00000000
+# [111000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002F6: 0x00000179
+# [111080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002F7: 0x00000000
+# [111160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002F8: 0x0000017A
+# [111240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002F9: 0x00000000
+# [111320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002FA: 0x0000017B
+# [111400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002FB: 0x00000000
+# [111480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002FC: 0x0000017C
+# [111560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002FD: 0x00000000
+# [111640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002FE: 0x0000017D
+# [111720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000002FF: 0x00000000
+# [111800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000300: 0x0000017E
+# [111880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000301: 0x00000000
+# [111960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000302: 0x0000017F
+# [112040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000303: 0x00000000
+# [112120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000304: 0x00000180
+# [112200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000305: 0x00000000
+# [112280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000306: 0x00000181
+# [112360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000307: 0x00000000
+# [112440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000308: 0x00000182
+# [112520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000309: 0x00000000
+# [112600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000030A: 0x00000183
+# [112680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000030B: 0x00000000
+# [112760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000030C: 0x00000184
+# [112840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000030D: 0x00000000
+# [112920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000030E: 0x00000185
+# [113000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000030F: 0x00000000
+# [113080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000310: 0x00000186
+# [113160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000311: 0x00000000
+# [113240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000312: 0x00000187
+# [113320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000313: 0x00000000
+# [113400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000314: 0x00000188
+# [113480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000315: 0x00000000
+# [113560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000316: 0x00000189
+# [113620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000317: 0x00000000
+# [113700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000318: 0x0000018A
+# [113780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000319: 0x00000000
+# [113860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000031A: 0x0000018B
+# [113940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000031B: 0x00000000
+# [114020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000031C: 0x0000018C
+# [114100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000031D: 0x00000000
+# [114180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000031E: 0x0000018D
+# [114260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000031F: 0x00000000
+# [114340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000320: 0x0000018E
+# [114420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000321: 0x00000000
+# [114500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000322: 0x0000018F
+# [114580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000323: 0x00000000
+# [114660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000324: 0x00000190
+# [114740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000325: 0x00000000
+# [114820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000326: 0x00000191
+# [114900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000327: 0x00000000
+# [114980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000328: 0x00000192
+# [115060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000329: 0x00000000
+# [115140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000032A: 0x00000193
+# [115220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000032B: 0x00000000
+# [115300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000032C: 0x00000194
+# [115380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000032D: 0x00000000
+# [115460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000032E: 0x00000195
+# [115540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000032F: 0x00000000
+# [115620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000330: 0x00000196
+# [115700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000331: 0x00000000
+# [115780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000332: 0x00000197
+# [115860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000333: 0x00000000
+# [115940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000334: 0x00000198
+# [116020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000335: 0x00000000
+# [116100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000336: 0x00000199
+# [116180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000337: 0x00000000
+# [116260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000338: 0x0000019A
+# [116340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000339: 0x00000000
+# [116420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000033A: 0x0000019B
+# [116500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000033B: 0x00000000
+# [116580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000033C: 0x0000019C
+# [116660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000033D: 0x00000000
+# [116740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000033E: 0x0000019D
+# [116820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000033F: 0x00000000
+# [116900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000340: 0x0000019E
+# [116980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000341: 0x00000000
+# [117060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000342: 0x0000019F
+# [117140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000343: 0x00000000
+# [117220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000344: 0x000001A0
+# [117300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000345: 0x00000000
+# [117380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000346: 0x000001A1
+# [117460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000347: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 117502500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 117502500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [117540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000348: 0x000001A2
+# [117620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000349: 0x00000000
+# [117700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000034A: 0x000001A3
+# [117780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000034B: 0x00000000
+# [117860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000034C: 0x000001A4
+# [117940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000034D: 0x00000000
+# [118020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000034E: 0x000001A5
+# [118100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000034F: 0x00000000
+# [118180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000350: 0x000001A6
+# [118260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000351: 0x00000000
+# [118340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000352: 0x000001A7
+# [118420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000353: 0x00000000
+# [118500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000354: 0x000001A8
+# [118580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000355: 0x00000000
+# [118660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000356: 0x000001A9
+# [118740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000357: 0x00000000
+# [118820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000358: 0x000001AA
+# [118900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000359: 0x00000000
+# [118980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000035A: 0x000001AB
+# [119060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000035B: 0x00000000
+# [119140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000035C: 0x000001AC
+# [119220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000035D: 0x00000000
+# [119300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000035E: 0x000001AD
+# [119380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000035F: 0x00000000
+# [119460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000360: 0x000001AE
+# [119540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000361: 0x00000000
+# [119620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000362: 0x000001AF
+# [119700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000363: 0x00000000
+# [119780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000364: 0x000001B0
+# [119860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000365: 0x00000000
+# [119940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000366: 0x000001B1
+# [120020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000367: 0x00000000
+# [120100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000368: 0x000001B2
+# [120160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000369: 0x00000000
+# [120240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000036A: 0x000001B3
+# [120320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000036B: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 120377500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [120400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000036C: 0x000001B4
+# [120480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000036D: 0x00000000
+# [120560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000036E: 0x000001B5
+# [120620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000036F: 0x00000000
+# [120700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000370: 0x000001B6
+# [120780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000371: 0x00000000
+# [120860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000372: 0x000001B7
+# [120940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000373: 0x00000000
+# [121020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000374: 0x000001B8
+# [121100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000375: 0x00000000
+# [121180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000376: 0x000001B9
+# [121260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000377: 0x00000000
+# [121340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000378: 0x000001BA
+# [121420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000379: 0x00000000
+# [121500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000037A: 0x000001BB
+# [121580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000037B: 0x00000000
+# [121660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000037C: 0x000001BC
+# [121740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000037D: 0x00000000
+# [121820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000037E: 0x000001BD
+# [121900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000037F: 0x00000000
+# [121980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000380: 0x000001BE
+# [122060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000381: 0x00000000
+# [122140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000382: 0x000001BF
+# [122220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000383: 0x00000000
+# [122300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000384: 0x000001C0
+# [122380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000385: 0x00000000
+# [122460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000386: 0x000001C1
+# [122540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000387: 0x00000000
+# [122620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000388: 0x000001C2
+# [122700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000389: 0x00000000
+# [122780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000038A: 0x000001C3
+# [122860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000038B: 0x00000000
+# [122940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000038C: 0x000001C4
+# [123020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000038D: 0x00000000
+# [123100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000038E: 0x000001C5
+# [123180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000038F: 0x00000000
+# [123260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000390: 0x000001C6
+# [123340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000391: 0x00000000
+# [123420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000392: 0x000001C7
+# [123500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000393: 0x00000000
+# [123580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000394: 0x000001C8
+# [123660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000395: 0x00000000
+# [123740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000396: 0x000001C9
+# [123820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000397: 0x00000000
+# [123900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000398: 0x000001CA
+# [123980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000399: 0x00000000
+# [124060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000039A: 0x000001CB
+# [124140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000039B: 0x00000000
+# [124220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000039C: 0x000001CC
+# [124300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000039D: 0x00000000
+# [124380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000039E: 0x000001CD
+# [124460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000039F: 0x00000000
+# [124540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003A0: 0x000001CE
+# [124620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003A1: 0x00000000
+# [124700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003A2: 0x000001CF
+# [124780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003A3: 0x00000000
+# [124860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003A4: 0x000001D0
+# [124940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003A5: 0x00000000
+# [125020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003A6: 0x000001D1
+# [125100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003A7: 0x00000000
+# [125180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003A8: 0x000001D2
+# [125260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003A9: 0x00000000
+# [125340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003AA: 0x000001D3
+# [125420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003AB: 0x00000000
+# [125500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003AC: 0x000001D4
+# [125580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003AD: 0x00000000
+# [125660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003AE: 0x000001D5
+# [125720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003AF: 0x00000000
+# [125800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003B0: 0x000001D6
+# [125880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003B1: 0x00000000
+# [125960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003B2: 0x000001D7
+# [126040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003B3: 0x00000000
+# [126120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003B4: 0x000001D8
+# [126200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003B5: 0x00000000
+# [126280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003B6: 0x000001D9
+# [126360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003B7: 0x00000000
+# [126440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003B8: 0x000001DA
+# [126520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003B9: 0x00000000
+# [126600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003BA: 0x000001DB
+# [126680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003BB: 0x00000000
+# [126760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003BC: 0x000001DC
+# [126840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003BD: 0x00000000
+# [126920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003BE: 0x000001DD
+# [127000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003BF: 0x00000000
+# [127080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003C0: 0x000001DE
+# [127160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003C1: 0x00000000
+# [127240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003C2: 0x000001DF
+# [127320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003C3: 0x00000000
+# [127400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003C4: 0x000001E0
+# [127480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003C5: 0x00000000
+# [127560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003C6: 0x000001E1
+# [127640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003C7: 0x00000000
+# [127720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003C8: 0x000001E2
+# [127800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003C9: 0x00000000
+# [127880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003CA: 0x000001E3
+# [127960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003CB: 0x00000000
+# [128040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003CC: 0x000001E4
+# [128120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003CD: 0x00000000
+# [128200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003CE: 0x000001E5
+# [128280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003CF: 0x00000000
+# [128360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003D0: 0x000001E6
+# [128440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003D1: 0x00000000
+# [128520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003D2: 0x000001E7
+# [128600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003D3: 0x00000000
+# [128680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003D4: 0x000001E8
+# [128760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003D5: 0x00000000
+# [128840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003D6: 0x000001E9
+# [128920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003D7: 0x00000000
+# [129000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003D8: 0x000001EA
+# [129080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003D9: 0x00000000
+# [129160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003DA: 0x000001EB
+# [129240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003DB: 0x00000000
+# [129320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003DC: 0x000001EC
+# [129400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003DD: 0x00000000
+# [129480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003DE: 0x000001ED
+# [129560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003DF: 0x00000000
+# [129640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003E0: 0x000001EE
+# [129720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003E1: 0x00000000
+# [129800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003E2: 0x000001EF
+# [129880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003E3: 0x00000000
+# [129960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003E4: 0x000001F0
+# [130040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003E5: 0x00000000
+# [130120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003E6: 0x000001F1
+# [130200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003E7: 0x00000000
+# [130280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003E8: 0x000001F2
+# [130360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003E9: 0x00000000
+# [130440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003EA: 0x000001F3
+# [130520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003EB: 0x00000000
+# [130600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003EC: 0x000001F4
+# [130680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003ED: 0x00000000
+# [130760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003EE: 0x000001F5
+# [130840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003EF: 0x00000000
+# [130920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003F0: 0x000001F6
+# [131000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003F1: 0x00000000
+# [131080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003F2: 0x000001F7
+# [131160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003F3: 0x00000000
+# [131240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003F4: 0x000001F8
+# [131320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003F5: 0x00000000
+# [131400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003F6: 0x000001F9
+# [131480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003F7: 0x00000000
+# [131560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003F8: 0x000001FA
+# [131640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003F9: 0x00000000
+# [131720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003FA: 0x000001FB
+# [131800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003FB: 0x00000000
+# [131880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003FC: 0x000001FC
+# [131960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003FD: 0x00000000
+# [132020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003FE: 0x000001FD
+# [132100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000003FF: 0x00000000
+# [132180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000400: 0x000001FE
+# [132260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000401: 0x00000000
+# [132340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000402: 0x000001FF
+# [132420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000403: 0x00000000
+# [132500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000404: 0x00000000
+# [132580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000405: 0x00000000
+# [132660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000406: 0x00000001
+# [132740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000407: 0x00000000
+# [132820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000408: 0x00000002
+# [132900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000409: 0x00000000
+# [132980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000040A: 0x00000003
+# [133060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000040B: 0x00000000
+# [133140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000040C: 0x00000004
+# [133220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000040D: 0x00000000
+# [133300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000040E: 0x00000005
+# [133380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000040F: 0x00000000
+# [133460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000410: 0x00000006
+# [133540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000411: 0x00000000
+# [133620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000412: 0x00000007
+# [133700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000413: 0x00000000
+# [133780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000414: 0x00000008
+# [133860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000415: 0x00000000
+# [133940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000416: 0x00000009
+# [134020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000417: 0x00000000
+# [134100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000418: 0x0000000A
+# [134180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000419: 0x00000000
+# [134260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000041A: 0x0000000B
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 134327500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 134327500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [134340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000041B: 0x00000000
+# [134420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000041C: 0x0000000C
+# [134500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000041D: 0x00000000
+# [134580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000041E: 0x0000000D
+# [134660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000041F: 0x00000000
+# [134740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000420: 0x0000000E
+# [134820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000421: 0x00000000
+# [134900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000422: 0x0000000F
+# [134980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000423: 0x00000000
+# [135060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000424: 0x00000010
+# [135140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000425: 0x00000000
+# [135220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000426: 0x00000011
+# [135300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000427: 0x00000000
+# [135380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000428: 0x00000012
+# [135460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000429: 0x00000000
+# [135540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000042A: 0x00000013
+# [135620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000042B: 0x00000000
+# [135700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000042C: 0x00000014
+# [135780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000042D: 0x00000000
+# [135860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000042E: 0x00000015
+# [135940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000042F: 0x00000000
+# [136020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000430: 0x00000016
+# [136100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000431: 0x00000000
+# [136180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000432: 0x00000017
+# [136260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000433: 0x00000000
+# [136340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000434: 0x00000018
+# [136420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000435: 0x00000000
+# [136500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000436: 0x00000019
+# [136580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000437: 0x00000000
+# [136660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000438: 0x0000001A
+# [136740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000439: 0x00000000
+# [136820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000043A: 0x0000001B
+# [136900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000043B: 0x00000000
+# [136980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000043C: 0x0000001C
+# [137060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000043D: 0x00000000
+# [137140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000043E: 0x0000001D
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 137197500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [137220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000043F: 0x00000000
+# [137300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000440: 0x0000001E
+# [137380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000441: 0x00000000
+# [137460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000442: 0x0000001F
+# [137540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000443: 0x00000000
+# [137620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000444: 0x00000020
+# [137700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000445: 0x00000000
+# [137780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000446: 0x00000021
+# [137840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000447: 0x00000000
+# [137920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000448: 0x00000022
+# [138000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000449: 0x00000000
+# [138080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000044A: 0x00000023
+# [138160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000044B: 0x00000000
+# [138240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000044C: 0x00000024
+# [138320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000044D: 0x00000000
+# [138400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000044E: 0x00000025
+# [138480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000044F: 0x00000000
+# [138560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000450: 0x00000026
+# [138640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000451: 0x00000000
+# [138720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000452: 0x00000027
+# [138800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000453: 0x00000000
+# [138880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000454: 0x00000028
+# [138960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000455: 0x00000000
+# [139040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000456: 0x00000029
+# [139120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000457: 0x00000000
+# [139200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000458: 0x0000002A
+# [139280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000459: 0x00000000
+# [139360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000045A: 0x0000002B
+# [139440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000045B: 0x00000000
+# [139520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000045C: 0x0000002C
+# [139600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000045D: 0x00000000
+# [139680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000045E: 0x0000002D
+# [139760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000045F: 0x00000000
+# [139840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000460: 0x0000002E
+# [139920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000461: 0x00000000
+# [140000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000462: 0x0000002F
+# [140080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000463: 0x00000000
+# [140160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000464: 0x00000030
+# [140240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000465: 0x00000000
+# [140320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000466: 0x00000031
+# [140400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000467: 0x00000000
+# [140480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000468: 0x00000032
+# [140560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000469: 0x00000000
+# [140640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000046A: 0x00000033
+# [140720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000046B: 0x00000000
+# [140800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000046C: 0x00000034
+# [140880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000046D: 0x00000000
+# [140960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000046E: 0x00000035
+# [141040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000046F: 0x00000000
+# [141120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000470: 0x00000036
+# [141200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000471: 0x00000000
+# [141280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000472: 0x00000037
+# [141360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000473: 0x00000000
+# [141440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000474: 0x00000038
+# [141520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000475: 0x00000000
+# [141600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000476: 0x00000039
+# [141680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000477: 0x00000000
+# [141760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000478: 0x0000003A
+# [141840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000479: 0x00000000
+# [141920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000047A: 0x0000003B
+# [142000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000047B: 0x00000000
+# [142080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000047C: 0x0000003C
+# [142160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000047D: 0x00000000
+# [142240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000047E: 0x0000003D
+# [142320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000047F: 0x00000000
+# [142400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000480: 0x0000003E
+# [142480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000481: 0x00000000
+# [142560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000482: 0x0000003F
+# [142640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000483: 0x00000000
+# [142720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000484: 0x00000040
+# [142800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000485: 0x00000000
+# [142880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000486: 0x00000041
+# [142960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000487: 0x00000000
+# [143040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000488: 0x00000042
+# [143120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000489: 0x00000000
+# [143200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000048A: 0x00000043
+# [143280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000048B: 0x00000000
+# [143360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000048C: 0x00000044
+# [143440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000048D: 0x00000000
+# [143520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000048E: 0x00000045
+# [143600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000048F: 0x00000000
+# [143680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000490: 0x00000046
+# [143760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000491: 0x00000000
+# [143840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000492: 0x00000047
+# [143920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000493: 0x00000000
+# [144000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000494: 0x00000048
+# [144080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000495: 0x00000000
+# [144160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000496: 0x00000049
+# [144240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000497: 0x00000000
+# [144320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000498: 0x0000004A
+# [144400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000499: 0x00000000
+# [144480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000049A: 0x0000004B
+# [144560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000049B: 0x00000000
+# [144640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000049C: 0x0000004C
+# [144720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000049D: 0x00000000
+# [144800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000049E: 0x0000004D
+# [144880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000049F: 0x00000000
+# [144960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004A0: 0x0000004E
+# [145040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004A1: 0x00000000
+# [145120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004A2: 0x0000004F
+# [145200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004A3: 0x00000000
+# [145280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004A4: 0x00000050
+# [145360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004A5: 0x00000000
+# [145440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004A6: 0x00000051
+# [145520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004A7: 0x00000000
+# [145600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004A8: 0x00000052
+# [145680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004A9: 0x00000000
+# [145760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004AA: 0x00000053
+# [145840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004AB: 0x00000000
+# [145920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004AC: 0x00000054
+# [146000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004AD: 0x00000000
+# [146080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004AE: 0x00000055
+# [146160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004AF: 0x00000000
+# [146240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004B0: 0x00000056
+# [146320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004B1: 0x00000000
+# [146400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004B2: 0x00000057
+# [146480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004B3: 0x00000000
+# [146560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004B4: 0x00000058
+# [146640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004B5: 0x00000000
+# [146720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004B6: 0x00000059
+# [146800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004B7: 0x00000000
+# [146880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004B8: 0x0000005A
+# [146960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004B9: 0x00000000
+# [147040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004BA: 0x0000005B
+# [147120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004BB: 0x00000000
+# [147200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004BC: 0x0000005C
+# [147280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004BD: 0x00000000
+# [147360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004BE: 0x0000005D
+# [147440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004BF: 0x00000000
+# [147520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004C0: 0x0000005E
+# [147600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004C1: 0x00000000
+# [147680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004C2: 0x0000005F
+# [147760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004C3: 0x00000000
+# [147840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004C4: 0x00000060
+# [147920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004C5: 0x00000000
+# [148000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004C6: 0x00000061
+# [148080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004C7: 0x00000000
+# [148160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004C8: 0x00000062
+# [148240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004C9: 0x00000000
+# [148320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004CA: 0x00000063
+# [148400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004CB: 0x00000000
+# [148480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004CC: 0x00000064
+# [148560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004CD: 0x00000000
+# [148640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004CE: 0x00000065
+# [148720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004CF: 0x00000000
+# [148800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004D0: 0x00000066
+# [148880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004D1: 0x00000000
+# [148960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004D2: 0x00000067
+# [149040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004D3: 0x00000000
+# [149120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004D4: 0x00000068
+# [149200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004D5: 0x00000000
+# [149280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004D6: 0x00000069
+# [149360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004D7: 0x00000000
+# [149440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004D8: 0x0000006A
+# [149520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004D9: 0x00000000
+# [149600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004DA: 0x0000006B
+# [149680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004DB: 0x00000000
+# [149760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004DC: 0x0000006C
+# [149840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004DD: 0x00000000
+# [149920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004DE: 0x0000006D
+# [150000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004DF: 0x00000000
+# [150080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004E0: 0x0000006E
+# [150160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004E1: 0x00000000
+# [150240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004E2: 0x0000006F
+# [150320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004E3: 0x00000000
+# [150400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004E4: 0x00000070
+# [150460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004E5: 0x00000000
+# [150540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004E6: 0x00000071
+# [150620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004E7: 0x00000000
+# [150700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004E8: 0x00000072
+# [150780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004E9: 0x00000000
+# [150860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004EA: 0x00000073
+# [150940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004EB: 0x00000000
+# [151020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004EC: 0x00000074
+# [151100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004ED: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 151152500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 151152500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [151180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004EE: 0x00000075
+# [151260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004EF: 0x00000000
+# [151340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004F0: 0x00000076
+# [151420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004F1: 0x00000000
+# [151500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004F2: 0x00000077
+# [151580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004F3: 0x00000000
+# [151660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004F4: 0x00000078
+# [151740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004F5: 0x00000000
+# [151820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004F6: 0x00000079
+# [151900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004F7: 0x00000000
+# [151980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004F8: 0x0000007A
+# [152060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004F9: 0x00000000
+# [152140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004FA: 0x0000007B
+# [152220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004FB: 0x00000000
+# [152300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004FC: 0x0000007C
+# [152380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004FD: 0x00000000
+# [152460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004FE: 0x0000007D
+# [152540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000004FF: 0x00000000
+# [152620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000500: 0x0000007E
+# [152700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000501: 0x00000000
+# [152780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000502: 0x0000007F
+# [152860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000503: 0x00000000
+# [152940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000504: 0x00000080
+# [153020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000505: 0x00000000
+# [153100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000506: 0x00000081
+# [153180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000507: 0x00000000
+# [153260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000508: 0x00000082
+# [153340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000509: 0x00000000
+# [153420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000050A: 0x00000083
+# [153500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000050B: 0x00000000
+# [153580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000050C: 0x00000084
+# [153660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000050D: 0x00000000
+# [153740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000050E: 0x00000085
+# [153820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000050F: 0x00000000
+# [153900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000510: 0x00000086
+# [153980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000511: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 154017500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [154060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000512: 0x00000087
+# [154140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000513: 0x00000000
+# [154220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000514: 0x00000088
+# [154300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000515: 0x00000000
+# [154380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000516: 0x00000089
+# [154460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000517: 0x00000000
+# [154540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000518: 0x0000008A
+# [154620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000519: 0x00000000
+# [154700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000051A: 0x0000008B
+# [154780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000051B: 0x00000000
+# [154860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000051C: 0x0000008C
+# [154940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000051D: 0x00000000
+# [155020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000051E: 0x0000008D
+# [155100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000051F: 0x00000000
+# [155180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000520: 0x0000008E
+# [155260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000521: 0x00000000
+# [155340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000522: 0x0000008F
+# [155420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000523: 0x00000000
+# [155480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000524: 0x00000090
+# [155560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000525: 0x00000000
+# [155640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000526: 0x00000091
+# [155720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000527: 0x00000000
+# [155800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000528: 0x00000092
+# [155880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000529: 0x00000000
+# [155960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000052A: 0x00000093
+# [156040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000052B: 0x00000000
+# [156120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000052C: 0x00000094
+# [156200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000052D: 0x00000000
+# [156260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000052E: 0x00000095
+# [156320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000052F: 0x00000000
+# [156400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000530: 0x00000096
+# [156480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000531: 0x00000000
+# [156560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000532: 0x00000097
+# [156640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000533: 0x00000000
+# [156720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000534: 0x00000098
+# [156800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000535: 0x00000000
+# [156880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000536: 0x00000099
+# [156960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000537: 0x00000000
+# [157040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000538: 0x0000009A
+# [157120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000539: 0x00000000
+# [157200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000053A: 0x0000009B
+# [157280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000053B: 0x00000000
+# [157360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000053C: 0x0000009C
+# [157440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000053D: 0x00000000
+# [157520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000053E: 0x0000009D
+# [157600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000053F: 0x00000000
+# [157680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000540: 0x0000009E
+# [157760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000541: 0x00000000
+# [157840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000542: 0x0000009F
+# [157920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000543: 0x00000000
+# [158000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000544: 0x000000A0
+# [158080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000545: 0x00000000
+# [158160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000546: 0x000000A1
+# [158240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000547: 0x00000000
+# [158320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000548: 0x000000A2
+# [158400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000549: 0x00000000
+# [158480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000054A: 0x000000A3
+# [158560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000054B: 0x00000000
+# [158640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000054C: 0x000000A4
+# [158720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000054D: 0x00000000
+# [158800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000054E: 0x000000A5
+# [158880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000054F: 0x00000000
+# [158960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000550: 0x000000A6
+# [159040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000551: 0x00000000
+# [159120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000552: 0x000000A7
+# [159200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000553: 0x00000000
+# [159280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000554: 0x000000A8
+# [159360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000555: 0x00000000
+# [159440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000556: 0x000000A9
+# [159520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000557: 0x00000000
+# [159600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000558: 0x000000AA
+# [159680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000559: 0x00000000
+# [159760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000055A: 0x000000AB
+# [159840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000055B: 0x00000000
+# [159920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000055C: 0x000000AC
+# [160000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000055D: 0x00000000
+# [160080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000055E: 0x000000AD
+# [160160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000055F: 0x00000000
+# [160240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000560: 0x000000AE
+# [160320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000561: 0x00000000
+# [160400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000562: 0x000000AF
+# [160480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000563: 0x00000000
+# [160560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000564: 0x000000B0
+# [160640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000565: 0x00000000
+# [160720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000566: 0x000000B1
+# [160800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000567: 0x00000000
+# [160880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000568: 0x000000B2
+# [160960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000569: 0x00000000
+# [161040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000056A: 0x000000B3
+# [161120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000056B: 0x00000000
+# [161200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000056C: 0x000000B4
+# [161280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000056D: 0x00000000
+# [161360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000056E: 0x000000B5
+# [161440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000056F: 0x00000000
+# [161520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000570: 0x000000B6
+# [161600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000571: 0x00000000
+# [161680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000572: 0x000000B7
+# [161760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000573: 0x00000000
+# [161840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000574: 0x000000B8
+# [161920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000575: 0x00000000
+# [162000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000576: 0x000000B9
+# [162080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000577: 0x00000000
+# [162160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000578: 0x000000BA
+# [162240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000579: 0x00000000
+# [162320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000057A: 0x000000BB
+# [162400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000057B: 0x00000000
+# [162480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000057C: 0x000000BC
+# [162560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000057D: 0x00000000
+# [162640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000057E: 0x000000BD
+# [162720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000057F: 0x00000000
+# [162800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000580: 0x000000BE
+# [162880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000581: 0x00000000
+# [162960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000582: 0x000000BF
+# [163040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000583: 0x00000000
+# [163120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000584: 0x000000C0
+# [163200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000585: 0x00000000
+# [163280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000586: 0x000000C1
+# [163360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000587: 0x00000000
+# [163440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000588: 0x000000C2
+# [163520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000589: 0x00000000
+# [163600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000058A: 0x000000C3
+# [163680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000058B: 0x00000000
+# [163760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000058C: 0x000000C4
+# [163840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000058D: 0x00000000
+# [163920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000058E: 0x000000C5
+# [164000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000058F: 0x00000000
+# [164080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000590: 0x000000C6
+# [164160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000591: 0x00000000
+# [164240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000592: 0x000000C7
+# [164320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000593: 0x00000000
+# [164400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000594: 0x000000C8
+# [164480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000595: 0x00000000
+# [164560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000596: 0x000000C9
+# [164640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000597: 0x00000000
+# [164720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000598: 0x000000CA
+# [164800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000599: 0x00000000
+# [164880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000059A: 0x000000CB
+# [164960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000059B: 0x00000000
+# [165040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000059C: 0x000000CC
+# [165120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000059D: 0x00000000
+# [165200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000059E: 0x000000CD
+# [165280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000059F: 0x00000000
+# [165360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005A0: 0x000000CE
+# [165440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005A1: 0x00000000
+# [165520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005A2: 0x000000CF
+# [165600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005A3: 0x00000000
+# [165680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005A4: 0x000000D0
+# [165760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005A5: 0x00000000
+# [165840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005A6: 0x000000D1
+# [165920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005A7: 0x00000000
+# [166000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005A8: 0x000000D2
+# [166080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005A9: 0x00000000
+# [166160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005AA: 0x000000D3
+# [166240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005AB: 0x00000000
+# [166320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005AC: 0x000000D4
+# [166400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005AD: 0x00000000
+# [166480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005AE: 0x000000D5
+# [166560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005AF: 0x00000000
+# [166640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005B0: 0x000000D6
+# [166720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005B1: 0x00000000
+# [166800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005B2: 0x000000D7
+# [166880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005B3: 0x00000000
+# [166960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005B4: 0x000000D8
+# [167040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005B5: 0x00000000
+# [167120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005B6: 0x000000D9
+# [167200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005B7: 0x00000000
+# [167280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005B8: 0x00000000
+# [167360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005B9: 0x00000000
+# [167440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005BA: 0x000000DA
+# [167520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005BB: 0x00000000
+# [167600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005BC: 0x000000DB
+# [167680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005BD: 0x00000000
+# [167760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005BE: 0x000000DC
+# [167840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005BF: 0x00000000
+# [167920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005C0: 0x000000DD
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 167977500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 167977500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [168000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005C1: 0x00000000
+# [168080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005C2: 0x000000DE
+# [168160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005C3: 0x00000000
+# [168240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005C4: 0x000000DF
+# [168320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005C5: 0x00000000
+# [168400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005C6: 0x000000E0
+# [168480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005C7: 0x00000000
+# [168540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005C8: 0x000000E1
+# [168620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005C9: 0x00000000
+# [168700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005CA: 0x000000E2
+# [168780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005CB: 0x00000000
+# [168860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005CC: 0x000000E3
+# [168940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005CD: 0x00000000
+# [169020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005CE: 0x000000E4
+# [169100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005CF: 0x00000000
+# [169180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005D0: 0x000000E5
+# [169260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005D1: 0x00000000
+# [169340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005D2: 0x000000E6
+# [169420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005D3: 0x00000000
+# [169500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005D4: 0x000000E7
+# [169580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005D5: 0x00000000
+# [169660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005D6: 0x000000E8
+# [169740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005D7: 0x00000000
+# [169820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005D8: 0x000000E9
+# [169900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005D9: 0x00000000
+# [169980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005DA: 0x000000EA
+# [170060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005DB: 0x00000000
+# [170140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005DC: 0x000000EB
+# [170220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005DD: 0x00000000
+# [170300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005DE: 0x000000EC
+# [170380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005DF: 0x00000000
+# [170460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005E0: 0x000000ED
+# [170540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005E1: 0x00000000
+# [170620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005E2: 0x000000EE
+# [170700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005E3: 0x00000000
+# [170780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005E4: 0x000000EF
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 170837500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [170860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005E5: 0x00000000
+# [170940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005E6: 0x000000F0
+# [171020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005E7: 0x00000000
+# [171100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005E8: 0x000000F1
+# [171180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005E9: 0x00000000
+# [171260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005EA: 0x000000F2
+# [171340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005EB: 0x00000000
+# [171420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005EC: 0x000000F3
+# [171500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005ED: 0x00000000
+# [171580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005EE: 0x000000F4
+# [171660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005EF: 0x00000000
+# [171740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005F0: 0x000000F5
+# [171820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005F1: 0x00000000
+# [171900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005F2: 0x000000F6
+# [171980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005F3: 0x00000000
+# [172060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005F4: 0x000000F7
+# [172140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005F5: 0x00000000
+# [172220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005F6: 0x000000F8
+# [172300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005F7: 0x00000000
+# [172380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005F8: 0x000000F9
+# [172460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005F9: 0x00000000
+# [172540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005FA: 0x000000FA
+# [172620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005FB: 0x00000000
+# [172700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005FC: 0x000000FB
+# [172780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005FD: 0x00000000
+# [172860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005FE: 0x000000FC
+# [172940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000005FF: 0x00000000
+# [173020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000600: 0x000000FD
+# [173100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000601: 0x00000000
+# [173180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000602: 0x000000FE
+# [173260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000603: 0x00000000
+# [173340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000604: 0x000000FF
+# [173420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000605: 0x00000000
+# [173500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000606: 0x00000100
+# [173580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000607: 0x00000000
+# [173660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000608: 0x00000101
+# [173740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000609: 0x00000000
+# [173820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000060A: 0x00000102
+# [173900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000060B: 0x00000000
+# [173980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000060C: 0x00000103
+# [174060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000060D: 0x00000000
+# [174140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000060E: 0x00000104
+# [174220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000060F: 0x00000000
+# [174300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000610: 0x00000105
+# [174380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000611: 0x00000000
+# [174460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000612: 0x00000106
+# [174540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000613: 0x00000000
+# [174620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000614: 0x00000107
+# [174680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000615: 0x00000000
+# [174760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000616: 0x00000108
+# [174840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000617: 0x00000000
+# [174920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000618: 0x00000109
+# [175000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000619: 0x00000000
+# [175080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000061A: 0x0000010A
+# [175160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000061B: 0x00000000
+# [175240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000061C: 0x0000010B
+# [175320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000061D: 0x00000000
+# [175400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000061E: 0x0000010C
+# [175480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000061F: 0x00000000
+# [175560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000620: 0x0000010D
+# [175640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000621: 0x00000000
+# [175720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000622: 0x0000010E
+# [175800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000623: 0x00000000
+# [175880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000624: 0x0000010F
+# [175960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000625: 0x00000000
+# [176040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000626: 0x00000110
+# [176120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000627: 0x00000000
+# [176200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000628: 0x00000111
+# [176280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000629: 0x00000000
+# [176360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000062A: 0x00000112
+# [176440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000062B: 0x00000000
+# [176520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000062C: 0x00000113
+# [176600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000062D: 0x00000000
+# [176680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000062E: 0x00000114
+# [176760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000062F: 0x00000000
+# [176840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000630: 0x00000115
+# [176920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000631: 0x00000000
+# [177000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000632: 0x00000116
+# [177080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000633: 0x00000000
+# [177160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000634: 0x00000117
+# [177240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000635: 0x00000000
+# [177320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000636: 0x00000118
+# [177400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000637: 0x00000000
+# [177480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000638: 0x00000119
+# [177560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000639: 0x00000000
+# [177640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000063A: 0x0000011A
+# [177720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000063B: 0x00000000
+# [177800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000063C: 0x0000011B
+# [177880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000063D: 0x00000000
+# [177960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000063E: 0x0000011C
+# [178040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000063F: 0x00000000
+# [178120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000640: 0x0000011D
+# [178200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000641: 0x00000000
+# [178280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000642: 0x0000011E
+# [178360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000643: 0x00000000
+# [178440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000644: 0x0000011F
+# [178520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000645: 0x00000000
+# [178600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000646: 0x00000120
+# [178680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000647: 0x00000000
+# [178760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000648: 0x00000121
+# [178840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000649: 0x00000000
+# [178920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000064A: 0x00000122
+# [179000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000064B: 0x00000000
+# [179080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000064C: 0x00000123
+# [179160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000064D: 0x00000000
+# [179240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000064E: 0x00000124
+# [179320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000064F: 0x00000000
+# [179400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000650: 0x00000125
+# [179480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000651: 0x00000000
+# [179560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000652: 0x00000126
+# [179640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000653: 0x00000000
+# [179720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000654: 0x00000127
+# [179800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000655: 0x00000000
+# [179880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000656: 0x00000128
+# [179960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000657: 0x00000000
+# [180040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000658: 0x00000129
+# [180120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000659: 0x00000000
+# [180200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000065A: 0x0000012A
+# [180280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000065B: 0x00000000
+# [180360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000065C: 0x0000012B
+# [180440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000065D: 0x00000000
+# [180520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000065E: 0x0000012C
+# [180600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000065F: 0x00000000
+# [180680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000660: 0x0000012D
+# [180760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000661: 0x00000000
+# [180840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000662: 0x0000012E
+# [180920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000663: 0x00000000
+# [180980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000664: 0x0000012F
+# [181060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000665: 0x00000000
+# [181140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000666: 0x00000130
+# [181220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000667: 0x00000000
+# [181300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000668: 0x00000131
+# [181380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000669: 0x00000000
+# [181460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000066A: 0x00000132
+# [181540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000066B: 0x00000000
+# [181620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000066C: 0x00000133
+# [181700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000066D: 0x00000000
+# [181780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000066E: 0x00000134
+# [181860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000066F: 0x00000000
+# [181940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000670: 0x00000135
+# [182020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000671: 0x00000000
+# [182100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000672: 0x00000136
+# [182180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000673: 0x00000000
+# [182260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000674: 0x00000137
+# [182340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000675: 0x00000000
+# [182420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000676: 0x00000138
+# [182500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000677: 0x00000000
+# [182580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000678: 0x00000139
+# [182660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000679: 0x00000000
+# [182740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000067A: 0x0000013A
+# [182820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000067B: 0x00000000
+# [182900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000067C: 0x0000013B
+# [182980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000067D: 0x00000000
+# [183060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000067E: 0x0000013C
+# [183140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000067F: 0x00000000
+# [183220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000680: 0x0000013D
+# [183300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000681: 0x00000000
+# [183380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000682: 0x0000013E
+# [183460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000683: 0x00000000
+# [183540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000684: 0x0000013F
+# [183620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000685: 0x00000000
+# [183700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000686: 0x00000140
+# [183780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000687: 0x00000000
+# [183860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000688: 0x00000141
+# [183940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000689: 0x00000000
+# [184020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000068A: 0x00000142
+# [184100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000068B: 0x00000000
+# [184180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000068C: 0x00000143
+# [184260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000068D: 0x00000000
+# [184340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000068E: 0x00000144
+# [184420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000068F: 0x00000000
+# [184500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000690: 0x00000145
+# [184580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000691: 0x00000000
+# [184660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000692: 0x00000146
+# [184740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000693: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 184802500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 184802500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [184820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000694: 0x00000147
+# [184900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000695: 0x00000000
+# [184980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000696: 0x00000148
+# [185060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000697: 0x00000000
+# [185140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000698: 0x00000149
+# [185220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000699: 0x00000000
+# [185300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000069A: 0x0000014A
+# [185380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000069B: 0x00000000
+# [185460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000069C: 0x0000014B
+# [185540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000069D: 0x00000000
+# [185620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000069E: 0x0000014C
+# [185700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000069F: 0x00000000
+# [185780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006A0: 0x0000014D
+# [185860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006A1: 0x00000000
+# [185940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006A2: 0x0000014E
+# [186020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006A3: 0x00000000
+# [186100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006A4: 0x0000014F
+# [186180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006A5: 0x00000000
+# [186260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006A6: 0x00000150
+# [186340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006A7: 0x00000000
+# [186420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006A8: 0x00000151
+# [186500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006A9: 0x00000000
+# [186580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006AA: 0x00000152
+# [186660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006AB: 0x00000000
+# [186740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006AC: 0x00000153
+# [186820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006AD: 0x00000000
+# [186900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006AE: 0x00000154
+# [186960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006AF: 0x00000000
+# [187040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006B0: 0x00000155
+# [187120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006B1: 0x00000000
+# [187200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006B2: 0x00000156
+# [187280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006B3: 0x00000000
+# [187360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006B4: 0x00000157
+# [187440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006B5: 0x00000000
+# [187520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006B6: 0x00000158
+# [187600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006B7: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 187647500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [187680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006B8: 0x00000159
+# [187760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006B9: 0x00000000
+# [187840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006BA: 0x0000015A
+# [187920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006BB: 0x00000000
+# [188000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006BC: 0x0000015B
+# [188080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006BD: 0x00000000
+# [188160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006BE: 0x0000015C
+# [188240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006BF: 0x00000000
+# [188320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006C0: 0x0000015D
+# [188400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006C1: 0x00000000
+# [188480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006C2: 0x0000015E
+# [188560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006C3: 0x00000000
+# [188640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006C4: 0x0000015F
+# [188720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006C5: 0x00000000
+# [188800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006C6: 0x00000160
+# [188880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006C7: 0x00000000
+# [188960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006C8: 0x00000161
+# [189040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006C9: 0x00000000
+# [189120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006CA: 0x00000162
+# [189200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006CB: 0x00000000
+# [189280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006CC: 0x00000163
+# [189360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006CD: 0x00000000
+# [189440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006CE: 0x00000164
+# [189520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006CF: 0x00000000
+# [189600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006D0: 0x00000165
+# [189680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006D1: 0x00000000
+# [189760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006D2: 0x00000166
+# [189840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006D3: 0x00000000
+# [189920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006D4: 0x00000167
+# [190000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006D5: 0x00000000
+# [190080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006D6: 0x00000168
+# [190160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006D7: 0x00000000
+# [190240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006D8: 0x00000169
+# [190320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006D9: 0x00000000
+# [190400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006DA: 0x0000016A
+# [190480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006DB: 0x00000000
+# [190560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006DC: 0x0000016B
+# [190640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006DD: 0x00000000
+# [190720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006DE: 0x0000016C
+# [190800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006DF: 0x00000000
+# [190880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006E0: 0x0000016D
+# [190960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006E1: 0x00000000
+# [191040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006E2: 0x0000016E
+# [191120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006E3: 0x00000000
+# [191200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006E4: 0x0000016F
+# [191280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006E5: 0x00000000
+# [191360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006E6: 0x00000170
+# [191440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006E7: 0x00000000
+# [191520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006E8: 0x00000171
+# [191600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006E9: 0x00000000
+# [191680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006EA: 0x00000172
+# [191760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006EB: 0x00000000
+# [191840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006EC: 0x00000173
+# [191920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006ED: 0x00000000
+# [192000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006EE: 0x00000174
+# [192080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006EF: 0x00000000
+# [192160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006F0: 0x00000175
+# [192240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006F1: 0x00000000
+# [192320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006F2: 0x00000176
+# [192400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006F3: 0x00000000
+# [192480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006F4: 0x00000177
+# [192560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006F5: 0x00000000
+# [192640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006F6: 0x00000178
+# [192720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006F7: 0x00000000
+# [192800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006F8: 0x00000179
+# [192880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006F9: 0x00000000
+# [192960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006FA: 0x0000017A
+# [193040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006FB: 0x00000000
+# [193100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006FC: 0x0000017B
+# [193180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006FD: 0x00000000
+# [193260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006FE: 0x0000017C
+# [193340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000006FF: 0x00000000
+# [193420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000700: 0x0000017D
+# [193500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000701: 0x00000000
+# [193580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000702: 0x0000017E
+# [193660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000703: 0x00000000
+# [193740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000704: 0x0000017F
+# [193820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000705: 0x00000000
+# [193900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000706: 0x00000180
+# [193980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000707: 0x00000000
+# [194060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000708: 0x00000181
+# [194140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000709: 0x00000000
+# [194220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000070A: 0x00000182
+# [194300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000070B: 0x00000000
+# [194380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000070C: 0x00000183
+# [194460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000070D: 0x00000000
+# [194540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000070E: 0x00000184
+# [194620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000070F: 0x00000000
+# [194700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000710: 0x00000185
+# [194780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000711: 0x00000000
+# [194860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000712: 0x00000186
+# [194940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000713: 0x00000000
+# [195020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000714: 0x00000187
+# [195100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000715: 0x00000000
+# [195180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000716: 0x00000188
+# [195260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000717: 0x00000000
+# [195340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000718: 0x00000189
+# [195420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000719: 0x00000000
+# [195500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000071A: 0x0000018A
+# [195560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000071B: 0x00000000
+# [195640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000071C: 0x0000018B
+# [195720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000071D: 0x00000000
+# [195800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000071E: 0x0000018C
+# [195880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000071F: 0x00000000
+# [195960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000720: 0x0000018D
+# [196040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000721: 0x00000000
+# [196120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000722: 0x0000018E
+# [196200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000723: 0x00000000
+# [196280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000724: 0x0000018F
+# [196360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000725: 0x00000000
+# [196440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000726: 0x00000190
+# [196520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000727: 0x00000000
+# [196600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000728: 0x00000191
+# [196680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000729: 0x00000000
+# [196760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000072A: 0x00000192
+# [196840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000072B: 0x00000000
+# [196920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000072C: 0x00000193
+# [197000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000072D: 0x00000000
+# [197080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000072E: 0x00000194
+# [197160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000072F: 0x00000000
+# [197240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000730: 0x00000195
+# [197320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000731: 0x00000000
+# [197400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000732: 0x00000196
+# [197480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000733: 0x00000000
+# [197560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000734: 0x00000197
+# [197640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000735: 0x00000000
+# [197720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000736: 0x00000198
+# [197800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000737: 0x00000000
+# [197880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000738: 0x00000199
+# [197960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000739: 0x00000000
+# [198040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000073A: 0x0000019A
+# [198120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000073B: 0x00000000
+# [198200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000073C: 0x0000019B
+# [198280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000073D: 0x00000000
+# [198360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000073E: 0x0000019C
+# [198440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000073F: 0x00000000
+# [198520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000740: 0x0000019D
+# [198600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000741: 0x00000000
+# [198680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000742: 0x0000019E
+# [198760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000743: 0x00000000
+# [198840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000744: 0x0000019F
+# [198920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000745: 0x00000000
+# [199000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000746: 0x000001A0
+# [199080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000747: 0x00000000
+# [199160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000748: 0x000001A1
+# [199240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000749: 0x00000000
+# [199320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000074A: 0x000001A2
+# [199380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000074B: 0x00000000
+# [199440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000074C: 0x000001A3
+# [199520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000074D: 0x00000000
+# [199600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000074E: 0x000001A4
+# [199680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000074F: 0x00000000
+# [199760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000750: 0x000001A5
+# [199840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000751: 0x00000000
+# [199920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000752: 0x000001A6
+# [200000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000753: 0x00000000
+# [200080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000754: 0x000001A7
+# [200160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000755: 0x00000000
+# [200240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000756: 0x000001A8
+# [200320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000757: 0x00000000
+# [200400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000758: 0x000001A9
+# [200480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000759: 0x00000000
+# [200560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000075A: 0x000001AA
+# [200640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000075B: 0x00000000
+# [200720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000075C: 0x000001AB
+# [200800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000075D: 0x00000000
+# [200880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000075E: 0x000001AC
+# [200960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000075F: 0x00000000
+# [201040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000760: 0x000001AD
+# [201120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000761: 0x00000000
+# [201200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000762: 0x000001AE
+# [201280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000763: 0x00000000
+# [201360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000764: 0x000001AF
+# [201440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000765: 0x00000000
+# [201520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000766: 0x000001B0
+# [201600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000767: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 201627500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 201627500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [201680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000768: 0x000001B1
+# [201760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000769: 0x00000000
+# [201840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000076A: 0x000001B2
+# [201920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000076B: 0x00000000
+# [202000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000076C: 0x000001B3
+# [202080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000076D: 0x00000000
+# [202160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000076E: 0x000001B4
+# [202240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000076F: 0x00000000
+# [202320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000770: 0x000001B5
+# [202400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000771: 0x00000000
+# [202480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000772: 0x000001B6
+# [202560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000773: 0x00000000
+# [202640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000774: 0x000001B7
+# [202720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000775: 0x00000000
+# [202800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000776: 0x000001B8
+# [202880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000777: 0x00000000
+# [202960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000778: 0x000001B9
+# [203040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000779: 0x00000000
+# [203120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000077A: 0x000001BA
+# [203200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000077B: 0x00000000
+# [203280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000077C: 0x000001BB
+# [203360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000077D: 0x00000000
+# [203440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000077E: 0x000001BC
+# [203520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000077F: 0x00000000
+# [203600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000780: 0x000001BD
+# [203680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000781: 0x00000000
+# [203760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000782: 0x000001BE
+# [203840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000783: 0x00000000
+# [203920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000784: 0x000001BF
+# [204000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000785: 0x00000000
+# [204080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000786: 0x000001C0
+# [204160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000787: 0x00000000
+# [204240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000788: 0x000001C1
+# [204320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000789: 0x00000000
+# [204400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000078A: 0x000001C2
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 204467500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# [204480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000078B: 0x00000000
+# [204560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000078C: 0x000001C3
+# [204640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000078D: 0x00000000
+# [204720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000078E: 0x000001C4
+# [204800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000078F: 0x00000000
+# [204880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000790: 0x000001C5
+# [204960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000791: 0x00000000
+# [205040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000792: 0x000001C6
+# [205120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000793: 0x00000000
+# [205180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000794: 0x000001C7
+# [205260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000795: 0x00000000
+# [205340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000796: 0x000001C8
+# [205420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000797: 0x00000000
+# [205500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000798: 0x000001C9
+# [205580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x00000799: 0x00000000
+# [205660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000079A: 0x000001CA
+# [205740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000079B: 0x00000000
+# [205820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000079C: 0x000001CB
+# [205900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000079D: 0x00000000
+# [205980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000079E: 0x000001CC
+# [206060 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x0000079F: 0x00000000
+# [206140 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007A0: 0x000001CD
+# [206220 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007A1: 0x00000000
+# [206300 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007A2: 0x000001CE
+# [206380 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007A3: 0x00000000
+# [206460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007A4: 0x000001CF
+# [206540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007A5: 0x00000000
+# [206620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007A6: 0x000001D0
+# [206700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007A7: 0x00000000
+# [206780 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007A8: 0x000001D1
+# [206860 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007A9: 0x00000000
+# [206940 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007AA: 0x000001D2
+# [207020 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007AB: 0x00000000
+# [207100 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007AC: 0x000001D3
+# [207180 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007AD: 0x00000000
+# [207260 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007AE: 0x000001D4
+# [207340 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007AF: 0x00000000
+# [207420 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007B0: 0x000001D5
+# [207500 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007B1: 0x00000000
+# [207580 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007B2: 0x000001D6
+# [207660 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007B3: 0x00000000
+# [207740 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007B4: 0x000001D7
+# [207820 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007B5: 0x00000000
+# [207900 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007B6: 0x000001D8
+# [207980 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007B7: 0x00000000
+# [208040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007B8: 0x000001D9
+# [208120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007B9: 0x00000000
+# [208200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007BA: 0x000001DA
+# [208280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007BB: 0x00000000
+# [208360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007BC: 0x000001DB
+# [208440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007BD: 0x00000000
+# [208520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007BE: 0x000001DC
+# [208600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007BF: 0x00000000
+# [208680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007C0: 0x000001DD
+# [208760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007C1: 0x00000000
+# [208840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007C2: 0x000001DE
+# [208920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007C3: 0x00000000
+# [209000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007C4: 0x000001DF
+# [209080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007C5: 0x00000000
+# [209160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007C6: 0x000001E0
+# [209240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007C7: 0x00000000
+# [209320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007C8: 0x000001E1
+# [209400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007C9: 0x00000000
+# [209480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007CA: 0x000001E2
+# [209560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007CB: 0x00000000
+# [209640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007CC: 0x000001E3
+# [209720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007CD: 0x00000000
+# [209800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007CE: 0x000001E4
+# [209880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007CF: 0x00000000
+# [209960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007D0: 0x000001E5
+# [210040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007D1: 0x00000000
+# [210120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007D2: 0x000001E6
+# [210200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007D3: 0x00000000
+# [210280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007D4: 0x000001E7
+# [210360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007D5: 0x00000000
+# [210440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007D6: 0x000001E8
+# [210520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007D7: 0x00000000
+# [210600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007D8: 0x000001E9
+# [210680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007D9: 0x00000000
+# [210760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007DA: 0x000001EA
+# [210840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007DB: 0x00000000
+# [210920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007DC: 0x000001EB
+# [211000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007DD: 0x00000000
+# [211080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007DE: 0x000001EC
+# [211160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007DF: 0x00000000
+# [211240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007E0: 0x000001ED
+# [211320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007E1: 0x00000000
+# [211400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007E2: 0x000001EE
+# [211480 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007E3: 0x00000000
+# [211560 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007E4: 0x000001EF
+# [211640 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007E5: 0x00000000
+# [211720 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007E6: 0x000001F0
+# [211800 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007E7: 0x00000000
+# [211880 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007E8: 0x000001F1
+# [211960 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007E9: 0x00000000
+# [212040 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007EA: 0x000001F2
+# [212120 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007EB: 0x00000000
+# [212200 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007EC: 0x000001F3
+# [212280 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007ED: 0x00000000
+# [212360 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007EE: 0x000001F4
+# [212440 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007EF: 0x00000000
+# [212520 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007F0: 0x000001F5
+# [212600 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007F1: 0x00000000
+# [212680 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007F2: 0x000001F6
+# [212760 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007F3: 0x00000000
+# [212840 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007F4: 0x000001F7
+# [212920 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007F5: 0x00000000
+# [213000 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007F6: 0x000001F8
+# [213080 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007F7: 0x00000000
+# [213160 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007F8: 0x000001F9
+# [213240 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007F9: 0x00000000
+# [213320 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007FA: 0x000001FA
+# [213400 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007FB: 0x00000000
+# [213460 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007FC: 0x000001FB
+# [213540 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007FD: 0x00000000
+# [213620 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007FE: 0x000001FC
+# [213700 ns ] $UNB/Software/python/sim/UNB_0_FN_3_RAM_DIAG_DATA_BUFFER.ctrl: Reading from address 0x000007FF: 0x00000000
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 218452500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 218452500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 221287500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 235277500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 235277500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 238107500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 252102500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 252102500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 254927500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 268927500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 268927500 ps Iteration: 13 Instance: /tb_compaan_unb1_10g_app/u_lcu/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 271747500 ps Iteration: 12 Instance: /tb_compaan_unb1_10g_app/u_dut/u_dp_offload_tx/gen_dp_field_blk(0)/u_dp_field_blk/u_dp_repack_data/gen_dp_repack_out/u_dp_repack_out/no_bypass
+# Break key hit
+# Break in Architecture vital_pll at /home/software/Altera/11.1/quartus/eda/sim_lib/altera_mf.vhd line 11419