diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/lofar2_unb2b_ring.cl b/applications/lofar2/designs/lofar2_unb2b_ring/lofar2_unb2b_ring.cl
index e2d43ed01ac2c362d8bb8fc1273301f5b0e54756..b2f0baeee6bf008a08e10f6989b151cebfce7c16 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/lofar2_unb2b_ring.cl
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/lofar2_unb2b_ring.cl
@@ -37,7 +37,7 @@
#define LANE_DIRECTION 1
// Nof lanes = 1 - 8
#define NOF_LANES 8
-#define USE_DP_LAYER true
+#define USE_DP_LAYER
#define ETH_HEADER_SIZE 2
#define DP_HEADER_SIZE 3
#ifdef EMULATOR
@@ -45,7 +45,7 @@
#else
#define PAYLOAD_SIZE 750 // = 750*8 bytes = 6000 bytes
#endif
-#if USE_DP_LAYER
+#ifdef USE_DP_LAYER
#define BLOCK_LENGTH (PAYLOAD_SIZE+DP_HEADER_SIZE)
#else
#define BLOCK_LENGTH (PAYLOAD_SIZE+ETH_HEADER_SIZE)
@@ -532,7 +532,7 @@ __kernel void block_validate_decode()
for (int x = 0; x < NOF_ERR_COUNTS; x++)
reg.parameters.err_cnt[x] = 0;
-#if USE_DP_LAYER
+#ifdef USE_DP_LAYER
union dp_packet packets[2]; //one to read and one to write
#else
union eth_packet packets[2]; //one to read and one to write
@@ -561,6 +561,7 @@ __kernel void block_validate_decode()
else {
if (i != BLOCK_LENGTH-1)
reg.parameters.err_cnt[ERR_BI] += 1;
+#pragma unroll
for (int err = 0; err < NOF_ERR_COUNTS; err++){
if (err != ERR_BI)
reg.parameters.err_cnt[err] += ((input_10GbE.err & (1 << err)) >> err);
@@ -592,7 +593,7 @@ __kernel void block_validate_decode()
line_out.dp_channel = 0;
if (j == 0) {
line_out.flags |= FLAG_FIRST;
-#if USE_DP_LAYER
+#ifdef USE_DP_LAYER
line_out.dp_bsn = (packets[writeIndex].packet.dp_header.dp_sync_and_bsn & MASK_BSN); //62:0 = bsn
line_out.dp_channel = packets[writeIndex].packet.dp_header.dp_channel;
@@ -644,7 +645,7 @@ __kernel void rx_split()
}
}
-#if USE_DP_LAYER
+#ifdef USE_DP_LAYER
__attribute__((max_global_work_dim(0)))
#ifndef EMULATOR
__attribute__((autorun))
@@ -720,7 +721,7 @@ __kernel void no_validate_bsn_at_sync()
/* ----- End of ring_rx ----- */
/* ----- ring_tx ----- */
-#if USE_DP_LAYER
+#ifdef USE_DP_LAYER
__attribute__((max_global_work_dim(0)))
#ifndef EMULATOR
__attribute__((autorun))
@@ -776,7 +777,7 @@ __attribute__((autorun))
#endif
__kernel void no_validate_channel()
{
- uint no_param_arr[8] = [-1, -1, -1, -1, -1, -1, -1, -1];
+ uint no_param_arr[8] = [~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0];
while(1){
// handle MM read/write requests
handle_ro_mm_request(CH_VALIDATE_CHANNEL, no_param_arr);
@@ -826,7 +827,7 @@ __kernel void tx_encode()
ushort dp_channel = 0;
for (int j = 0; j < BLOCK_LENGTH; j++){
-#if USE_DP_LAYER
+#ifdef USE_DP_LAYER
if(j == 0 || (j > DP_HEADER_SIZE)){
#else
if(j == 0 || (j > ETH_HEADER_SIZE)){
@@ -836,36 +837,42 @@ __kernel void tx_encode()
output_10GbE.flags = 0;
output_10GbE.err = 0;
- if(j == 0){
-#if USE_DP_LAYER
- dp_channel = input_dp.dp_channel + 1; //Add 1 hop.
- if ((input_dp.flags & FLAG_SYNC)==FLAG_SYNC){
- dp_sync_and_bsn = (input_dp.dp_bsn | MASK_SYNC); // set bsn and sync
- }
- else{
- dp_sync_and_bsn = (input_dp.dp_bsn & MASK_BSN); // set bsn and clear sync (if set)
- }
-#endif
- output_10GbE.flags = FLAG_FIRST;
- output_10GbE.data = c_header_out[0];
- }
- else if (j == 1){
-#if USE_DP_LAYER
- output_10GbE.data = (c_header_out[1] | ((uint64_t) dp_channel));
+ switch(j)
+ {
+ case 0:
+#ifdef USE_DP_LAYER
+ dp_channel = input_dp.dp_channel + 1; //Add 1 hop.
+ if ((input_dp.flags & FLAG_SYNC)==FLAG_SYNC){
+ dp_sync_and_bsn = (input_dp.dp_bsn | MASK_SYNC); // set bsn and sync
+ }
+ else{
+ dp_sync_and_bsn = (input_dp.dp_bsn & MASK_BSN); // set bsn and clear sync (if set)
+ }
+#endif
+ output_10GbE.flags = FLAG_FIRST;
+ output_10GbE.data = c_header_out[0];
+ break;
+
+ case 1:
+#ifdef USE_DP_LAYER
+ output_10GbE.data = (c_header_out[1] | ((uint64_t) dp_channel));
#else
- output_10GbE.data = c_header_out[1];
+ output_10GbE.data = c_header_out[1];
#endif
- }
-#if USE_DP_LAYER
- else if (j == 2){
- output_10GbE.data = dp_sync_and_bsn;
- }
+ break;
+
+#ifdef USE_DP_LAYER
+ case 2:
+ output_10GbE.data = dp_sync_and_bsn;
+ break;
#endif
- else {
- output_10GbE.data = input_dp.data;
- }
- if (j == BLOCK_LENGTH-1){
- output_10GbE.flags = FLAG_LAST;
+
+ case (BLOCK_LENGTH-1):
+ output_10GbE.flags = FLAG_LAST;
+ // no break, we also want to execute the default case.
+
+ default:
+ output_10GbE.data = input_dp.data;
}
write_channel_intel(tx_sosi_channels[laneIndex], output_10GbE);
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index e8bc077f5559eb052dba6fdc6c9b793bd76eb2d2..33507f51bf32ace02a46dd204711306190958f92 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -94,10 +94,10 @@ ENTITY top IS
QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
-- ring transceivers
- RING_0_RX : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0) := (OTHERS => '0');
- RING_0_TX : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
- RING_1_RX : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0) := (OTHERS=>'0');
- RING_1_TX : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
@@ -115,7 +115,7 @@ ARCHITECTURE str OF top IS
-- RING
CONSTANT c_nof_ring_bus : NATURAL := 2;
- CONSTANT c_ring_bus_w : NATURAL := 4; --Using 4 phisically there are 12
+ CONSTANT c_ring_bus_w : NATURAL := 4; --Using 4 phisically, there are 12
CONSTANT c_nof_streams_ring : NATURAL := c_ring_bus_w*c_nof_ring_bus; --c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus; -- 8
-- 10GbE
@@ -125,6 +125,16 @@ ARCHITECTURE str OF top IS
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
+ -- OpenCL kernel channel widths as defined in the OpenCL kernel
+ CONSTANT c_kernel_10gbe_channel_w : NATURAL := 104;
+ CONSTANT c_kernel_bs_sosi_channel_w : NATURAL := 104;
+ CONSTANT c_kernel_lane_sosi_channel_w : NATURAL := 168;
+ CONSTANT c_kernel_mm_io_mosi_channel_w : NATURAL := 72;
+ CONSTANT c_kernel_mm_io_miso_channel_w : NATURAL := 32;
+
+ -- OpenCL kernel regmap address width as defined in qsys
+ CONSTANT c_kernel_regmap_addr_w : NATURAL := 8;
+
------------
-- Types
------------
@@ -305,10 +315,6 @@ ARCHITECTURE str OF top IS
SIGNAL ta2_unb2b_10GbE_tx_serial_r : STD_LOGIC_VECTOR(c_max_nof_mac -1 DOWNTO 0);
SIGNAL ta2_unb2b_10GbE_rx_serial_r : STD_LOGIC_VECTOR(c_max_nof_mac -1 DOWNTO 0);
- SIGNAL ta2_unb2b_10GbE_ring_ch_src_out_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL ta2_unb2b_10GbE_ring_ch_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL ta2_unb2b_10GbE_ring_ch_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL ta2_unb2b_10GbE_ring_ch_snk_in_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL ta2_unb2b_10GbE_ring_src_out_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL ta2_unb2b_10GbE_ring_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_ring_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
@@ -465,39 +471,35 @@ BEGIN
----------
-- 10GbE
----------
- -- Map [0,0; 0,1; 0,2; 0,3; 1,0; 1,1; 1,2; 1,3] -> [0,0; 1,0; 0,1; 1,1; 0,2; 1,2; 0,3; 1,3]
+ -- For the indexing of the lanes we would like to have all even indices (0, 2, 4, 6) to receive from the left (RING_RX_0) and transmit to the right (RING_TX_1).
+ -- For the odd indices it should be the other way around, from RING_RX_1 to RING_TX_0. Therefore we need to rewire those signals as follows:
+ -- For receiving, instead of the array [0,0; 0,1; 0,2; 0,3; 1,0; 1,1; 1,2; 1,3] we need the array [0,0; 1,0; 0,1; 1,1; 0,2; 1,2; 0,3; 1,3] where each element is (RING bus index, stream index of that bus).
+ -- Because all of all the RING busses are concatenated into one array we can do the following:
+ -- Rewire [0, 1, 2, 3, 4, 5, 6, 7] to [0, 4, 1, 5, 2, 6, 3, 7]. So now we have the even indices containing the interfaces from RING_0 (receive from the left)
+ -- and the odd indices containing RING_1 (receive from the right).
+ -- For transmitting we need to have the even indices containing RING_1 (transmit to the right) and the odd having RING_0 (transmit to the left)
gen_ring_lanes : FOR I IN 0 TO c_ring_bus_w -1 GENERATE
- ta2_unb2b_10GbE_ring_rx_serial_r(I*2) <= unb2b_board_ring_io_serial_rx_arr(I);
- ta2_unb2b_10GbE_ring_rx_serial_r(I*2 +1) <= unb2b_board_ring_io_serial_rx_arr(I+c_ring_bus_w);
- unb2b_board_ring_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2);
- unb2b_board_ring_io_serial_tx_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2 +1);
- END GENERATE;
-
- -- Map to kernel channel, swapping every two elements of the sink.
- ta2_unb2b_10GbE_ring_ch_src_out_arr <= ta2_unb2b_10GbE_ring_src_out_arr;
- ta2_unb2b_10GbE_ring_src_in_arr <= ta2_unb2b_10GbE_ring_ch_src_in_arr;
- gen_ring_ch : FOR I IN 0 TO c_nof_streams_ring/2 -1 GENERATE
- ta2_unb2b_10GbE_ring_snk_in_arr(2*I) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I+1);
- ta2_unb2b_10GbE_ring_snk_in_arr(2*I+1) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I);
- ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I+1) <= ta2_unb2b_10GbE_ring_snk_out_arr(2*I);
- ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I) <= ta2_unb2b_10GbE_ring_snk_out_arr(2*I+1);
+ ta2_unb2b_10GbE_ring_rx_serial_r(I*2) <= unb2b_board_ring_io_serial_rx_arr(I);
+ ta2_unb2b_10GbE_ring_rx_serial_r(I*2 +1) <= unb2b_board_ring_io_serial_rx_arr(I+c_ring_bus_w);
+ unb2b_board_ring_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2 +1);
+ unb2b_board_ring_io_serial_tx_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2);
END GENERATE;
-- Wire ring and qsfp to one array
- ta2_unb2b_10GbE_snk_in_arr(c_nof_streams_qsfp-1 DOWNTO 0) <= ta2_unb2b_10GbE_qsfp_snk_in_arr;
+ ta2_unb2b_10GbE_snk_in_arr(c_nof_streams_qsfp-1 DOWNTO 0) <= ta2_unb2b_10GbE_qsfp_snk_in_arr;
ta2_unb2b_10GbE_snk_in_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= ta2_unb2b_10GbE_ring_snk_in_arr;
- ta2_unb2b_10GbE_qsfp_snk_out_arr <= ta2_unb2b_10GbE_snk_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
- ta2_unb2b_10GbE_ring_snk_out_arr <= ta2_unb2b_10GbE_snk_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
+ ta2_unb2b_10GbE_qsfp_snk_out_arr <= ta2_unb2b_10GbE_snk_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
+ ta2_unb2b_10GbE_ring_snk_out_arr <= ta2_unb2b_10GbE_snk_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
- ta2_unb2b_10GbE_qsfp_src_out_arr <= ta2_unb2b_10GbE_src_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
- ta2_unb2b_10GbE_ring_src_out_arr <= ta2_unb2b_10GbE_src_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
- ta2_unb2b_10GbE_src_in_arr(c_nof_streams_qsfp-1 DOWNTO 0) <= ta2_unb2b_10GbE_qsfp_src_in_arr;
+ ta2_unb2b_10GbE_qsfp_src_out_arr <= ta2_unb2b_10GbE_src_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
+ ta2_unb2b_10GbE_ring_src_out_arr <= ta2_unb2b_10GbE_src_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
+ ta2_unb2b_10GbE_src_in_arr(c_nof_streams_qsfp-1 DOWNTO 0) <= ta2_unb2b_10GbE_qsfp_src_in_arr;
ta2_unb2b_10GbE_src_in_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= ta2_unb2b_10GbE_ring_src_in_arr;
- ta2_unb2b_10GbE_rx_serial_r(c_nof_streams_qsfp-1 DOWNTO 0) <= unb2b_board_front_io_serial_rx_arr;
- ta2_unb2b_10GbE_rx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <=ta2_unb2b_10GbE_ring_rx_serial_r;
- unb2b_board_front_io_serial_tx_arr <= ta2_unb2b_10GbE_tx_serial_r(c_nof_streams_qsfp-1 DOWNTO 0);
- ta2_unb2b_10GbE_ring_tx_serial_r <= ta2_unb2b_10GbE_tx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
+ ta2_unb2b_10GbE_rx_serial_r(c_nof_streams_qsfp-1 DOWNTO 0) <= unb2b_board_front_io_serial_rx_arr;
+ ta2_unb2b_10GbE_rx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= ta2_unb2b_10GbE_ring_rx_serial_r;
+ unb2b_board_front_io_serial_tx_arr <= ta2_unb2b_10GbE_tx_serial_r(c_nof_streams_qsfp-1 DOWNTO 0);
+ ta2_unb2b_10GbE_ring_tx_serial_r <= ta2_unb2b_10GbE_tx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
-- tr_10GbE
u_ta2_unb2b_10GbE : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
@@ -554,7 +556,7 @@ BEGIN
u_ta2_channel_cross_lanes : ENTITY ta2_channel_cross_lib.ta2_channel_cross
GENERIC MAP(
g_nof_streams => g_nof_lanes,
- g_nof_bytes => 8,
+ g_nof_bytes => c_longword_sz,
g_reverse_bytes => TRUE,
g_use_bsn => TRUE,
g_use_sync => TRUE,
@@ -584,7 +586,7 @@ BEGIN
u_ta2_channel_cross_bs_sosi : ENTITY ta2_channel_cross_lib.ta2_channel_cross
GENERIC MAP(
g_nof_streams => 1,
- g_nof_bytes => 4,
+ g_nof_bytes => c_word_sz,
g_reverse_bytes => TRUE,
g_use_bsn => TRUE,
g_use_sync => TRUE
@@ -606,7 +608,7 @@ BEGIN
u_ta2_channel_cross_rx_monitor : ENTITY ta2_channel_cross_lib.ta2_channel_cross
GENERIC MAP(
g_nof_streams => g_nof_lanes,
- g_nof_bytes => 8,
+ g_nof_bytes => c_longword_sz,
g_reverse_bytes => TRUE,
g_use_bsn => TRUE,
g_use_sync => TRUE,
@@ -632,7 +634,7 @@ BEGIN
u_ta2_channel_cross_tx_monitor : ENTITY ta2_channel_cross_lib.ta2_channel_cross
GENERIC MAP(
g_nof_streams => g_nof_lanes,
- g_nof_bytes => 8,
+ g_nof_bytes => c_longword_sz,
g_reverse_bytes => TRUE,
g_use_bsn => TRUE,
g_use_sync => TRUE,
@@ -660,7 +662,7 @@ BEGIN
dp_demux_tx_monitor_sosi_arr <= tx_monitor_sosi_arr;
FOR I IN 0 TO g_nof_lanes-1 LOOP
- dp_demux_rx_monitor_sosi_arr(I).channel <= nof_hops_to_source_rn(rx_monitor_sosi_arr(I).channel, this_rn_id, sdp_info.N_rn, ((I+1) MOD 2));
+ dp_demux_rx_monitor_sosi_arr(I).channel <= nof_hops_to_source_rn(rx_monitor_sosi_arr(I).channel, this_rn_id, sdp_info.N_rn, ((I+1) MOD 2)); -- Use (I+1) MOD 2 to get 1 if I is even and 0 if I is odd
dp_demux_tx_monitor_sosi_arr(I).channel <= nof_hops_to_source_rn(tx_monitor_sosi_arr(I).channel, this_rn_id, sdp_info.N_rn, ((I+1) MOD 2));
END LOOP;
END PROCESS;
@@ -941,219 +943,220 @@ BEGIN
board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
- board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(103 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).valid,
- board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(103 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).valid,
- board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(0).ready,
-
- board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(103 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).valid,
- board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(1).ready,
- board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(103 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).valid,
- board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(1).ready,
-
- board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(103 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).valid,
- board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(2).ready,
- board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(103 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).valid,
- board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(2).ready,
-
- board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(103 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).valid,
- board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(3).ready,
- board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(103 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).valid,
- board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(3).ready,
-
- board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(103 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).valid,
- board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(4).ready,
- board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(103 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).valid,
- board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(4).ready,
-
- board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(103 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).valid,
- board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(5).ready,
- board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(103 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).valid,
- board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(5).ready,
-
- board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(103 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).valid,
- board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(6).ready,
- board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(103 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).valid,
- board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(6).ready,
-
- board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(103 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).valid,
- board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(7).ready,
- board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(103 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).valid,
- board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(7).ready,
-
- board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(103 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_src_out_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_src_out_arr(0).valid,
+ board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_src_in_arr(0).ready,
+ board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_snk_in_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_snk_in_arr(0).valid,
+ board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_src_out_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_src_out_arr(1).valid,
+ board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_src_in_arr(1).ready,
+ board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_snk_in_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_snk_in_arr(1).valid,
+ board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_snk_out_arr(1).ready,
+
+ board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_src_out_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_src_out_arr(2).valid,
+ board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_src_in_arr(2).ready,
+ board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_snk_in_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_snk_in_arr(2).valid,
+ board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_snk_out_arr(2).ready,
+
+ board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_src_out_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_src_out_arr(3).valid,
+ board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_src_in_arr(3).ready,
+ board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_snk_in_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_snk_in_arr(3).valid,
+ board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_snk_out_arr(3).ready,
+
+ board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_src_out_arr(4).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_src_out_arr(4).valid,
+ board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_src_in_arr(4).ready,
+ board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_snk_in_arr(4).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_snk_in_arr(4).valid,
+ board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_snk_out_arr(4).ready,
+
+ board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_src_out_arr(5).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_src_out_arr(5).valid,
+ board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_src_in_arr(5).ready,
+ board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_snk_in_arr(5).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_snk_in_arr(5).valid,
+ board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_snk_out_arr(5).ready,
+
+ board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_src_out_arr(6).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_src_out_arr(6).valid,
+ board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_src_in_arr(6).ready,
+ board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_snk_in_arr(6).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_snk_in_arr(6).valid,
+ board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_snk_out_arr(6).ready,
+
+ board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_src_out_arr(7).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_src_out_arr(7).valid,
+ board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_src_in_arr(7).ready,
+ board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_snk_in_arr(7).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_snk_in_arr(7).valid,
+ board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_snk_out_arr(7).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid,
board_kernel_stream_src_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(103 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).valid,
board_kernel_stream_snk_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(0).ready,
- board_kernel_stream_src_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(103 DOWNTO 0),
+ board_kernel_stream_src_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(1).valid,
board_kernel_stream_src_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(1).ready,
- board_kernel_stream_snk_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(103 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).valid,
board_kernel_stream_snk_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(1).ready,
- board_kernel_stream_src_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(103 DOWNTO 0),
+ board_kernel_stream_src_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(2).valid,
board_kernel_stream_src_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(2).ready,
- board_kernel_stream_snk_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(103 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).valid,
board_kernel_stream_snk_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(2).ready,
- board_kernel_stream_src_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(103 DOWNTO 0),
+ board_kernel_stream_src_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(3).valid,
board_kernel_stream_src_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(3).ready,
- board_kernel_stream_snk_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(103 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).valid,
board_kernel_stream_snk_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(3).ready,
- board_kernel_stream_src_lane_0_data => kernel_to_lane_sosi_arr(0).data(167 DOWNTO 0),
+ board_kernel_stream_src_lane_0_data => kernel_to_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_src_lane_0_valid => kernel_to_lane_sosi_arr(0).valid,
board_kernel_stream_src_lane_0_ready => kernel_to_lane_siso_arr(0).ready,
- board_kernel_stream_snk_lane_0_data => kernel_from_lane_sosi_arr(0).data(167 DOWNTO 0),
+ board_kernel_stream_snk_lane_0_data => kernel_from_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_lane_0_valid => kernel_from_lane_sosi_arr(0).valid,
board_kernel_stream_snk_lane_0_ready => kernel_from_lane_siso_arr(0).ready,
- board_kernel_stream_src_lane_1_data => kernel_to_lane_sosi_arr(1).data(167 DOWNTO 0),
+ board_kernel_stream_src_lane_1_data => kernel_to_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_src_lane_1_valid => kernel_to_lane_sosi_arr(1).valid,
board_kernel_stream_src_lane_1_ready => kernel_to_lane_siso_arr(1).ready,
- board_kernel_stream_snk_lane_1_data => kernel_from_lane_sosi_arr(1).data(167 DOWNTO 0),
+ board_kernel_stream_snk_lane_1_data => kernel_from_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_lane_1_valid => kernel_from_lane_sosi_arr(1).valid,
board_kernel_stream_snk_lane_1_ready => kernel_from_lane_siso_arr(1).ready,
- board_kernel_stream_src_lane_2_data => kernel_to_lane_sosi_arr(2).data(167 DOWNTO 0),
+ board_kernel_stream_src_lane_2_data => kernel_to_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_src_lane_2_valid => kernel_to_lane_sosi_arr(2).valid,
board_kernel_stream_src_lane_2_ready => kernel_to_lane_siso_arr(2).ready,
- board_kernel_stream_snk_lane_2_data => kernel_from_lane_sosi_arr(2).data(167 DOWNTO 0),
+ board_kernel_stream_snk_lane_2_data => kernel_from_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_lane_2_valid => kernel_from_lane_sosi_arr(2).valid,
board_kernel_stream_snk_lane_2_ready => kernel_from_lane_siso_arr(2).ready,
- board_kernel_stream_src_lane_3_data => kernel_to_lane_sosi_arr(3).data(167 DOWNTO 0),
+ board_kernel_stream_src_lane_3_data => kernel_to_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_src_lane_3_valid => kernel_to_lane_sosi_arr(3).valid,
board_kernel_stream_src_lane_3_ready => kernel_to_lane_siso_arr(3).ready,
- board_kernel_stream_snk_lane_3_data => kernel_from_lane_sosi_arr(3).data(167 DOWNTO 0),
+ board_kernel_stream_snk_lane_3_data => kernel_from_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_lane_3_valid => kernel_from_lane_sosi_arr(3).valid,
board_kernel_stream_snk_lane_3_ready => kernel_from_lane_siso_arr(3).ready,
- board_kernel_stream_src_lane_4_data => kernel_to_lane_sosi_arr(4).data(167 DOWNTO 0),
+ board_kernel_stream_src_lane_4_data => kernel_to_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_src_lane_4_valid => kernel_to_lane_sosi_arr(4).valid,
board_kernel_stream_src_lane_4_ready => kernel_to_lane_siso_arr(4).ready,
- board_kernel_stream_snk_lane_4_data => kernel_from_lane_sosi_arr(4).data(167 DOWNTO 0),
+ board_kernel_stream_snk_lane_4_data => kernel_from_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_lane_4_valid => kernel_from_lane_sosi_arr(4).valid,
board_kernel_stream_snk_lane_4_ready => kernel_from_lane_siso_arr(4).ready,
- board_kernel_stream_src_lane_5_data => kernel_to_lane_sosi_arr(5).data(167 DOWNTO 0),
+ board_kernel_stream_src_lane_5_data => kernel_to_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_src_lane_5_valid => kernel_to_lane_sosi_arr(5).valid,
board_kernel_stream_src_lane_5_ready => kernel_to_lane_siso_arr(5).ready,
- board_kernel_stream_snk_lane_5_data => kernel_from_lane_sosi_arr(5).data(167 DOWNTO 0),
+ board_kernel_stream_snk_lane_5_data => kernel_from_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_lane_5_valid => kernel_from_lane_sosi_arr(5).valid,
board_kernel_stream_snk_lane_5_ready => kernel_from_lane_siso_arr(5).ready,
- board_kernel_stream_src_lane_6_data => kernel_to_lane_sosi_arr(6).data(167 DOWNTO 0),
+ board_kernel_stream_src_lane_6_data => kernel_to_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_src_lane_6_valid => kernel_to_lane_sosi_arr(6).valid,
board_kernel_stream_src_lane_6_ready => kernel_to_lane_siso_arr(6).ready,
- board_kernel_stream_snk_lane_6_data => kernel_from_lane_sosi_arr(6).data(167 DOWNTO 0),
+ board_kernel_stream_snk_lane_6_data => kernel_from_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_lane_6_valid => kernel_from_lane_sosi_arr(6).valid,
board_kernel_stream_snk_lane_6_ready => kernel_from_lane_siso_arr(6).ready,
- board_kernel_stream_src_lane_7_data => kernel_to_lane_sosi_arr(7).data(167 DOWNTO 0),
+ board_kernel_stream_src_lane_7_data => kernel_to_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_src_lane_7_valid => kernel_to_lane_sosi_arr(7).valid,
board_kernel_stream_src_lane_7_ready => kernel_to_lane_siso_arr(7).ready,
- board_kernel_stream_snk_lane_7_data => kernel_from_lane_sosi_arr(7).data(167 DOWNTO 0),
+ board_kernel_stream_snk_lane_7_data => kernel_from_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_lane_7_valid => kernel_from_lane_sosi_arr(7).valid,
board_kernel_stream_snk_lane_7_ready => kernel_from_lane_siso_arr(7).ready,
- board_kernel_stream_snk_rx_monitor_0_data => kernel_rx_monitor_sosi_arr(0).data(167 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_0_data => kernel_rx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_rx_monitor_0_valid => kernel_rx_monitor_sosi_arr(0).valid,
board_kernel_stream_snk_rx_monitor_0_ready => kernel_rx_monitor_siso_arr(0).ready,
- board_kernel_stream_snk_tx_monitor_0_data => kernel_tx_monitor_sosi_arr(0).data(167 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_0_data => kernel_tx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_tx_monitor_0_valid => kernel_tx_monitor_sosi_arr(0).valid,
board_kernel_stream_snk_tx_monitor_0_ready => kernel_tx_monitor_siso_arr(0).ready,
- board_kernel_stream_snk_rx_monitor_1_data => kernel_rx_monitor_sosi_arr(1).data(167 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_1_data => kernel_rx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_rx_monitor_1_valid => kernel_rx_monitor_sosi_arr(1).valid,
board_kernel_stream_snk_rx_monitor_1_ready => kernel_rx_monitor_siso_arr(1).ready,
- board_kernel_stream_snk_tx_monitor_1_data => kernel_tx_monitor_sosi_arr(1).data(167 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_1_data => kernel_tx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_tx_monitor_1_valid => kernel_tx_monitor_sosi_arr(1).valid,
board_kernel_stream_snk_tx_monitor_1_ready => kernel_tx_monitor_siso_arr(1).ready,
- board_kernel_stream_snk_rx_monitor_2_data => kernel_rx_monitor_sosi_arr(2).data(167 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_2_data => kernel_rx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_rx_monitor_2_valid => kernel_rx_monitor_sosi_arr(2).valid,
board_kernel_stream_snk_rx_monitor_2_ready => kernel_rx_monitor_siso_arr(2).ready,
- board_kernel_stream_snk_tx_monitor_2_data => kernel_tx_monitor_sosi_arr(2).data(167 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_2_data => kernel_tx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_tx_monitor_2_valid => kernel_tx_monitor_sosi_arr(2).valid,
board_kernel_stream_snk_tx_monitor_2_ready => kernel_tx_monitor_siso_arr(2).ready,
- board_kernel_stream_snk_rx_monitor_3_data => kernel_rx_monitor_sosi_arr(3).data(167 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_3_data => kernel_rx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_rx_monitor_3_valid => kernel_rx_monitor_sosi_arr(3).valid,
board_kernel_stream_snk_rx_monitor_3_ready => kernel_rx_monitor_siso_arr(3).ready,
- board_kernel_stream_snk_tx_monitor_3_data => kernel_tx_monitor_sosi_arr(3).data(167 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_3_data => kernel_tx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_tx_monitor_3_valid => kernel_tx_monitor_sosi_arr(3).valid,
board_kernel_stream_snk_tx_monitor_3_ready => kernel_tx_monitor_siso_arr(3).ready,
- board_kernel_stream_snk_rx_monitor_4_data => kernel_rx_monitor_sosi_arr(4).data(167 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_4_data => kernel_rx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_rx_monitor_4_valid => kernel_rx_monitor_sosi_arr(4).valid,
board_kernel_stream_snk_rx_monitor_4_ready => kernel_rx_monitor_siso_arr(4).ready,
- board_kernel_stream_snk_tx_monitor_4_data => kernel_tx_monitor_sosi_arr(4).data(167 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_4_data => kernel_tx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_tx_monitor_4_valid => kernel_tx_monitor_sosi_arr(4).valid,
board_kernel_stream_snk_tx_monitor_4_ready => kernel_tx_monitor_siso_arr(4).ready,
- board_kernel_stream_snk_rx_monitor_5_data => kernel_rx_monitor_sosi_arr(5).data(167 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_5_data => kernel_rx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_rx_monitor_5_valid => kernel_rx_monitor_sosi_arr(5).valid,
board_kernel_stream_snk_rx_monitor_5_ready => kernel_rx_monitor_siso_arr(5).ready,
- board_kernel_stream_snk_tx_monitor_5_data => kernel_tx_monitor_sosi_arr(5).data(167 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_5_data => kernel_tx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_tx_monitor_5_valid => kernel_tx_monitor_sosi_arr(5).valid,
board_kernel_stream_snk_tx_monitor_5_ready => kernel_tx_monitor_siso_arr(5).ready,
- board_kernel_stream_snk_rx_monitor_6_data => kernel_rx_monitor_sosi_arr(6).data(167 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_6_data => kernel_rx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_rx_monitor_6_valid => kernel_rx_monitor_sosi_arr(6).valid,
board_kernel_stream_snk_rx_monitor_6_ready => kernel_rx_monitor_siso_arr(6).ready,
- board_kernel_stream_snk_tx_monitor_6_data => kernel_tx_monitor_sosi_arr(6).data(167 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_6_data => kernel_tx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_tx_monitor_6_valid => kernel_tx_monitor_sosi_arr(6).valid,
board_kernel_stream_snk_tx_monitor_6_ready => kernel_tx_monitor_siso_arr(6).ready,
- board_kernel_stream_snk_rx_monitor_7_data => kernel_rx_monitor_sosi_arr(7).data(167 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_7_data => kernel_rx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_rx_monitor_7_valid => kernel_rx_monitor_sosi_arr(7).valid,
board_kernel_stream_snk_rx_monitor_7_ready => kernel_rx_monitor_siso_arr(7).ready,
- board_kernel_stream_snk_tx_monitor_7_data => kernel_tx_monitor_sosi_arr(7).data(167 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_7_data => kernel_tx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_tx_monitor_7_valid => kernel_tx_monitor_sosi_arr(7).valid,
board_kernel_stream_snk_tx_monitor_7_ready => kernel_tx_monitor_siso_arr(7).ready,
- board_kernel_stream_src_bs_data => kernel_bs_sosi.data(103 DOWNTO 0),
+ board_kernel_stream_src_bs_data => kernel_bs_sosi.data(c_kernel_bs_sosi_channel_w-1 DOWNTO 0),
board_kernel_stream_src_bs_valid => kernel_bs_sosi.valid,
board_kernel_stream_src_bs_ready => OPEN,
- board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(71 DOWNTO 0),
+ board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(c_kernel_mm_io_mosi_channel_w-1 DOWNTO 0),
board_kernel_stream_src_mm_io_valid => ta2_unb2b_mm_io_src_out.valid,
board_kernel_stream_src_mm_io_ready => ta2_unb2b_mm_io_src_in.ready,
- board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(31 DOWNTO 0),
+ board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(c_kernel_mm_io_miso_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_mm_io_valid => ta2_unb2b_mm_io_snk_in.valid,
board_kernel_stream_snk_mm_io_ready => ta2_unb2b_mm_io_snk_out.ready
);
- i_reset_n <= NOT mm_rst;
- i_kernel_rst <= NOT board_kernel_reset_reset_n;
+ i_reset_n <= NOT mm_rst; -- First reset OpenCL components in qsys (board)
+ i_kernel_rst <= NOT board_kernel_reset_reset_n; -- qsys output used to reset all OpenCL BSP components
- -- Kernel should start later than BSP
+ -- Kernel should start later than BSP. Delaying the reset from the qsys output to form the reset of the OpenCL kernel.
+ -- This way it is ensured the OpenCL kernel does not start reading/writing data before the components in the OpenCL BSP are ready.
u_common_areset : ENTITY common_lib.common_areset
GENERIC MAP (
g_rst_level => '0',
@@ -1471,7 +1474,7 @@ BEGIN
kernel_irq_irq => board_kernel_irq_irq,
- reg_ta2_unb2b_mm_io_address_export => reg_ta2_unb2b_mm_io_mosi.address(7 DOWNTO 0),
+ reg_ta2_unb2b_mm_io_address_export => reg_ta2_unb2b_mm_io_mosi.address(c_kernel_regmap_addr_w-1 DOWNTO 0),
reg_ta2_unb2b_mm_io_read_export => reg_ta2_unb2b_mm_io_mosi.rd,
reg_ta2_unb2b_mm_io_readdata_export => reg_ta2_unb2b_mm_io_miso.rddata(c_word_w-1 DOWNTO 0),
reg_ta2_unb2b_mm_io_write_export => reg_ta2_unb2b_mm_io_mosi.wr,
diff --git a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index 07f83a7a19f1d9949feb26d47b126c299bb1f9f9..4203f8ac92663d13f948d8b1bd6d93d3f309c0e5 100644
--- a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -55,7 +55,9 @@
-- | | | generics |
-- +-----------+---------+--------------------------------------------------------+
-- Remark:
--- . It may be nice to be able to configure a larger empty field to support g_nof_bytes > 32. Keep
+-- . This IP should be configured according to the corresponding IO channel in the OpenCL code.
+-- . It may be nice to be able to configure a larger empty field to support g_nof_bytes > 32
+-- but that would mean that the data structure in the OpenCL code must be adapted. Keep
-- in mind that IO channels must be a multiple of 8 bits (bytes).
LIBRARY IEEE, common_lib, dp_lib, technology_lib;
@@ -67,7 +69,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY ta2_channel_cross IS
GENERIC (
g_nof_streams : NATURAL;
- g_nof_bytes : POSITIVE; -- Max = 32
+ g_nof_bytes : POSITIVE; -- nof bytes in payload field, Max = 32
g_reverse_bytes : BOOLEAN := TRUE;
g_fifo_size : NATURAL := 8;
g_use_err : BOOLEAN := FALSE;
@@ -101,15 +103,20 @@ END ta2_channel_cross;
ARCHITECTURE str OF ta2_channel_cross IS
- CONSTANT c_data_w : NATURAL := c_byte_w * g_nof_bytes;
- CONSTANT c_empty_w : NATURAL := ceil_log2(g_nof_bytes);
- CONSTANT c_err_w : NATURAL := sel_a_b(g_use_err, g_err_w, 0);
- CONSTANT c_bsn_w : NATURAL := sel_a_b(g_use_err, g_err_w, 0);
- CONSTANT c_channel_w : NATURAL := sel_a_b(g_use_err, g_err_w, 0);
+ CONSTANT c_data_w : NATURAL := c_byte_w * g_nof_bytes;
+ CONSTANT c_empty_w : NATURAL := ceil_log2(g_nof_bytes);
+ CONSTANT c_err_w : NATURAL := sel_a_b(g_use_err, g_err_w, 0);
+ CONSTANT c_bsn_w : NATURAL := sel_a_b(g_use_bsn, g_bsn_w, 0);
+ CONSTANT c_channel_w : NATURAL := sel_a_b(g_use_channel, g_channel_w, 0);
- CONSTANT c_err_offset : NATURAL := (g_nof_bytes+1 * c_byte_w);
- CONSTANT c_bsn_offset : NATURAL := c_err_offset+c_err_w;
- CONSTANT c_channel_offset : NATURAL := c_bsn_offset+c_bsn_w;
+ CONSTANT c_err_offset : NATURAL := (g_nof_bytes+1 * c_byte_w);
+ CONSTANT c_bsn_offset : NATURAL := c_err_offset+c_err_w;
+ CONSTANT c_channel_offset : NATURAL := c_bsn_offset+c_bsn_w;
+
+ CONSTANT c_sop_offset : NATURAL := g_nof_bytes*c_byte_w;
+ CONSTANT c_eop_offset : NATURAL := g_nof_bytes*c_byte_w+1;
+ CONSTANT c_sync_offset : NATURAL := g_nof_bytes*c_byte_w+2;
+ CONSTANT c_empty_offset : NATURAL := c_byte_w*(g_nof_bytes+1);
SIGNAL dp_latency_adapter_tx_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_latency_adapter_tx_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
@@ -189,6 +196,16 @@ BEGIN
kernel_src_out_arr(stream).data(c_data_w-1 DOWNTO 0) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_data_w-1 DOWNTO 0);
END GENERATE;
+ -- Assign control signals to correct data fields.
+ kernel_src_out_arr(stream).data(c_sop_offset) <= dp_latency_adapter_tx_src_out_arr(stream).sop;
+ kernel_src_out_arr(stream).data(c_eop_offset) <= dp_latency_adapter_tx_src_out_arr(stream).eop;
+ kernel_src_out_arr(stream).data(c_sync_offset) <= dp_latency_adapter_tx_src_out_arr(stream).sync WHEN g_use_sync ELSE '0';
+ kernel_src_out_arr(stream).data(c_empty_offset-1 DOWNTO c_empty_offset-c_empty_w) <= dp_latency_adapter_tx_src_out_arr(stream).empty(c_empty_w-1 DOWNTO 0);
+ kernel_src_out_arr(stream).valid <= dp_latency_adapter_tx_src_out_arr(stream).valid;
+ dp_latency_adapter_tx_src_in_arr(stream).ready <= kernel_src_in_arr(stream).ready;
+ dp_latency_adapter_tx_src_in_arr(stream).xon <= '1';
+
+ -- Assign optional meta data signals to correct data fields.
gen_err_out : IF g_use_err GENERATE
kernel_src_out_arr(stream).data(c_err_offset+c_err_w-1 DOWNTO c_err_offset) <= dp_latency_adapter_tx_src_out_arr(stream).err(c_err_w-1 DOWNTO 0);
END GENERATE;
@@ -200,16 +217,6 @@ BEGIN
gen_channel_out : IF g_use_channel GENERATE
kernel_src_out_arr(stream).data(c_channel_offset+c_channel_w-1 DOWNTO c_channel_offset) <= dp_latency_adapter_tx_src_out_arr(stream).channel(c_channel_w-1 DOWNTO 0);
END GENERATE;
-
- -- Assign control signals to correct data fields.
- kernel_src_out_arr(stream).data(g_nof_bytes*c_byte_w+0) <= dp_latency_adapter_tx_src_out_arr(stream).sop;
- kernel_src_out_arr(stream).data(g_nof_bytes*c_byte_w+1) <= dp_latency_adapter_tx_src_out_arr(stream).eop;
- kernel_src_out_arr(stream).data(g_nof_bytes*c_byte_w+2) <= dp_latency_adapter_tx_src_out_arr(stream).sync WHEN g_use_sync ELSE '0';
- kernel_src_out_arr(stream).data(c_byte_w*(g_nof_bytes+1)-1 DOWNTO c_byte_w*(g_nof_bytes+1)-c_empty_w) <= dp_latency_adapter_tx_src_out_arr(stream).empty(c_empty_w-1 DOWNTO 0);
- kernel_src_out_arr(stream).valid <= dp_latency_adapter_tx_src_out_arr(stream).valid;
- dp_latency_adapter_tx_src_in_arr(stream).ready <= kernel_src_in_arr(stream).ready;
- dp_latency_adapter_tx_src_in_arr(stream).xon <= '1';
-
-- kernel_snk_in -> dp_src_out
----------------------------------------------------------------------------