diff --git a/libraries/dsp/st/src/vhdl/st_sst.vhd b/libraries/dsp/st/src/vhdl/st_sst.vhd
index b21195656a2cec221c3a4afdb74bf46efc740349..26b661ddbb2e1a6b69b2068333ee9a5586852c67 100644
--- a/libraries/dsp/st/src/vhdl/st_sst.vhd
+++ b/libraries/dsp/st/src/vhdl/st_sst.vhd
@@ -21,6 +21,7 @@
LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
+USE IEEE.math_real.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
@@ -43,6 +44,10 @@ USE technology_lib.technology_select_pkg.ALL;
-- of the previous sync interval. The length of the sync interval determines
-- the nof accumlations per statistic, hence the integration time. See st_calc
-- for more details.
+--
+-- View wrdata_power and stat_bin in Wave window to see the stat power
+-- values series.
+--
-- Remarks:
-- . The in_sync is assumed to be a pulse an interpreted directly.
-- . The MM register is single page RAM to save memory resources. Therefore
@@ -56,12 +61,13 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY st_sst IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
- g_nof_stat : NATURAL := 512; -- nof accumulators
+ g_nof_stat : NATURAL := 512; -- total nof accumulators
g_xst_enable : BOOLEAN := FALSE; -- when set to true, an extra memory is instantiated to hold the imaginary part of the cross-correlation results
g_in_data_w : NATURAL := 18; -- width o dth edata to be accumulated
g_stat_data_w : NATURAL := 54; -- statistics accumulator width
- g_stat_data_sz : NATURAL := 2 -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
- );
+ g_stat_data_sz : NATURAL := 2; -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ g_stat_multiplex: NATURAL := 2 -- number of accumulators per stat_bin, for debug purposes with view in Wave window
+ );
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
@@ -103,7 +109,7 @@ ARCHITECTURE str OF st_sst IS
CONSTANT c_field_arr : t_common_field_arr(0 DOWNTO 0) := (0=> ( field_name_pad("treshold"), "RW", c_nof_stat_w, field_default(0) ));
SIGNAL mm_fields_out : STD_LOGIC_VECTOR(field_slv_out_len(c_field_arr)-1 DOWNTO 0);
- SIGNAL treshold : STD_LOGIC_VECTOR(c_nof_stat_w-1 DOWNTO 0);
+ SIGNAL treshold : STD_LOGIC_VECTOR(c_nof_stat_w-1 DOWNTO 0);
TYPE reg_type IS RECORD
in_sosi_reg : t_dp_sosi;
@@ -113,14 +119,19 @@ ARCHITECTURE str OF st_sst IS
SIGNAL r, rin : reg_type;
SIGNAL in_sync : STD_LOGIC;
- SIGNAL stat_data_re : STD_LOGIC_VECTOR(g_stat_data_w-1 DOWNTO 0);
+
+ SIGNAL stat_data_re : STD_LOGIC_VECTOR(g_stat_data_w-1 DOWNTO 0);
SIGNAL stat_data_im : STD_LOGIC_VECTOR(g_stat_data_w-1 DOWNTO 0);
SIGNAL wrdata_re : STD_LOGIC_VECTOR(c_mem_data_w-1 DOWNTO 0);
SIGNAL wrdata_im : STD_LOGIC_VECTOR(c_mem_data_w-1 DOWNTO 0);
-
- SIGNAL stat_mosi : t_mem_mosi;
- SIGNAL count : STD_LOGIC_VECTOR(c_nof_stat_w-1 DOWNTO 0);
+ SIGNAL wrdata_power : REAL;
+
+ SIGNAL stat_bin : NATURAL;
+
+ SIGNAL stat_mosi : t_mem_mosi := c_mem_mosi_rst;
+
+ SIGNAL treshold_count : STD_LOGIC_VECTOR(c_nof_stat_w-1 DOWNTO 0);
SIGNAL ram_st_sst_mosi_arr : t_mem_mosi_arr(c_nof_complex-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL ram_st_sst_miso_arr : t_mem_miso_arr(c_nof_complex-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
@@ -153,24 +164,23 @@ BEGIN
------------------------------------------------------------------------------
-- Input registers and preparation of the input data for the multiplier.
------------------------------------------------------------------------------
- comb : PROCESS(r, dp_rst, in_complex, count, treshold)
+ comb : PROCESS(r, dp_rst, in_complex, treshold_count, treshold)
VARIABLE v : reg_type;
BEGIN
v := r;
v.in_sosi_reg := in_complex;
- IF(count = zeros OR treshold = zeros) THEN
+ IF treshold_count = zeros OR treshold = zeros THEN
v.in_a_re := in_complex.re(g_in_data_w-1 DOWNTO 0);
v.in_a_im := in_complex.im(g_in_data_w-1 DOWNTO 0);
END IF;
- IF(dp_rst = '1') THEN
+ IF dp_rst = '1' THEN
v.in_a_re := (OTHERS => '0');
v.in_a_im := (OTHERS => '0');
END IF;
- rin <= v;
-
+ rin <= v;
END PROCESS comb;
regs : PROCESS(dp_clk)
@@ -181,7 +191,7 @@ BEGIN
END PROCESS;
------------------------------------------------------------------------------
- -- Counter used to detect when treshold is reached in order to load new
+ -- Counter used to detect when treshold is reached in order to load new
-- input vlaues for the multiplier.
------------------------------------------------------------------------------
treshold_cnt : ENTITY common_lib.common_counter
@@ -197,13 +207,13 @@ BEGIN
clk => dp_clk,
cnt_clr => in_complex.eop,
cnt_en => in_complex.valid,
- cnt_max => treshold,
- count => count
+ cnt_max => treshold,
+ count => treshold_count
);
in_sync <= in_complex.sync;
- st_calc : ENTITY work.st_calc
+ st_calc : ENTITY work.st_calc
GENERIC MAP (
g_technology => g_technology,
g_nof_mux => 1,
@@ -228,10 +238,17 @@ BEGIN
out_val => stat_mosi.wr,
out_val_m => OPEN
);
-
- wrdata_re <= RESIZE_MEM_UDATA(stat_data_re);
- wrdata_im <= RESIZE_MEM_UDATA(stat_data_im);
-
+
+ -- Auto correlations are unsigned value, cross correlations are signed values
+ wrdata_re <= RESIZE_MEM_UDATA(stat_data_re) WHEN g_xst_enable=FALSE ELSE RESIZE_MEM_SDATA(stat_data_re);
+ wrdata_im <= RESIZE_MEM_UDATA(stat_data_im) WHEN g_xst_enable=FALSE ELSE RESIZE_MEM_SDATA(stat_data_im);
+
+ -- View SST or XST power values in wave window (stat_data_im = 0 for SST)
+ wrdata_power <= COMPLEX_RADIUS(TO_SREAL(stat_data_re), TO_SREAL(stat_data_im)) ** 2.0;
+
+ stat_bin <= TO_UINT(stat_mosi.address(c_stat_ram.adr_w-1 DOWNTO 0)) / g_stat_multiplex;
+
+ -- For SST or for real part of XST
stat_reg_re : ENTITY common_lib.common_ram_crw_crw_ratio
GENERIC MAP (
g_technology => g_technology,
@@ -261,12 +278,12 @@ BEGIN
rd_val_b => OPEN
);
- gen_re: IF g_xst_enable=FALSE GENERATE
+ gen_sst: IF g_xst_enable=FALSE GENERATE
ram_st_sst_mosi_arr(0) <= ram_st_sst_mosi;
ram_st_sst_miso <= ram_st_sst_miso_arr(0);
END GENERATE;
- gen_im: IF g_xst_enable=TRUE GENERATE
+ gen_xst: IF g_xst_enable=TRUE GENERATE
---------------------------------------------------------------
-- COMBINE MEMORY MAPPED INTERFACES
---------------------------------------------------------------
@@ -284,6 +301,7 @@ BEGIN
miso_arr => ram_st_sst_miso_arr
);
+ -- For imaginary part of XST
stat_reg_im : ENTITY common_lib.common_ram_crw_crw_ratio
GENERIC MAP (
g_technology => g_technology,
@@ -311,8 +329,7 @@ BEGIN
rd_en_b => '0',
rd_dat_b => OPEN,
rd_val_b => OPEN
- );
-
+ );
END GENERATE;
-END str;
\ No newline at end of file
+END str;