From 81cffcb7420cd003808cc2459053e14ff31fdc07 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Wed, 9 Oct 2019 09:38:52 +0200
Subject: [PATCH] changes in config files
---
.../unb1_ddr3_reorder_dual_rank/hdllib.cfg | 2 +-
.../unb1_ddr3_reorder_single_rank/hdllib.cfg | 2 +-
.../designs/unb1_ddr3_transpose/hdllib.cfg | 2 +-
boards/uniboard1/designs/unb1_test/doc/README | 2 +-
.../revisions/unb1_test_all/hdllib.cfg | 4 +-
.../revisions/unb1_test_ddr/hdllib.cfg | 4 +-
.../unb1_test_ddr_16g_MB_I/hdllib.cfg | 2 +-
.../unb1_test_ddr_16g_MB_II/hdllib.cfg | 2 +-
.../unb1_test_ddr_16g_MB_I_II/hdllib.cfg | 2 +-
.../revisions/unb1_test_ddr_MB_I/hdllib.cfg | 2 +-
.../revisions/unb1_test_ddr_MB_II/hdllib.cfg | 2 +-
.../unb1_test_ddr_MB_I_II/hdllib.cfg | 2 +-
libraries/io/ddr3/hdllib.cfg | 6 +-
libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd | 4 +-
libraries/technology/10gbase_r/hdllib.cfg | 22 +--
.../10gbase_r/tech_10gbase_r_arria10_e1sg.vhd | 24 +--
libraries/technology/clkbuf/hdllib.cfg | 2 +-
libraries/technology/clkbuf/tech_clkbuf.vhd | 2 +-
libraries/technology/ddr/hdllib.cfg | 8 +-
.../technology/ddr/tech_ddr_arria10_e1sg.vhd | 8 +-
.../technology/ddr/tech_ddr_component_pkg.vhd | 22 +--
.../ddr/tech_ddr_mem_model_component_pkg.vhd | 2 +-
libraries/technology/flash/hdllib.cfg | 4 +-
.../flash/tech_flash_asmi_parallel.vhd | 2 +-
.../flash/tech_flash_remote_update.vhd | 2 +-
.../technology/fpga_temp_sens/hdllib.cfg | 2 +-
.../fpga_temp_sens/tech_fpga_temp_sens.vhd | 2 +-
.../technology/fpga_voltage_sens/hdllib.cfg | 2 +-
.../tech_fpga_voltage_sens.vhd | 2 +-
.../technology/fractional_pll/hdllib.cfg | 4 +-
.../tech_fractional_pll_clk125.vhd | 2 +-
.../tech_fractional_pll_clk200.vhd | 2 +-
.../ip_arria10/clkbuf_global/compile_ip.tcl | 2 +-
.../ip_arria10/clkbuf_global/hdllib.cfg | 2 +-
.../ip_arria10/complex_mult/README.txt | 2 +-
.../ip_arria10/complex_mult/compile_ip.tcl | 2 +-
.../ip_arria10/complex_mult/hdllib.cfg | 2 +-
.../technology/ip_arria10/ddio/compile_ip.tcl | 2 +-
.../technology/ip_arria10/ddio/hdllib.cfg | 4 +-
.../ip_arria10/ddr4_4g_1600/compile_ip.tcl | 2 +-
.../ddr4_4g_1600/copy_hex_files.tcl | 2 +-
.../ip_arria10/ddr4_4g_1600/hdllib.cfg | 2 +-
.../ip_arria10/ddr4_4g_2000/compile_ip.tcl | 2 +-
.../ddr4_4g_2000/copy_hex_files.tcl | 2 +-
.../ip_arria10/ddr4_4g_2000/hdllib.cfg | 2 +-
.../ip_arria10/ddr4_8g_2400/compile_ip.tcl | 2 +-
.../ddr4_8g_2400/copy_hex_files.tcl | 2 +-
.../ip_arria10/ddr4_8g_2400/hdllib.cfg | 2 +-
.../technology/ip_arria10/fifo/README.txt | 2 +-
.../technology/ip_arria10/fifo/generate_ip.sh | 2 +-
.../flash/asmi_parallel/compile_ip.tcl | 2 +-
.../ip_arria10/flash/asmi_parallel/hdllib.cfg | 2 +-
.../flash/remote_update/compile_ip.tcl | 2 +-
.../ip_arria10/flash/remote_update/hdllib.cfg | 2 +-
.../fractional_pll_clk125/compile_ip.tcl | 2 +-
.../fractional_pll_clk125/hdllib.cfg | 2 +-
.../fractional_pll_clk200/compile_ip.tcl | 2 +-
.../fractional_pll_clk200/hdllib.cfg | 2 +-
.../technology/ip_arria10/mac_10g/README.txt | 2 +-
.../ip_arria10/mac_10g/compile_ip.tcl | 4 +-
.../technology/ip_arria10/mac_10g/hdllib.cfg | 4 +-
.../ip_arria10/phy_10gbase_r/README.txt | 2 +-
.../ip_arria10/phy_10gbase_r/compile_ip.tcl | 2 +-
.../ip_arria10/phy_10gbase_r/hdllib.cfg | 2 +-
.../phy_10gbase_r_12/compile_ip.tcl | 2 +-
.../ip_arria10/phy_10gbase_r_12/hdllib.cfg | 2 +-
.../phy_10gbase_r_24/compile_ip.tcl | 2 +-
.../ip_arria10/phy_10gbase_r_24/hdllib.cfg | 2 +-
.../ip_arria10/phy_10gbase_r_4/compile_ip.tcl | 2 +-
.../ip_arria10/phy_10gbase_r_4/hdllib.cfg | 2 +-
.../phy_10gbase_r_48/compile_ip.tcl | 2 +-
.../ip_arria10/phy_10gbase_r_48/hdllib.cfg | 2 +-
.../ip_arria10/pll_clk125/compile_ip.tcl | 2 +-
.../ip_arria10/pll_clk125/hdllib.cfg | 2 +-
.../ip_arria10/pll_clk200/compile_ip.tcl | 2 +-
.../ip_arria10/pll_clk200/hdllib.cfg | 2 +-
.../ip_arria10/pll_clk25/compile_ip.tcl | 2 +-
.../ip_arria10/pll_clk25/hdllib.cfg | 2 +-
.../pll_xgmii_mac_clocks/compile_ip.tcl | 2 +-
.../pll_xgmii_mac_clocks/hdllib.cfg | 2 +-
.../technology/ip_arria10/ram/README.txt | 2 +-
.../technology/ip_arria10/ram/generate_ip.sh | 2 +-
.../ip_arria10/ram/ip_arria10_ram_cr_cw.vhd | 2 +-
.../ip_arria10/ram/ip_arria10_ram_crw_crw.vhd | 2 +-
.../ram/ip_arria10_ram_crwk_crw.vhd | 2 +-
.../ip_arria10/ram/ip_arria10_ram_r_w.vhd | 2 +-
.../ip_arria10/temp_sense/compile_ip.tcl | 2 +-
.../ip_arria10/temp_sense/hdllib.cfg | 2 +-
.../transceiver_pll_10g/compile_ip.tcl | 2 +-
.../ip_arria10/transceiver_pll_10g/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../transceiver_reset_controller_1/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../transceiver_reset_controller_4/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../ip_arria10/tse_sgmii_gx/compile_ip.tcl | 2 +-
.../ip_arria10/tse_sgmii_gx/hdllib.cfg | 2 +-
.../ip_arria10/tse_sgmii_lvds/compile_ip.tcl | 2 +-
.../ip_arria10/tse_sgmii_lvds/hdllib.cfg | 2 +-
.../ip_arria10/voltage_sense/compile_ip.tcl | 2 +-
.../ip_arria10/voltage_sense/hdllib.cfg | 2 +-
.../alt_em10g32_170/compile_ip.tcl | 149 ----------------
.../alt_em10g32_170/hdllib.cfg | 20 ---
.../alt_mem_if_jtag_master_170/compile_ip.tcl | 38 ----
.../alt_mem_if_jtag_master_170/hdllib.cfg | 17 --
.../altclkctrl_170/compile_ip.tcl | 35 ----
.../altclkctrl_170/hdllib.cfg | 17 --
.../altera_asmi_parallel_170/compile_ip.tcl | 37 ----
.../altera_asmi_parallel_170/hdllib.cfg | 15 --
.../compile_ip.tcl | 35 ----
.../altera_avalon_mm_bridge_170/hdllib.cfg | 20 ---
.../compile_ip.tcl | 46 -----
.../hdllib.cfg | 16 --
.../compile_ip.tcl | 37 ----
.../hdllib.cfg | 16 --
.../altera_avalon_sc_fifo_170/compile_ip.tcl | 40 -----
.../altera_avalon_sc_fifo_170/hdllib.cfg | 16 --
.../compile_ip.tcl | 37 ----
.../hdllib.cfg | 16 --
.../compile_ip.tcl | 39 -----
.../hdllib.cfg | 16 --
.../altera_emif_170/compile_ip.tcl | 162 ------------------
.../altera_emif_170/hdllib.cfg | 16 --
.../altera_emif_arch_nf_170/compile_ip.tcl | 98 -----------
.../altera_emif_arch_nf_170/hdllib.cfg | 20 ---
.../compile_ip.tcl | 47 -----
.../altera_emif_cal_slave_nf_170/hdllib.cfg | 16 --
.../altera_eth_tse_170/compile_ip.tcl | 40 -----
.../altera_eth_tse_170/hdllib.cfg | 27 ---
.../compile_ip.tcl | 33 ----
.../hdllib.cfg | 17 --
.../altera_eth_tse_mac_170/compile_ip.tcl | 148 ----------------
.../altera_eth_tse_mac_170/hdllib.cfg | 16 --
.../compile_ip.tcl | 40 -----
.../hdllib.cfg | 17 --
.../compile_ip.tcl | 35 ----
.../hdllib.cfg | 17 --
.../compile_ip.tcl | 114 ------------
.../hdllib.cfg | 17 --
.../compile_ip.tcl | 116 -------------
.../hdllib.cfg | 17 --
.../altera_iopll_170/compile_ip.tcl | 41 -----
.../altera_iopll_170/hdllib.cfg | 17 --
.../altera_ip_col_if_170/compile_ip.tcl | 37 ----
.../altera_ip_col_if_170/hdllib.cfg | 16 --
.../compile_ip.tcl | 45 -----
.../altera_jtag_dc_streaming_170/hdllib.cfg | 16 --
.../altera_lvds_170/compile_ip.tcl | 34 ----
.../altera_lvds_170/hdllib.cfg | 17 --
.../altera_lvds_core20_170/compile_ip.tcl | 39 -----
.../altera_lvds_core20_170/hdllib.cfg | 17 --
.../compile_ip.tcl | 36 ----
.../hdllib.cfg | 16 --
.../compile_ip.tcl | 36 ----
.../hdllib.cfg | 16 --
.../altera_mm_interconnect_170/compile_ip.tcl | 46 -----
.../altera_mm_interconnect_170/hdllib.cfg | 16 --
.../altera_remote_update_170/compile_ip.tcl | 37 ----
.../altera_remote_update_170/hdllib.cfg | 15 --
.../compile_ip.tcl | 40 -----
.../altera_remote_update_core_170/hdllib.cfg | 12 --
.../compile_ip.tcl | 37 ----
.../altera_reset_controller_170/hdllib.cfg | 16 --
.../compile_ip.tcl | 55 ------
.../altera_xcvr_atx_pll_a10_170/hdllib.cfg | 17 --
.../altera_xcvr_fpll_a10_170/compile_ip.tcl | 50 ------
.../altera_xcvr_fpll_a10_170/hdllib.cfg | 17 --
.../altera_xcvr_native_a10_170/compile_ip.tcl | 98 -----------
.../altera_xcvr_native_a10_170/hdllib.cfg | 16 --
.../compile_ip.tcl | 44 -----
.../altera_xcvr_reset_control_170/hdllib.cfg | 16 --
.../channel_adapter_170/compile_ip.tcl | 40 -----
.../channel_adapter_170/hdllib.cfg | 16 --
.../timing_adapter_170/compile_ip.tcl | 39 -----
.../timing_adapter_170/hdllib.cfg | 16 --
.../clkbuf_global/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/clkbuf_global/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_clkbuf_global.qsys | 2 +-
.../ip_arria10_e1sg/complex_mult/README.txt | 2 +-
.../complex_mult/compile_ip.tcl | 11 +-
.../complex_mult/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/complex_mult/hdllib.cfg | 4 +-
.../ip_arria10_e1sg_complex_mult.qsys | 2 +-
.../ip_arria10_e1sg/ddio/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/ddio/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/ddio/hdllib.cfg | 4 +-
.../ddio/ip_arria10_e1sg_ddio_in_1.qsys | 2 +-
.../ddio/ip_arria10_e1sg_ddio_out_1.qsys | 2 +-
.../ddr4_4g_1600/compile_ip.tcl | 2 +-
.../ddr4_4g_1600/copy_hex_files.tcl | 10 +-
.../ddr4_4g_1600/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_ddr4_4g_1600.qsys | 2 +-
.../ddr4_4g_2000/compile_ip.tcl | 2 +-
.../ddr4_4g_2000/copy_hex_files.tcl | 2 +-
.../ddr4_4g_2000/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_ddr4_4g_2000.qsys | 2 +-
.../ddr4_8g_1600/compile_ip.tcl | 2 +-
.../ddr4_8g_1600/copy_hex_files.tcl | 2 +-
.../ddr4_8g_1600/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_ddr4_8g_1600.qsys | 2 +-
.../ddr4_8g_2400/compile_ip.tcl | 2 +-
.../ddr4_8g_2400/copy_hex_files.tcl | 2 +-
.../ddr4_8g_2400/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_ddr4_8g_2400.qsys | 2 +-
.../ip_arria10_e1sg/fifo/README.txt | 2 +-
.../ip_arria10_e1sg/fifo/generate_ip.sh | 4 +-
.../fifo/ip_arria10_e1sg_fifo_dc.qsys | 2 +-
.../ip_arria10_e1sg_fifo_dc_mixed_widths.qsys | 2 +-
.../fifo/ip_arria10_e1sg_fifo_sc.qsys | 2 +-
.../flash/asmi_parallel/compile_ip.tcl | 2 +-
.../flash/asmi_parallel/generate_ip.sh | 2 +-
.../flash/asmi_parallel/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_asmi_parallel.qsys | 2 +-
.../flash/remote_update/compile_ip.tcl | 2 +-
.../flash/remote_update/generate_ip.sh | 2 +-
.../flash/remote_update/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_remote_update.qsys | 2 +-
.../fractional_pll_clk125/compile_ip.tcl | 2 +-
.../fractional_pll_clk125/generate_ip.sh | 2 +-
.../fractional_pll_clk125/hdllib.cfg | 6 +-
...ip_arria10_e1sg_fractional_pll_clk125.qsys | 2 +-
.../fractional_pll_clk200/compile_ip.tcl | 2 +-
.../fractional_pll_clk200/generate_ip.sh | 2 +-
.../fractional_pll_clk200/hdllib.cfg | 6 +-
...ip_arria10_e1sg_fractional_pll_clk200.qsys | 2 +-
.../ip_arria10_e1sg/mac_10g/README.txt | 2 +-
.../ip_arria10_e1sg/mac_10g/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/mac_10g/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/mac_10g/hdllib.cfg | 8 +-
.../mac_10g/ip_arria10_e1sg_mac_10g.qsys | 2 +-
.../ip_arria10_e1sg/mult_add4/compile_ip.tcl | 6 +-
.../ip_arria10_e1sg/mult_add4/generate_ip.sh | 2 +-
.../mult_add4/ip_arria10_e1sg_mult_add4.qsys | 2 +-
.../phy_10gbase_r/compile_ip.tcl | 2 +-
.../phy_10gbase_r/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_phy_10gbase_r.qsys | 2 +-
.../phy_10gbase_r_12/compile_ip.tcl | 2 +-
.../phy_10gbase_r_12/generate_ip.sh | 2 +-
.../phy_10gbase_r_12/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_phy_10gbase_r_12.qsys | 2 +-
.../phy_10gbase_r_24/compile_ip.tcl | 2 +-
.../phy_10gbase_r_24/generate_ip.sh | 2 +-
.../phy_10gbase_r_24/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_phy_10gbase_r_24.qsys | 2 +-
.../phy_10gbase_r_3/compile_ip.tcl | 2 +-
.../phy_10gbase_r_3/generate_ip.sh | 2 +-
.../phy_10gbase_r_3/hdllib.cfg | 11 +-
.../ip_arria10_e1sg_phy_10gbase_r_3.qsys | 2 +-
.../phy_10gbase_r_4/compile_ip.tcl | 2 +-
.../phy_10gbase_r_4/generate_ip.sh | 2 +-
.../phy_10gbase_r_4/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_phy_10gbase_r_4.qsys | 2 +-
.../phy_10gbase_r_48/compile_ip.tcl | 2 +-
.../phy_10gbase_r_48/generate_ip.sh | 2 +-
.../phy_10gbase_r_48/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_phy_10gbase_r_48.qsys | 2 +-
.../ip_arria10_e1sg/pll_clk125/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/pll_clk125/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/pll_clk125/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_pll_clk125.qsys | 2 +-
.../ip_arria10_e1sg/pll_clk200/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/pll_clk200/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/pll_clk200/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_pll_clk200.qsys | 2 +-
.../ip_arria10_e1sg/pll_clk25/compile_ip.tcl | 2 +-
.../ip_arria10_e1sg/pll_clk25/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/pll_clk25/hdllib.cfg | 6 +-
.../pll_clk25/ip_arria10_e1sg_pll_clk25.qsys | 2 +-
.../pll_xgmii_mac_clocks/compile_ip.tcl | 2 +-
.../pll_xgmii_mac_clocks/generate_ip.sh | 2 +-
.../pll_xgmii_mac_clocks/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys | 2 +-
.../technology/ip_arria10_e1sg/ram/README.txt | 2 +-
.../ip_arria10_e1sg/ram/generate_ip.sh | 4 +-
.../technology/ip_arria10_e1sg/ram/hdllib.cfg | 8 -
.../ram/ip_arria10_e1sg_ram_cr_cw.qsys | 2 +-
.../ram/ip_arria10_e1sg_ram_cr_cw.vhd | 2 +-
.../ram/ip_arria10_e1sg_ram_crw_crw.qsys | 2 +-
.../ram/ip_arria10_e1sg_ram_crw_crw.vhd | 2 +-
.../ram/ip_arria10_e1sg_ram_crwk_crw.qsys | 2 +-
.../ram/ip_arria10_e1sg_ram_crwk_crw.vhd | 2 +-
.../ram/ip_arria10_e1sg_ram_r_w.qsys | 2 +-
.../ram/ip_arria10_e1sg_ram_r_w.vhd | 2 +-
.../ip_arria10_e1sg/temp_sense/compile_ip.tcl | 6 +-
.../ip_arria10_e1sg/temp_sense/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/temp_sense/hdllib.cfg | 9 +-
.../ip_arria10_e1sg_temp_sense.qsys | 2 +-
.../transceiver_pll_10g/compile_ip.tcl | 2 +-
.../transceiver_pll_10g/generate_ip.sh | 2 +-
.../transceiver_pll_10g/hdllib.cfg | 11 +-
.../ip_arria10_e1sg_transceiver_pll_10g.qsys | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../transceiver_reset_controller_1/hdllib.cfg | 6 +-
...0_e1sg_transceiver_reset_controller_1.qsys | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 6 +-
..._e1sg_transceiver_reset_controller_12.qsys | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 6 +-
..._e1sg_transceiver_reset_controller_24.qsys | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../transceiver_reset_controller_3/hdllib.cfg | 6 +-
...0_e1sg_transceiver_reset_controller_3.qsys | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../transceiver_reset_controller_4/hdllib.cfg | 6 +-
...0_e1sg_transceiver_reset_controller_4.qsys | 2 +-
.../compile_ip.tcl | 2 +-
.../generate_ip.sh | 2 +-
.../hdllib.cfg | 6 +-
..._e1sg_transceiver_reset_controller_48.qsys | 2 +-
.../tse_sgmii_gx/compile_ip.tcl | 2 +-
.../tse_sgmii_gx/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_tse_sgmii_gx.qsys | 2 +-
.../tse_sgmii_lvds/compile_ip.tcl | 2 +-
.../tse_sgmii_lvds/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg | 6 +-
.../ip_arria10_e1sg_tse_sgmii_lvds.qsys | 2 +-
.../voltage_sense/compile_ip.tcl | 22 +--
.../voltage_sense/generate_ip.sh | 2 +-
.../ip_arria10_e1sg/voltage_sense/hdllib.cfg | 4 +-
.../ip_arria10_e1sg_voltage_sense.qsys | 2 +-
.../clkbuf_global/compile_ip.tcl | 2 +-
.../clkbuf_global/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/complex_mult/README.txt | 2 +-
.../complex_mult/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/complex_mult/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/ddio/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/ddio/hdllib.cfg | 4 +-
.../ddr4_4g_1600/compile_ip.tcl | 2 +-
.../ddr4_4g_1600/copy_hex_files.tcl | 2 +-
.../ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg | 2 +-
.../ddr4_4g_2000/compile_ip.tcl | 2 +-
.../ddr4_4g_2000/copy_hex_files.tcl | 2 +-
.../ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg | 2 +-
.../ddr4_8g_1600/compile_ip.tcl | 2 +-
.../ddr4_8g_1600/copy_hex_files.tcl | 2 +-
.../ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg | 2 +-
.../ddr4_8g_2400/compile_ip.tcl | 2 +-
.../ddr4_8g_2400/copy_hex_files.tcl | 2 +-
.../ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/fifo/README.txt | 2 +-
.../ip_arria10_e3sge3/fifo/generate_ip.sh | 2 +-
.../flash/asmi_parallel/compile_ip.tcl | 2 +-
.../flash/asmi_parallel/hdllib.cfg | 2 +-
.../flash/remote_update/compile_ip.tcl | 2 +-
.../flash/remote_update/hdllib.cfg | 2 +-
.../fractional_pll_clk125/compile_ip.tcl | 2 +-
.../fractional_pll_clk125/hdllib.cfg | 2 +-
.../fractional_pll_clk200/compile_ip.tcl | 2 +-
.../fractional_pll_clk200/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/mac_10g/README.txt | 2 +-
.../ip_arria10_e3sge3/mac_10g/compile_ip.tcl | 4 +-
.../ip_arria10_e3sge3/mac_10g/hdllib.cfg | 4 +-
.../mult_add4/compile_ip.tcl | 2 +-
.../phy_10gbase_r/compile_ip.tcl | 2 +-
.../phy_10gbase_r/hdllib.cfg | 2 +-
.../phy_10gbase_r_12/compile_ip.tcl | 2 +-
.../phy_10gbase_r_12/hdllib.cfg | 2 +-
.../phy_10gbase_r_24/compile_ip.tcl | 2 +-
.../phy_10gbase_r_24/hdllib.cfg | 2 +-
.../phy_10gbase_r_4/compile_ip.tcl | 2 +-
.../phy_10gbase_r_4/hdllib.cfg | 2 +-
.../phy_10gbase_r_48/compile_ip.tcl | 2 +-
.../phy_10gbase_r_48/hdllib.cfg | 2 +-
.../pll_clk125/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/pll_clk125/hdllib.cfg | 2 +-
.../pll_clk200/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/pll_clk200/hdllib.cfg | 2 +-
.../pll_clk25/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/pll_clk25/hdllib.cfg | 2 +-
.../pll_xgmii_mac_clocks/compile_ip.tcl | 2 +-
.../pll_xgmii_mac_clocks/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/ram/README.txt | 2 +-
.../ip_arria10_e3sge3/ram/generate_ip.sh | 2 +-
.../ram/ip_arria10_e3sge3_ram_cr_cw.vhd | 2 +-
.../ram/ip_arria10_e3sge3_ram_crw_crw.vhd | 2 +-
.../ram/ip_arria10_e3sge3_ram_crwk_crw.vhd | 2 +-
.../ram/ip_arria10_e3sge3_ram_r_w.vhd | 2 +-
.../temp_sense/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/temp_sense/hdllib.cfg | 2 +-
.../transceiver_pll_10g/compile_ip.tcl | 2 +-
.../transceiver_pll_10g/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../transceiver_reset_controller_1/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../transceiver_reset_controller_4/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../tse_sgmii_gx/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg | 2 +-
.../tse_sgmii_lvds/compile_ip.tcl | 2 +-
.../tse_sgmii_lvds/hdllib.cfg | 2 +-
.../voltage_sense/compile_ip.tcl | 2 +-
.../voltage_sense/hdllib.cfg | 2 +-
.../ddr3_mem_model/compile_ip.tcl | 3 +-
.../compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../ddr3_uphy_16g_dual_rank_800/hdllib.cfg | 2 +-
.../ddr3_uphy_4g_800_master/compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../ddr3_uphy_4g_800_master/hdllib.cfg | 2 +-
.../ddr3_uphy_4g_800_slave/compile_ip.tcl | 2 +-
.../ddr3_uphy_4g_800_slave/copy_hex_files.tcl | 2 +-
.../ddr3_uphy_4g_800_slave/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../ip_stratixiv/mac_10g/compile_ip.tcl | 2 +-
.../altera_avalon_sc_fifo_0001.vho | 16 +-
.../altera_avalon_sc_fifo_0002.vho | 16 +-
.../altera_avalon_sc_fifo_0003.vho | 12 +-
.../altera_avalon_sc_fifo_0004.vho | 16 +-
.../altera_merlin_master_translator_0001.vho | 6 +-
.../ip_stratixiv/mac_10g/hdllib.cfg | 2 +-
.../ip_stratixiv/phy_xaui/compile_ip.tcl | 2 +-
.../ip_stratixiv/phy_xaui/compile_ip_soft.tcl | 2 +-
.../ip_stratixiv/phy_xaui/hdllib.cfg | 2 +-
libraries/technology/mac_10g/hdllib.cfg | 2 +-
.../mac_10g/tech_mac_10g_arria10_e1sg.vhd | 2 +-
.../mac_10g/tech_mac_10g_component_pkg.vhd | 2 +-
libraries/technology/mult/hdllib.cfg | 2 +-
.../technology/mult/tech_complex_mult.vhd | 2 +-
libraries/technology/pll/hdllib.cfg | 8 +-
libraries/technology/pll/tech_pll_clk125.vhd | 2 +-
libraries/technology/pll/tech_pll_clk200.vhd | 2 +-
libraries/technology/pll/tech_pll_clk25.vhd | 2 +-
.../pll/tech_pll_xgmii_mac_clocks.vhd | 2 +-
libraries/technology/tse/hdllib.cfg | 4 +-
.../technology/tse/tech_tse_arria10_e1sg.vhd | 4 +-
.../technology/tse/tech_tse_component_pkg.vhd | 12 +-
453 files changed, 559 insertions(+), 3273 deletions(-)
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
delete mode 100644 libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index e9680ed83e..5274dbde50 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -42,7 +42,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
$RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index 4e1e86e84b..a9fe01c699 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -42,7 +42,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
$RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index a11a44ecae..e5201297eb 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -36,7 +36,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_test/doc/README b/boards/uniboard1/designs/unb1_test/doc/README
index bb6725a13e..9eca9c326a 100644
--- a/boards/uniboard1/designs/unb1_test/doc/README
+++ b/boards/uniboard1/designs/unb1_test/doc/README
@@ -121,7 +121,7 @@ The 2nd tcl file can be created with Quartus. Here are the steps:
- generate the IP's by running: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
- Start synthesis in the Quartus GUI. Only the Analysis step!!
- Then in Quartus click: Tools/TclScripts.
- Open the Tcl file: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
+ Open the Tcl file: $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
Click Run.
- Then Continue synthesis with Fitter, or restart with Analysis.
- Copy the generated build/unb1_test_ddr_MB_I_II.qsf file to ./designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_MB_I_II_pins_constraints.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
index 67096db24e..9c83f47a8d 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
@@ -41,8 +41,8 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- #$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
index b45e077994..14de696954 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
@@ -41,8 +41,8 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- #$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
index 984c18f3c3..64451014be 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
@@ -42,7 +42,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
index 0f81d33534..48f3e6132c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
@@ -41,7 +41,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
index a3dc5f59d0..87fbbf48a8 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
@@ -41,7 +41,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
index 3c0d599d00..92dd925a66 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
@@ -41,7 +41,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
index 2141317b49..ffb6a7e81a 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
@@ -41,7 +41,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
index fc8059c27d..76ca23e4b7 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
@@ -40,7 +40,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index fe384d7392..6b8dd8ebd1 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -28,9 +28,9 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
+ $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
+ $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
+ $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index c5353b2262..a45392e234 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -121,7 +121,7 @@ PACKAGE ddr3_pkg IS
CONSTANT c_ddr3_seq : t_ddr3_seq := (64, 1, 16, 4, 0, 5);
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -173,7 +173,7 @@ PACKAGE ddr3_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index 6fd0f1dfc4..7b331603b5 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -41,17 +41,17 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
ip_arria10_e1sg_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
- ip_arria10_e1sg_phy_10gbase_r_3 ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180
- ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180
- ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180
- ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180
- ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180
- ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180
- ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180
- ip_arria10_e1sg_transceiver_reset_controller_3 ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_180
- ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180
- ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180
- ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180
+ ip_arria10_e1sg_phy_10gbase_r_3 ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170
+ ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_3 ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170
synth_files =
sim_10gbase_r.vhd
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
index a7600bb30b..a4bfba0a13 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
@@ -21,18 +21,18 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_170;
LIBRARY IEEE, tech_pll_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/clkbuf/hdllib.cfg b/libraries/technology/clkbuf/hdllib.cfg
index 8f8e995b7c..64d48639a1 100644
--- a/libraries/technology/clkbuf/hdllib.cfg
+++ b/libraries/technology/clkbuf/hdllib.cfg
@@ -7,7 +7,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_clkbuf_global ip_arria10_clkbuf_global_altclkctrl_150
ip_arria10_e3sge3_clkbuf_global ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
- ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_180
+ ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_170
synth_files =
tech_clkbuf_component_pkg.vhd
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index 621bc2a7c2..b55e51bdde 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
-LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_180;
+LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_170;
ENTITY tech_clkbuf IS
GENERIC (
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index c19a8419fd..f26d433199 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -33,10 +33,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_ddr4_8g_1600 ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151
ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151
ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
- ip_arria10_e1sg_ddr4_4g_1600 ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180
- ip_arria10_e1sg_ddr4_8g_1600 ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180
- ip_arria10_e1sg_ddr4_4g_2000 ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180
- ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180
+ ip_arria10_e1sg_ddr4_4g_1600 ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170
+ ip_arria10_e1sg_ddr4_8g_1600 ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170
+ ip_arria10_e1sg_ddr4_4g_2000 ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170
+ ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170
ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
index 7f86edd95a..6564425f2d 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
@@ -34,10 +34,10 @@
-- DDR interface monitoring purposes.
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180;
-LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180;
-LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180;
-LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180;
+LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170;
LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index 64314ddc33..011b01a5c1 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -83,7 +83,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
@@ -134,7 +134,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -186,7 +186,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS
PORT (
@@ -237,7 +237,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
COMPONENT ip_stratixiv_ddr3_uphy_16g_dual_rank_800 IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -293,7 +293,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim/ip_arria10_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
COMPONENT ip_arria10_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -331,7 +331,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim/ip_arria10_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
COMPONENT ip_arria10_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -373,7 +373,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -449,7 +449,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -491,7 +491,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -567,7 +567,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index 229a8e1824..e0b73443cc 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -32,7 +32,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
------------------------------------------------------------------------------
-- Manually derived VHDL entity from Verilog module alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv in:
- -- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
+ -- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en IS
GENERIC (
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index bbb6a855c1..770dc9a79d 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -16,8 +16,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_remote_update ip_arria10_remote_update_altera_remote_update_150
ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
- ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180
- ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_180
+ ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170
+ ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_170
synth_files =
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index a546364ef1..8ab9280968 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
---LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180;
+--LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170;
ENTITY tech_flash_asmi_parallel IS
GENERIC (
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index 8c54bb8882..f0949faec2 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_remote_update_altera_remote_update_150;
LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
-LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_180;
+LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_170;
ENTITY tech_flash_remote_update IS
GENERIC (
diff --git a/libraries/technology/fpga_temp_sens/hdllib.cfg b/libraries/technology/fpga_temp_sens/hdllib.cfg
index 97baab4751..2e5124c781 100644
--- a/libraries/technology/fpga_temp_sens/hdllib.cfg
+++ b/libraries/technology/fpga_temp_sens/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_temp_sense ip_arria10_temp_sense_altera_temp_sense_150
ip_arria10_e3sge3_temp_sense ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
- ip_arria10_e1sg_temp_sense ip_arria10_e1sg_temp_sense_altera_temp_sense_180
+ ip_arria10_e1sg_temp_sense ip_arria10_e1sg_temp_sense_altera_temp_sense_170
synth_files =
tech_fpga_temp_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index 749310fa3d..65a773084a 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
-LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_180;
+LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_170;
ENTITY tech_fpga_temp_sens IS
diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg
index a9c9d063c0..03aaf853ed 100644
--- a/libraries/technology/fpga_voltage_sens/hdllib.cfg
+++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_voltage_sense ip_arria10_voltage_sense_altera_voltage_sense_150
ip_arria10_e3sge3_voltage_sense ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
- ip_arria10_e1sg_voltage_sense ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180
+ ip_arria10_e1sg_voltage_sense ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170
synth_files =
tech_fpga_voltage_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index f16657aba0..bc66f172fd 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
-LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180;
+LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170;
ENTITY tech_fpga_voltage_sens IS
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index 4814f9b5de..3c2cf1abd6 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -10,8 +10,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_fractional_pll_clk125 ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150
ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151
ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
- ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180
- ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180
+ ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170
+ ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170
synth_files =
tech_fractional_pll_component_pkg.vhd
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index 287a6098d4..cc8f297c07 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170;
ENTITY tech_fractional_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 4a986c4c47..f30733508e 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170;
ENTITY tech_fractional_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
index ae2df593eb..5e5795ffac 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/clkbuf_global/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
index d3d850ad78..102fa8aac0 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_clkbuf_global.qip
+ ip_arria10_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/complex_mult/README.txt b/libraries/technology/ip_arria10/complex_mult/README.txt
index 3e33649f60..c9a33bbdfc 100644
--- a/libraries/technology/ip_arria10/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10/complex_mult/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_complex_mult.qip
+ ip_arria10_complex_mult.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
index 6827e85513..43acb41dbe 100644
--- a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/complex_mult/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
index b61b700ebc..962d1268ca 100644
--- a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_complex_mult.qip
+ ip_arria10_complex_mult.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/ddio/compile_ip.tcl b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
index 430497004b..64aba5490a 100644
--- a/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddio/generated/"
+ set IP_DIR "$env(HDL_BUILD_DIR)/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_150 ./work/
diff --git a/libraries/technology/ip_arria10/ddio/hdllib.cfg b/libraries/technology/ip_arria10/ddio/hdllib.cfg
index cdf478319d..79383ba97b 100644
--- a/libraries/technology/ip_arria10/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddio/hdllib.cfg
@@ -18,8 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_ddio_in_1.qip
- generated/ip_arria10_ddio_out_1.qip
+ ip_arria10_ddio_in_1.qip
+ ip_arria10_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
index 5dd0355376..92b736708c 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
index ffbd501ac2..fca54fa813 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
index cd9ab6a0c9..d6d5dd48ae 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_ddr4_4g_1600.qip
+ ip_arria10_ddr4_4g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
index 3bd52fc027..ec106dc119 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
index 91add01c14..e0de434cf6 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
index cf1a8b5f46..558f712cc2 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_ddr4_4g_2000.qip
+ ip_arria10_ddr4_4g_2000.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
index 24bb783efe..748f3779e1 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
index e1301d8ab0..dca56d5c3c 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
index 9883e05153..1687d60fab 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_ddr4_8g_2400.qip
+ ip_arria10_ddr4_8g_2400.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/fifo/README.txt b/libraries/technology/ip_arria10/fifo/README.txt
index cfe2a2a2d8..6db25b6412 100755
--- a/libraries/technology/ip_arria10/fifo/README.txt
+++ b/libraries/technology/ip_arria10/fifo/README.txt
@@ -38,7 +38,7 @@ Contents:
The IP only needs to be generated with ./generate_ip.sh if it need to be modified, because the ip_arria10_fifo_*.vhd
directly instantiates the altera_mf component.
- The instantiation is copied manually from the generated/ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
+ The instantiation is copied manually from the ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
saved in the <fifo_name>.vhd file. So then the MegaWizard vhd file is overwritten, but that is fine because it is
no longer needed, it could easily be derived from the original in $UNB and it is still as a previous verion in SVN.
diff --git a/libraries/technology/ip_arria10/fifo/generate_ip.sh b/libraries/technology/ip_arria10/fifo/generate_ip.sh
index 11005f95c6..1607650bfa 100755
--- a/libraries/technology/ip_arria10/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10/fifo/generate_ip.sh
@@ -33,7 +33,7 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_fifo_*.vhd directly instantiates
# the FIFO altera_mf component.
-# The instantiation is copied manually from the generated/ip_arria10_ram_*/fifo_140/sim/ip_arria10_fifo_*.vhd.
+# The instantiation is copied manually from the ip_arria10_ram_*/fifo_140/sim/ip_arria10_fifo_*.vhd.
# It appears that the altera_mf FIFO component for Arria10 can be synthesized similar as how it worked for Stratix IV,
# it is not necessary to use the generated qip file.
#
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
index 94b0a67c51..7ad84ee07b 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/flash/asmi_parallel/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
vmap ip_arria10_asmi_parallel_altera_asmi_parallel_150 ./work/
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
index fada8c8e47..a9fea8a6d5 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_asmi_parallel.qip
+ ip_arria10_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
index 525eab6a87..46836c8393 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/flash/remote_update/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
vmap ip_arria10_remote_update_altera_remote_update_core_150 ./work/
vmap ip_arria10_remote_update_altera_remote_update_150 ./work/
diff --git a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
index 464e3bdf68..32cacf3e6b 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_remote_update.qip
+ ip_arria10_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
index 9611ac9b64..80a62c6672 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/fractional_pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
index 71d929e9ed..f413ae490e 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_fractional_pll_clk125.qip
+ ip_arria10_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
index 09f0c82f72..8d2f641fcc 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/fractional_pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
index 6b6b3cef3a..1f2b253889 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_fractional_pll_clk200.qip
+ ip_arria10_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/mac_10g/README.txt b/libraries/technology/ip_arria10/mac_10g/README.txt
index 1809358e9c..c775402d02 100644
--- a/libraries/technology/ip_arria10/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10/mac_10g/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_mac_10g.qip
+ ip_arria10_mac_10g.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
index 0f37f969c4..1865ab2bb0 100644
--- a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/mac_10g/generated/sim"
-set IP_TBDIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_TBDIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
index bd87b3444a..4a0011ee35 100644
--- a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim/ip_arria10_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
[modelsim_project_file]
@@ -19,7 +19,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_mac_10g.qip
+ ip_arria10_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
index f834dcc99e..464263f96b 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
@@ -41,7 +41,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_phy_10gbase_r.qip
+ ip_arria10_phy_10gbase_r.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
index a2f5e5be10..05fdc5ebb7 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
index b4fc8605ca..dc9cdc38dd 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_phy_10gbase_r.qip
+ ip_arria10_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
index 7130d548d2..4df7738bdc 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
index 52866d7080..574c29ca06 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_phy_10gbase_r_12.qip
+ ip_arria10_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
index ecd8cac0a1..5ef95c261f 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
index 0c22bfef18..7aa111c072 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_phy_10gbase_r_24.qip
+ ip_arria10_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
index 319a668123..4df2e0bdec 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
index 9066174d78..6438682b22 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_phy_10gbase_r_4.qip
+ ip_arria10_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
index 89d1df9134..53e06e4de1 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
index 3372c4933b..d280316c1b 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_phy_10gbase_r_48.qip
+ ip_arria10_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
index ceb880b971..ca650eea03 100644
--- a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
index 716dc23633..b6b6d86efd 100644
--- a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_pll_clk125.qip
+ ip_arria10_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
index 45f591f9eb..88558ac778 100644
--- a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
index a2cceba6b3..c3b7fa01be 100644
--- a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_pll_clk200.qip
+ ip_arria10_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
index 8d6c1ffe3a..65f55bd48d 100644
--- a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk25/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
index 9254e79292..3a1a86267a 100644
--- a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_pll_clk25.qip
+ ip_arria10_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
index b9f8625f8c..20e438b4c1 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
index e868b714af..7fb31eb197 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_pll_xgmii_mac_clocks.qip
+ ip_arria10_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/ram/README.txt b/libraries/technology/ip_arria10/ram/README.txt
index a9fe41102a..24ad4ab94e 100755
--- a/libraries/technology/ip_arria10/ram/README.txt
+++ b/libraries/technology/ip_arria10/ram/README.txt
@@ -32,7 +32,7 @@ Contents:
if it need to be modified, because the ip_arria10_ram_*.vhd directly instantiates the altera_syncram component.
- The instantiation is copied manually from the generated/ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
+ The instantiation is copied manually from the ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
diff --git a/libraries/technology/ip_arria10/ram/generate_ip.sh b/libraries/technology/ip_arria10/ram/generate_ip.sh
index c1ca91ebd0..188eef243f 100755
--- a/libraries/technology/ip_arria10/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ram/generate_ip.sh
@@ -33,7 +33,7 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_ram_*.vhd directly instantiates
# the altera_syncram component.
-# The instantiation is copied manually from the generated/ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
+# The instantiation is copied manually from the ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
# It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
# that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
#
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
index e8c756ea16..94c873952b 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
@@ -99,7 +99,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_ram_cr_cw/ram_2port_140/sim/ip_arria10_ram_cr_cw_ram_2port_140_72tpmcy.vhd
+ -- Copied from ip_arria10_ram_cr_cw/ram_2port_140/sim/ip_arria10_ram_cr_cw_ram_2port_140_72tpmcy.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
index 70e872b00d..f1694d5462 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
@@ -115,7 +115,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_ram_crw_crw/ram_2port_140/sim/ip_arria10_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
+ -- Copied from ip_arria10_ram_crw_crw/ram_2port_140/sim/ip_arria10_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
index 08dce27a64..0a9ee2b831 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
@@ -95,7 +95,7 @@ ARCHITECTURE SYN OF ip_arria10_ram_crwk_crw IS
BEGIN
- -- Copied from generated/ip_arria10_ram_crwk_crw/ram_2port_140/sim/ip_arria10_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
+ -- Copied from ip_arria10_ram_crwk_crw/ram_2port_140/sim/ip_arria10_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
index 2399d0eb74..9cd46d0f8c 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
@@ -96,7 +96,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_ram_r_w : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_ram_r_w/ram_2port_140/sim/ip_arria10_ram_r_w_ram_2port_140_hukd7xi.vhd
+ -- Copied from ip_arria10_ram_r_w/ram_2port_140/sim/ip_arria10_ram_r_w_ram_2port_140_hukd7xi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
index fa0b733b48..e24b47eab8 100644
--- a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/temp_sense/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
index 743b54a4f8..7712a5afed 100644
--- a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
@@ -15,7 +15,7 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_temp_sense.qip
+quartus_qip_files = ip_arria10_temp_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
index 51e4722bd7..0ca0862832 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_pll_10g/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
index be5fa19d53..ab125a22db 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_pll_10g.qip
+ ip_arria10_transceiver_pll_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
index 69d2418773..ede7525a7c 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_1/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
index 64be140c28..45b9e866ea 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_reset_controller_1.qip
+ ip_arria10_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
index 22ce7e0c27..7e487453a1 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
index f5aa17bd77..8cb43574cb 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_reset_controller_12.qip
+ ip_arria10_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
index 1a97798dde..4b2d7cd58b 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
index f9d08597da..02bdc47594 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_reset_controller_24.qip
+ ip_arria10_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
index 1d2e7d4997..2adc9e61a6 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
index 7e5fb7f0d3..e2f5fe2620 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_reset_controller_4.qip
+ ip_arria10_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
index 62da163837..89dc59e26a 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
index a519b5da8e..9e5de0cc3e 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_reset_controller_48.qip
+ ip_arria10_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
index 22a2478a6c..97a8f992de 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
index 76550d695f..f4b67edbe2 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_tse_sgmii_gx.qip
+ ip_arria10_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
index 395170e9f5..a9062836f7 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
index f840e7826f..a9294f7aa9 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_tse_sgmii_lvds.qip
+ ip_arria10_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
index 0e31995904..03e7c495f2 100644
--- a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/voltage_sense/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
index 72730345ec..bd24313b84 100644
--- a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_voltage_sense.qip
+quartus_qip_files = ip_arria10_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
deleted file mode 100644
index 169569c196..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
+++ /dev/null
@@ -1,149 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
-
-vmap alt_em10g32_180 ./work/
-
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/alt_em10g32.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/alt_em10g32unit.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_clk_rst.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_clock_crosser.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_crc32.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_creg_map.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_creg_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_frm_decoder.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_pipeline_base.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rst_cnt.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_frm_control.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_stat_mem.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_stat_reg.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_flow_control.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_pause_req.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rr_buffer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_sc_fifo.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_altsyncram.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii_ultra.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii_tsu.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii16b_tsu.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_lpm_mult.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_ptp_processor.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_crc328generator.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_crc32ctl8.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_crc32galois8.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii16b_crc_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii16b_crc32.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/alt_em10g32_avalon_dc_fifo.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/alt_em10g32_dcfifo_synchronizer_bundle.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/alt_em10g32_std_synchronizer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/altera_std_synchronizer_nocut.v" -work alt_em10g32_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg
deleted file mode 100644
index 0276da73e5..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_alt_em10g32_180
-hdl_library_clause_name = alt_em10g32_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
- # The generated testbench is listed here to create a simulation configuration for it. However
- # the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
deleted file mode 100644
index 7fab7f0b8e..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap alt_mem_if_jtag_master_180 ./work/
-
- vcom "$IP_DIR/../alt_mem_if_jtag_master_180/sim/ip_arria10_e1sg_ddr4_8g_1600_alt_mem_if_jtag_master_180_biwt3uq.vhd" -work alt_mem_if_jtag_master_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg
deleted file mode 100644
index 21f6ab7cfc..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_alt_mem_if_jtag_master_180
-hdl_library_clause_name = alt_mem_if_jtag_master_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_jtag_dc_streaming_180 ip_arria10_e1sg_timing_adapter_180 ip_arria10_e1sg_altera_avalon_sc_fifo_180 ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_180 ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_180 ip_arria10_e1sg_altera_avalon_packets_to_master_180 ip_arria10_e1sg_channel_adapter_180 ip_arria10_e1sg_altera_reset_controller_180
-
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
deleted file mode 100644
index 75d1e499c6..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
+++ /dev/null
@@ -1,35 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
-
-vmap altclkctrl_180 ./work/
- vcom "$IP_DIR/../altclkctrl_180/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_180_7fwzyby.vhd" -work altclkctrl_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg
deleted file mode 100644
index d16da4aa98..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altclkctrl_180
-hdl_library_clause_name = altclkctrl_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
deleted file mode 100644
index 72d66d3bbe..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
-
-vmap altera_asmi_parallel_180 ./work/
-
-
- vcom "$IP_DIR/../altera_asmi_parallel_180/sim/ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180_eou4tfa.vhd" -work altera_asmi_parallel_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg
deleted file mode 100644
index 6a653a1689..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_asmi_parallel_180
-hdl_library_clause_name = altera_asmi_parallel_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
deleted file mode 100644
index 810bc500b8..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
+++ /dev/null
@@ -1,35 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
-vmap altera_avalon_mm_bridge_180 ./work/
-
- vlog "$IP_DIR/../altera_avalon_mm_bridge_180/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg
deleted file mode 100644
index 97f5b33a72..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_mm_bridge_180
-hdl_library_clause_name = altera_avalon_mm_bridge_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
- # The generated testbench is listed here to create a simulation configuration for it. However
- # the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
deleted file mode 100644
index c0eaa3adca..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
+++ /dev/null
@@ -1,46 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-vmap altera_avalon_onchip_memory2_180 ./work/
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg
deleted file mode 100644
index 3f74f6bb14..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_onchip_memory2_180
-hdl_library_clause_name = altera_avalon_onchip_memory2_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
deleted file mode 100644
index 0544c814cd..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap altera_avalon_packets_to_master_180 ./work/
-
- vlog "$IP_DIR/../altera_avalon_packets_to_master_180/sim/altera_avalon_packets_to_master.v" -work altera_avalon_packets_to_master_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg
deleted file mode 100644
index 3289315446..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_packets_to_master_180
-hdl_library_clause_name = altera_avalon_packets_to_master_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
deleted file mode 100644
index f852a2af5b..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
+++ /dev/null
@@ -1,40 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap altera_avalon_sc_fifo_180 ./work/
- vlog "$IP_DIR/../altera_avalon_sc_fifo_180/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_180
-
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg
deleted file mode 100644
index 7bf034a3bc..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_sc_fifo_180
-hdl_library_clause_name = altera_avalon_sc_fifo_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
deleted file mode 100644
index 12e257917d..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap altera_avalon_st_bytes_to_packets_180 ./work/
-
- vlog "$IP_DIR/../altera_avalon_st_bytes_to_packets_180/sim/altera_avalon_st_bytes_to_packets.v" -work altera_avalon_st_bytes_to_packets_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg
deleted file mode 100644
index 55d4345da9..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_180
-hdl_library_clause_name = altera_avalon_st_bytes_to_packets_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
deleted file mode 100644
index f289716983..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
+++ /dev/null
@@ -1,39 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-vmap altera_avalon_st_packets_to_bytes_180 ./work/
-
- vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_180/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_180
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg
deleted file mode 100644
index 3b7ae8e33f..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_180
-hdl_library_clause_name = altera_avalon_st_packets_to_bytes_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
deleted file mode 100644
index b2b1fad697..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
+++ /dev/null
@@ -1,162 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-vmap altera_emif_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180_fpxzpei.v" -work altera_emif_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180_e7aaa3y.v" -work altera_emif_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180_zmrgaza.v" -work altera_emif_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180_xxodvzi.v" -work altera_emif_180
-
-vmap altera_emif_arch_nf_180 ./work/
-# ddr4_4g_1600
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti.sv" -work altera_emif_arch_nf_180
-
-# ddr4_4g_2000
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq.sv" -work altera_emif_arch_nf_180
-
-# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei.sv" -work altera_emif_arch_nf_180
-
-# ddr4_8g_2400
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i.sv" -work altera_emif_arch_nf_180
-
-# common dependencies
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_oct.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_180
- vlog "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_180
-
-vmap altera_emif_cal_slave_nf_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-vmap altera_reset_controller_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_180
- vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_180
-
-vmap altera_mm_interconnect_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_3gbam2q.vhd" -work altera_mm_interconnect_180
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_lcqbbfq.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
-vmap altera_avalon_onchip_memory2_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-
-vmap altera_avalon_mm_bridge_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
- vlog "$IP_DIR/../altera_avalon_mm_bridge_180/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg
deleted file mode 100644
index b934e75cc0..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_emif_180
-hdl_library_clause_name = altera_emif_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_180 ip_arria10_e1sg_altera_merlin_slave_translator_180
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
deleted file mode 100644
index e641ceb72f..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
+++ /dev/null
@@ -1,98 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-vmap altera_emif_arch_nf_180 ./work/
-
-# ddr4_4g_1600
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti.sv" -work altera_emif_arch_nf_180
-
-# ddr4_4g_2000
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq.sv" -work altera_emif_arch_nf_180
-
-# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei.sv" -work altera_emif_arch_nf_180
-
-# ddr4_8g_2400
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i.sv" -work altera_emif_arch_nf_180
-
-# common dependencies
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_oct.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_180
- vlog "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg
deleted file mode 100644
index 88ddb715cb..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_emif_arch_nf_180
-hdl_library_clause_name = altera_emif_arch_nf_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
- # The generated testbench is listed here to create a simulation configuration for it. However
- # the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
deleted file mode 100644
index 7e92b4234e..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
+++ /dev/null
@@ -1,47 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-vmap altera_emif_cal_slave_nf_180 ./work/
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg
deleted file mode 100644
index b7252eec61..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_emif_cal_slave_nf_180
-hdl_library_clause_name = altera_emif_cal_slave_nf_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
deleted file mode 100644
index 0ba63276ca..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
+++ /dev/null
@@ -1,40 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-vmap altera_eth_tse_180 ./work/
-
-# tse_sgmii_gx
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
-vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180_bs6nd6i.vhd" -work altera_eth_tse_180
-
-# tse_sgmii_lvds
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
-vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180_kv2t7sq.vhd" -work altera_eth_tse_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg
deleted file mode 100644
index 06e083362f..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_180
-hdl_library_clause_name = altera_eth_tse_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-ip_arria10_e1sg_altera_eth_tse_mac_180
-ip_arria10_e1sg_altera_eth_tse_avalon_arbiter_180
-ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_phyip_180
-ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_lvds_180
-ip_arria10_e1sg_altera_xcvr_native_a10_180
-ip_arria10_e1sg_altera_eth_tse_nf_phyip_terminator_180
-ip_arria10_e1sg_altera_eth_tse_nf_lvds_terminator_180
-ip_arria10_e1sg_altera_lvds_180
-ip_arria10_e1sg_altera_reset_controller_180
-
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
deleted file mode 100644
index 745643de56..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
+++ /dev/null
@@ -1,33 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
-vmap altera_eth_tse_avalon_arbiter_180 ./work/
- vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_180/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg
deleted file mode 100644
index dfd8b2b09d..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_avalon_arbiter_180
-hdl_library_clause_name = altera_eth_tse_avalon_arbiter_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
deleted file mode 100644
index cd0fcdb40a..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
+++ /dev/null
@@ -1,148 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
-
-vmap altera_eth_tse_mac_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_eth_tse_mac.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_clk_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_crc328checker.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_crc328generator.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_crc32ctl8.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_crc32galois8.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_gmii_io.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_lb_read_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_lb_wrt_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_hashing.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_host_control.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_host_control_small.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mac_control.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_register_map.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_register_map_small.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_counter_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_shared_mac_control.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_shared_register_map.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_counter_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_lfsr_10.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_loopback_ff.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_altshifttaps.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_fifoless_mac_rx.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mac_rx.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_fifoless_mac_tx.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mac_tx.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_magic_detection.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mdio.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mdio_clk_gen.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mdio_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_mdio.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mii_rx_if.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mii_tx_if.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_pipeline_base.v" -work altera_eth_tse_mac_180
- vlog -sv "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_pipeline_stage.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_dpram_16x32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_dpram_8x32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_dpram_ecc_16x32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_fifoless_retransmit_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_retransmit_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rgmii_in1.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rgmii_in4.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_nf_rgmii_module.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rgmii_module.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rgmii_out1.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rgmii_out4.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_ff.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_min_ff.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_ff_cntrl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_ff_cntrl_32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_ff_length.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_stat_extract.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_timing_adapter32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_timing_adapter8.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_timing_adapter_fifo32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_timing_adapter_fifo8.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_1geth.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_fifoless_1geth.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_w_fifo.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_w_fifo_10_100_1000.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_wo_fifo.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_wo_fifo_10_100_1000.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_gen_host.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_min_ff.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff_cntrl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff_cntrl_32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff_length.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff_read_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_stat_extract.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_mac_180
- vlog -sv "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_mac_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg
deleted file mode 100644
index 3ca851ab1d..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_mac_180
-hdl_library_clause_name = altera_eth_tse_mac_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
deleted file mode 100644
index 01cb1beef8..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
+++ /dev/null
@@ -1,40 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
-vmap altera_eth_tse_nf_lvds_terminator_180 ./work/
-
-
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_180
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/mentor/altera_eth_tse_nf_lvds_terminator.v" -work altera_eth_tse_nf_lvds_terminator_180
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_180
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/mentor/altera_tse_nf_lvds_channel_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_180
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/mentor/altera_tse_nf_lvds_common_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_180
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_nf_lvds_terminator_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg
deleted file mode 100644
index 6cc184f5c6..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_nf_lvds_terminator_180
-hdl_library_clause_name = altera_eth_tse_nf_lvds_terminator_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
deleted file mode 100644
index b52152f566..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
+++ /dev/null
@@ -1,35 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
-
-vmap altera_eth_tse_nf_phyip_terminator_180 ./work/
-
- vlog "$IP_DIR/../altera_eth_tse_nf_phyip_terminator_180/sim/mentor/altera_eth_tse_nf_phyip_terminator.v" -work altera_eth_tse_nf_phyip_terminator_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg
deleted file mode 100644
index 20e2f82c82..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_nf_phyip_terminator_180
-hdl_library_clause_name = altera_eth_tse_nf_phyip_terminator_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
deleted file mode 100644
index 60f0c2d8ee..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
+++ /dev/null
@@ -1,114 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
-
-vmap altera_eth_tse_pcs_pma_nf_lvds_180 ./work/
-
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_eth_tse_pcs_pma_nf_lvds.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_lvds_reset_sequencer.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_lvds_reverse_loopback.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_pma_lvds_rx_av.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_pma_lvds_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_pma_lvds_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ph_calculator.sv" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg
deleted file mode 100644
index e32f89526d..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_lvds_180
-hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_lvds_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
deleted file mode 100644
index 3cd6e2eef4..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
+++ /dev/null
@@ -1,116 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
-
-
-vmap altera_eth_tse_pcs_pma_nf_phyip_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
-
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_eth_tse_pcs_pma_nf_phyip.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_reset_sequencer.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_reset_ctrl_lego.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_xcvr_resync.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_gxb_aligned_rxsync.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg
deleted file mode 100644
index 37eeea4205..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_phyip_180
-hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_phyip_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
deleted file mode 100644
index 1f120ec18e..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
+++ /dev/null
@@ -1,41 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-vmap altera_iopll_180 ./work/
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
- vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_180_7lq52ua.vo" -work altera_iopll_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
- vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_180_3a4ewza.vo" -work altera_iopll_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
- vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_180_bqwoevq.vo" -work altera_iopll_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg
deleted file mode 100644
index cd252f68f6..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_iopll_180
-hdl_library_clause_name = altera_iopll_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
deleted file mode 100644
index b6b2f7ec3a..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap altera_ip_col_if_180 ./work/
-
- vlog "$IP_DIR/../altera_ip_col_if_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_ip_col_if_180_bnb3mmy.v" -work altera_ip_col_if_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg
deleted file mode 100644
index 3ba5bffd7c..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_ip_col_if_180
-hdl_library_clause_name = altera_ip_col_if_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
deleted file mode 100644
index 31fd279855..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
+++ /dev/null
@@ -1,45 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap altera_jtag_dc_streaming_180 ./work/
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_jtag_dc_streaming.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_jtag_sld_node.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_jtag_streaming.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_clock_crosser.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_std_synchronizer_nocut.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_pipeline_base.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_idle_remover.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_idle_inserter.v" -work altera_jtag_dc_streaming_180
- vlog -sv "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_pipeline_stage.sv" -work altera_jtag_dc_streaming_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg
deleted file mode 100644
index 9ab2d1bf11..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_jtag_dc_streaming_180
-hdl_library_clause_name = altera_jtag_dc_streaming_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
deleted file mode 100644
index c015c3a84b..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
+++ /dev/null
@@ -1,34 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
-vmap altera_lvds_180 ./work/
- vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_m5pqrlq.vhd" -work altera_lvds_180
- vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_o42lhkq.vhd" -work altera_lvds_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg
deleted file mode 100644
index c9f081b5e9..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_lvds_180
-hdl_library_clause_name = altera_lvds_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_lvds_core20_180
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
deleted file mode 100644
index 9b8d787a34..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
+++ /dev/null
@@ -1,39 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
-vmap altera_lvds_core20_180 ./work/
-
-
- vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_180
- vlog "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
- vcom "$IP_DIR/../altera_lvds_core20_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_180_qagiwoa.vhd" -work altera_lvds_core20_180
- vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_180
- vlog "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
- vcom "$IP_DIR/../altera_lvds_core20_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_180_o4ldvbi.vhd" -work altera_lvds_core20_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg
deleted file mode 100644
index 7c32b3d809..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_lvds_core20_180
-hdl_library_clause_name = altera_lvds_core20_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
deleted file mode 100644
index 463209d51d..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
+++ /dev/null
@@ -1,36 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
-vmap altera_merlin_master_translator_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_merlin_master_translator_180/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg
deleted file mode 100644
index 2b22aa3b9b..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_merlin_master_translator_180
-hdl_library_clause_name = altera_merlin_master_translator_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
deleted file mode 100644
index 88f541d2de..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
+++ /dev/null
@@ -1,36 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
-vmap altera_merlin_slave_translator_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_merlin_slave_translator_180/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg
deleted file mode 100644
index 91f77c91d4..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_merlin_slave_translator_180
-hdl_library_clause_name = altera_merlin_slave_translator_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
deleted file mode 100644
index eaafd3dcc5..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
+++ /dev/null
@@ -1,46 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-vmap altera_mm_interconnect_180 ./work/
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_3gbam2q.vhd" -work altera_mm_interconnect_180
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_lcqbbfq.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg
deleted file mode 100644
index 73f5fa237c..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_mm_interconnect_180
-hdl_library_clause_name = altera_mm_interconnect_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_180 ip_arria10_e1sg_altera_merlin_slave_translator_180
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
deleted file mode 100644
index 33ac71fc50..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
-
-vmap altera_remote_update_180 ./work/
-
- vcom "$IP_DIR/../altera_remote_update_180/sim/ip_arria10_e1sg_remote_update_altera_remote_update_180_hsvaqga.vhd" -work altera_remote_update_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg
deleted file mode 100644
index 699861d088..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_remote_update_180
-hdl_library_clause_name = altera_remote_update_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_remote_update_core_180
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
deleted file mode 100644
index 2aeb031485..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
+++ /dev/null
@@ -1,40 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
-
-
-vmap altera_remote_update_core_180 ./work/
-
-
- vlog "$IP_DIR/../altera_remote_update_core_180/sim/mentor/altera_remote_update_core.sv" -work altera_remote_update_core_180
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg
deleted file mode 100644
index 92dcbaea09..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_remote_update_core_180
-hdl_library_clause_name = altera_remote_update_core_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
deleted file mode 100644
index 1696fa3810..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
-vmap altera_reset_controller_180 ./work/
-
- vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_180
- vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg
deleted file mode 100644
index 048e59748f..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_reset_controller_180
-hdl_library_clause_name = altera_reset_controller_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
deleted file mode 100644
index f0fadccebe..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
+++ /dev/null
@@ -1,55 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
-
-vmap altera_common_sv_packages ./work/
-vmap altera_xcvr_atx_pll_a10_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_atx_pll_rcfg_opt_logic_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg
deleted file mode 100644
index 595a260842..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_xcvr_atx_pll_a10_180
-hdl_library_clause_name = altera_xcvr_atx_pll_a10_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
deleted file mode 100644
index 4b48dd94a1..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
+++ /dev/null
@@ -1,50 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
-
-vmap altera_xcvr_fpll_a10_180 ./work/
-
-#pll_xgmii_mac_clocks
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/mentor/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/mentor/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/a10_avmm_h.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/alt_xcvr_native_avmm_nf.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_180
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg
deleted file mode 100644
index 06f182471a..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_xcvr_fpll_a10_180
-hdl_library_clause_name = altera_xcvr_fpll_a10_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
deleted file mode 100644
index 5a7cfcddb3..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
+++ /dev/null
@@ -1,98 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-vmap altera_xcvr_native_a10_180 ./work/
-vmap altera_common_sv_packages ./work/
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
-
-# common dependencies
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r_48
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r_24
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r_12
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r_4
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r_3
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# tse_sgmii_gx
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg
deleted file mode 100644
index eb5db3082a..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_xcvr_native_a10_180
-hdl_library_clause_name = altera_xcvr_native_a10_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
deleted file mode 100644
index c2e9b1f72d..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
+++ /dev/null
@@ -1,44 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
-
-vmap altera_xcvr_reset_control_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/mentor/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/mentor/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg
deleted file mode 100644
index fe27ceef66..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_xcvr_reset_control_180
-hdl_library_clause_name = altera_xcvr_reset_control_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
deleted file mode 100644
index adeb79939f..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
+++ /dev/null
@@ -1,40 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap channel_adapter_180 ./work/
-
- vlog -sv "$IP_DIR/../channel_adapter_180/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_180_bsi6toa.sv" -work channel_adapter_180
- vlog -sv "$IP_DIR/../channel_adapter_180/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_180_xbvi4ny.sv" -work channel_adapter_180
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg
deleted file mode 100644
index 553bb719ff..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_channel_adapter_180
-hdl_library_clause_name = channel_adapter_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
deleted file mode 100644
index c721f083bd..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
+++ /dev/null
@@ -1,39 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap timing_adapter_180 ./work/
-
- vlog -sv "$IP_DIR/../timing_adapter_180/sim/ip_arria10_e1sg_ddr4_8g_1600_timing_adapter_180_osazali.sv" -work timing_adapter_180
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg
deleted file mode 100644
index 342089f106..0000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_timing_adapter_180
-hdl_library_clause_name = timing_adapter_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
index 3ec2cd3bae..252951861f 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index 0f031bde49..9e1a2696f1 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_clkbuf_global
-hdl_library_clause_name = ip_arria10_e1sg_clkbuf_global_altclkctrl_180
+hdl_library_clause_name = ip_arria10_e1sg_clkbuf_global_altclkctrl_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altclkctrl_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altclkctrl_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_clkbuf_global.qip
+ ip_arria10_e1sg_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys b/libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys
index 1cf25870c5..fba6d6240d 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys
@@ -62,7 +62,7 @@
<module
name="altclkctrl_0"
kind="altclkctrl"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CLOCK_TYPE" value="1" />
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
index 3e33649f60..c9a33bbdfc 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_complex_mult.qip
+ ip_arria10_complex_mult.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
index 39c4b98614..f9948fbc5e 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -29,9 +29,8 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/complex_mult/generated/sim"
- vmap altmult_complex_180 ./work/
-
- vlog "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_altmult_complex_180_myrk3hi.v" -work altmult_complex_180
-
-vlog "$IP_DIR/ip_arria10_e1sg_complex_mult.v"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+vmap altmult_complex_170 ./work/
+ #vlog "$IP_DIR/../altmult_complex_170/sim/ip_arria10_e1sg_complex_mult_altmult_complex_170_myrk3hi.v" -work altmult_complex_170
+ vlog "$IP_DIR/../altmult_complex_170/synth/ip_arria10_e1sg_complex_mult_altmult_complex_170_myrk3hi.v" -work altmult_complex_170
+ #vlog "$IP_DIR/ip_arria10_e1sg_complex_mult_bb.v"
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
index c09f8f660f..96be7f2926 100755
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index bab3a669b2..792d355bb4 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_complex_mult
-hdl_library_clause_name = ip_arria10_e1sg_complex_mult_altmult_complex_180
+hdl_library_clause_name = ip_arria10_e1sg_complex_mult_altmult_complex_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_complex_mult.qip
+ ip_arria10_e1sg_complex_mult.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys b/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys
index 6156e6a7a6..4c2b48c320 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys
@@ -69,7 +69,7 @@
<module
name="altmult_complex_0"
kind="altmult_complex"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
index dbab4802e0..0cf7bb1d96 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# OUTDATED AND NOT USED!!
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddio/generated/"
+ set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_150 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
index 389f44f511..38843a3303 100755
--- a/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
@@ -34,7 +34,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index 4b67f37fb8..f2b64c3ae4 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -18,8 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_ddio_in_1.qip
- generated/ip_arria10_e1sg_ddio_out_1.qip
+ ip_arria10_e1sg_ddio_in_1.qip
+ ip_arria10_e1sg_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys
index 0183a6f254..5561d1ae46 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys
@@ -82,7 +82,7 @@
<module
name="ip_arria10_ddio_in_1"
kind="altera_gpio"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys
index 42fa9f2705..e212acf8eb 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys
@@ -84,7 +84,7 @@
<module
name="ip_arria10_ddio_out_1"
kind="altera_gpio"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
index 46dff72ef5..557a2cee6b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
index 82efc278ce..710e1fb69c 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,12 +22,12 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
- file copy -force $IP_DIR/../altera_avalon_onchip_memory2_180/sim/seq_cal_soft_m20k.hex ./
- file copy -force $IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_seq_cal.hex ./
- file copy -force $IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_seq_params_sim.hex ./
- file copy -force $IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_seq_params_synth.hex ./
+ file copy -force $IP_DIR/../altera_avalon_onchip_memory2_170/sim/seq_cal_soft_m20k.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_seq_cal.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_seq_params_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_seq_params_synth.hex ./
}
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
index 9e63a80dc1..9d98e72bce 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index 84d8e84cf0..275820f5ff 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_4g_1600
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_emif_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_emif_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_ddr4_4g_1600.qip
+ ip_arria10_e1sg_ddr4_4g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qsys
index 85a36dd86c..f00d65e364 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qsys
@@ -152,7 +152,7 @@
<module
name="emif_0"
kind="altera_emif"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
index 9497e3c7cc..70199c12f6 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
index 44a321affd..2063dbbb24 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
index bbbc8b7d3a..64364ce034 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index 55e704816e..20bde73a26 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_4g_2000
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_180 ip_arria10_e1sg_altera_emif_cal_slave_nf_180 ip_arria10_e1sg_altera_avalon_onchip_memory2_180 ip_arria10_e1sg_altera_mm_interconnect_180 ip_arria10_e1sg_altera_reset_controller_180 ip_arria10_e1sg_altera_emif_arch_nf_180 ip_arria10_e1sg_altera_emif_180 ip_arria10_e1sg_altera_avalon_mm_bridge_180 ip_arria10_e1sg_altera_merlin_slave_translator_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_170 ip_arria10_e1sg_altera_emif_cal_slave_nf_170 ip_arria10_e1sg_altera_avalon_onchip_memory2_170 ip_arria10_e1sg_altera_mm_interconnect_170 ip_arria10_e1sg_altera_reset_controller_170 ip_arria10_e1sg_altera_emif_arch_nf_170 ip_arria10_e1sg_altera_emif_170 ip_arria10_e1sg_altera_avalon_mm_bridge_170 ip_arria10_e1sg_altera_merlin_slave_translator_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_ddr4_4g_2000.qip
+ ip_arria10_e1sg_ddr4_4g_2000.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qsys
index cc070e9d38..58c2d117c7 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qsys
@@ -152,7 +152,7 @@
<module
name="emif_0"
kind="altera_emif"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
index ef04250d03..529636a9ca 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
index d384a4b5ea..68e998bc99 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
index 92679228d0..cf24b8c0fc 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index f77c4027e8..a1e0f76eba 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_8g_1600
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_180 ip_arria10_e1sg_altera_emif_cal_slave_nf_180 ip_arria10_e1sg_altera_avalon_onchip_memory2_180 ip_arria10_e1sg_altera_mm_interconnect_180 ip_arria10_e1sg_altera_reset_controller_180 ip_arria10_e1sg_altera_emif_arch_nf_180 ip_arria10_e1sg_altera_emif_180 ip_arria10_e1sg_altera_avalon_mm_bridge_180 ip_arria10_e1sg_altera_merlin_slave_translator_180 ip_arria10_e1sg_altera_avalon_sc_fifo_180 ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_180 ip_arria10_e1sg_altera_ip_col_if_180 ip_arria10_e1sg_altera_jtag_dc_streaming_180 ip_arria10_e1sg_alt_mem_if_jtag_master_180 ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_180 ip_arria10_e1sg_altera_avalon_packets_to_master_180 ip_arria10_e1sg_channel_adapter_180 ip_arria10_e1sg_timing_adapter_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_170 ip_arria10_e1sg_altera_emif_cal_slave_nf_170 ip_arria10_e1sg_altera_avalon_onchip_memory2_170 ip_arria10_e1sg_altera_mm_interconnect_170 ip_arria10_e1sg_altera_reset_controller_170 ip_arria10_e1sg_altera_emif_arch_nf_170 ip_arria10_e1sg_altera_emif_170 ip_arria10_e1sg_altera_avalon_mm_bridge_170 ip_arria10_e1sg_altera_merlin_slave_translator_170 ip_arria10_e1sg_altera_avalon_sc_fifo_170 ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_170 ip_arria10_e1sg_altera_ip_col_if_170 ip_arria10_e1sg_altera_jtag_dc_streaming_170 ip_arria10_e1sg_alt_mem_if_jtag_master_170 ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_170 ip_arria10_e1sg_altera_avalon_packets_to_master_170 ip_arria10_e1sg_channel_adapter_170 ip_arria10_e1sg_timing_adapter_170
hdl_lib_technology = ip_arria10_e1sg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_ddr4_8g_1600.qip
+ ip_arria10_e1sg_ddr4_8g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
index ab388d3ab2..a252c4e305 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
@@ -189,7 +189,7 @@
<module
name="emif_0"
kind="altera_emif"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
index 5798a026b4..9fc229d78e 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
index c8089fe859..668144a284 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
index 14eafe5589..b121261404 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index 9aaaa7d73e..305e04c17e 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_8g_2400
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_180 ip_arria10_e1sg_altera_emif_cal_slave_nf_180 ip_arria10_e1sg_altera_avalon_onchip_memory2_180 ip_arria10_e1sg_altera_mm_interconnect_180 ip_arria10_e1sg_altera_reset_controller_180 ip_arria10_e1sg_altera_emif_arch_nf_180 ip_arria10_e1sg_altera_emif_180 ip_arria10_e1sg_altera_avalon_mm_bridge_180 ip_arria10_e1sg_altera_merlin_slave_translator_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_170 ip_arria10_e1sg_altera_emif_cal_slave_nf_170 ip_arria10_e1sg_altera_avalon_onchip_memory2_170 ip_arria10_e1sg_altera_mm_interconnect_170 ip_arria10_e1sg_altera_reset_controller_170 ip_arria10_e1sg_altera_emif_arch_nf_170 ip_arria10_e1sg_altera_emif_170 ip_arria10_e1sg_altera_avalon_mm_bridge_170 ip_arria10_e1sg_altera_merlin_slave_translator_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_ddr4_8g_2400.qip
+ ip_arria10_e1sg_ddr4_8g_2400.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qsys
index e6d718357b..c2ee5866f9 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qsys
@@ -160,7 +160,7 @@
<module
name="ddr4_inst"
kind="altera_emif"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/README.txt b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
index cfe2a2a2d8..6db25b6412 100755
--- a/libraries/technology/ip_arria10_e1sg/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
@@ -38,7 +38,7 @@ Contents:
The IP only needs to be generated with ./generate_ip.sh if it need to be modified, because the ip_arria10_fifo_*.vhd
directly instantiates the altera_mf component.
- The instantiation is copied manually from the generated/ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
+ The instantiation is copied manually from the ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
saved in the <fifo_name>.vhd file. So then the MegaWizard vhd file is overwritten, but that is fine because it is
no longer needed, it could easily be derived from the original in $UNB and it is still as a previous verion in SVN.
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
index 0a36be76c2..99b5070d9b 100755
--- a/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
@@ -33,13 +33,13 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_e1sg_fifo_*.vhd directly instantiates
# the FIFO altera_mf component.
-# The instantiation is copied manually from the generated/ip_arria10_e1sg_ram_*/fifo_140/sim/ip_arria10_e1sg_fifo_*.vhd.
+# The instantiation is copied manually from the ip_arria10_e1sg_ram_*/fifo_140/sim/ip_arria10_e1sg_fifo_*.vhd.
# It appears that the altera_mf FIFO component for Arria10 can be synthesized similar as how it worked for Stratix IV,
# it is not necessary to use the generated qip file.
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.qsys b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.qsys
index c32f172ac8..b3b1e81c48 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.qsys
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.qsys
@@ -71,7 +71,7 @@
<module
name="ip_arria10_fifo_dc"
kind="fifo"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.qsys b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.qsys
index fa9a47f210..1bf9442eec 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.qsys
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.qsys
@@ -71,7 +71,7 @@
<module
name="ip_arria10_fifo_dc_mixed_widths"
kind="fifo"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.qsys b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.qsys
index 7126359e3d..a695a2c1f1 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.qsys
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.qsys
@@ -69,7 +69,7 @@
<module
name="ip_arria10_fifo_sc"
kind="fifo"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
index 381c1944ae..542532efc5 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
index 6bac379b60..c5d3230359 100755
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index 43fae1307c..63faeffb57 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_asmi_parallel
-hdl_library_clause_name = ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180
+hdl_library_clause_name = ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_asmi_parallel_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_asmi_parallel_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_asmi_parallel.qip
+ ip_arria10_e1sg_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/ip_arria10_e1sg_asmi_parallel.qsys b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/ip_arria10_e1sg_asmi_parallel.qsys
index 459e8dd290..7cd26610f9 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/ip_arria10_e1sg_asmi_parallel.qsys
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/ip_arria10_e1sg_asmi_parallel.qsys
@@ -144,7 +144,7 @@
<module
name="asmi_parallel_0"
kind="altera_asmi_parallel"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
index 71a2b64c03..758af045ba 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
index fdc94c04b3..f9d585f8bb 100755
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index 90a4be835a..dd59deef2f 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_remote_update
-hdl_library_clause_name = ip_arria10_e1sg_remote_update_altera_remote_update_180
+hdl_library_clause_name = ip_arria10_e1sg_remote_update_altera_remote_update_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_remote_update_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_remote_update_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_remote_update.qip
+ ip_arria10_e1sg_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/ip_arria10_e1sg_remote_update.qsys b/libraries/technology/ip_arria10_e1sg/flash/remote_update/ip_arria10_e1sg_remote_update.qsys
index 122c6cd3dc..566f27ac6d 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/ip_arria10_e1sg_remote_update.qsys
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/ip_arria10_e1sg_remote_update.qsys
@@ -113,7 +113,7 @@
<module
name="remote_update_0"
kind="altera_remote_update"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
index 6f767532c6..dbdd811b48 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
index 739ce3f27e..a64d398529 100755
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index e3acc9f80d..bd4e4eff0a 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_fractional_pll_clk125
-hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_fractional_pll_clk125.qip
+ ip_arria10_e1sg_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qsys b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qsys
index d26f152267..5d978f4e94 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qsys
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qsys
@@ -161,7 +161,7 @@
<module
name="xcvr_fpll_a10_0"
kind="altera_xcvr_fpll_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
index 5c8674a583..46788a5560 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
index b5aa729588..10802670a7 100755
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index 7d8bf1759b..0b2de2be9b 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_fractional_pll_clk200
-hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_fractional_pll_clk200.qip
+ ip_arria10_e1sg_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qsys b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qsys
index 9ca6a9ba35..9d07e994b9 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qsys
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qsys
@@ -141,7 +141,7 @@
<module
name="xcvr_fpll_a10_0"
kind="altera_xcvr_fpll_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
index 1809358e9c..c775402d02 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_mac_10g.qip
+ ip_arria10_mac_10g.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
index afd8e94094..311722c106 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_mac_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
index 2cfec0ecc4..510c550c2c 100755
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2a" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index 7b92d3e261..8e576bcb2a 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_mac_10g
-hdl_library_clause_name = ip_arria10_e1sg_mac_10g_alt_em10g32_180
+hdl_library_clause_name = ip_arria10_e1sg_mac_10g_alt_em10g32_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_alt_em10g32_180
+hdl_lib_uses_sim = ip_arria10_e1sg_alt_em10g32_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
@@ -19,7 +19,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_mac_10g.qip
+ ip_arria10_e1sg_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/ip_arria10_e1sg_mac_10g.qsys b/libraries/technology/ip_arria10_e1sg/mac_10g/ip_arria10_e1sg_mac_10g.qsys
index 197ff78c07..5f0f03560f 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/ip_arria10_e1sg_mac_10g.qsys
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/ip_arria10_e1sg_mac_10g.qsys
@@ -226,7 +226,7 @@
<module
name="alt_em10g32_0"
kind="alt_em10g32"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="ANLG_VOLTAGE" value="1_0V" />
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
index 67f2e7f33e..bd817b8d2c 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
@@ -29,11 +29,11 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mult_add4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap ip_arria10_e1sg_mult_add4 ./work/
-vmap altera_mult_add_180 ./work/
+vmap altera_mult_add_170 ./work/
- vcom "$IP_DIR/../altera_mult_add_180/sim/ip_arria10_e1sg_mult_add4_altera_mult_add_180_dl6xbqi.vhd" -work altera_mult_add_180
+ vcom "$IP_DIR/../altera_mult_add_170/sim/ip_arria10_e1sg_mult_add4_altera_mult_add_170_dl6xbqi.vhd" -work altera_mult_add_170
vcom "$IP_DIR/ip_arria10_e1sg_mult_add4.vhd" -work ip_arria10_e1sg_mult_add4
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
index b52b5b14f7..7e679ec72f 100755
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4.qsys b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4.qsys
index 5cbdca8d07..833254f3e0 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4.qsys
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4.qsys
@@ -88,7 +88,7 @@
<module
name="mult_add_0"
kind="altera_mult_add"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="accum_direction" value="ADD" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
index 41b87622bf..4af0090eb6 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
index 310c756aee..7f651810ba 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index 0dd4c8210f..29c2cd4a06 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r.qip
+ ip_arria10_e1sg_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qsys
index d35d88f6c0..bfd82d2a4e 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qsys
@@ -342,7 +342,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
index 32a75009b8..fa707de56d 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
index 0102778d11..0ecdbd7fef 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index 37eab001c9..adcef5d58c 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_12
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r_12.qip
+ ip_arria10_e1sg_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qsys
index 65d72ddf0c..7a766f54c3 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qsys
@@ -365,7 +365,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
index 9cc7830fe8..6c29765871 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
index 58b28fabec..32c3254360 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index 80f43504e4..84069a7a0d 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_24
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r_24.qip
+ ip_arria10_e1sg_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qsys
index bf0575a0f0..8a5f4c9e7b 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qsys
@@ -365,7 +365,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
index 4a869f57e2..c14dae50ea 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
index 1bb64ac723..3240ee8311 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
index 8cf820104d..72f4164679 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_3
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,4 +16,9 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r_3.qip
+ ip_arria10_e1sg_phy_10gbase_r_3.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_phy_10gbase_r_3.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys
index 896e306c1e..8eebf9a668 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys
@@ -362,7 +362,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
index 4f4b143abd..0d32e10667 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
index ee4b74eceb..445f2fed57 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index 6fd79d3c85..40308d30b6 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_4
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r_4.qip
+ ip_arria10_e1sg_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qsys
index 1b79db2c90..bcc15326c1 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qsys
@@ -365,7 +365,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
index f9487e1a4f..0e3facb298 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
index c0fc1047af..552a7a512e 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index 78002d0526..a439f350cf 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_48
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r_48.qip
+ ip_arria10_e1sg_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qsys
index 8f2f6de609..78c428793e 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qsys
@@ -365,7 +365,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
index 643d6d4096..5f91ef1076 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
index a00ef44c62..17e6673b38 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index 80efe2ac97..4be4605015 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_pll_clk125
-hdl_library_clause_name = ip_arria10_e1sg_pll_clk125_altera_iopll_180
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk125_altera_iopll_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_pll_clk125.qip
+ ip_arria10_e1sg_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/ip_arria10_e1sg_pll_clk125.qsys b/libraries/technology/ip_arria10_e1sg/pll_clk125/ip_arria10_e1sg_pll_clk125.qsys
index 4ec5c79a3e..55d16c8d49 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/ip_arria10_e1sg_pll_clk125.qsys
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/ip_arria10_e1sg_pll_clk125.qsys
@@ -122,7 +122,7 @@
<module
name="iopll_0"
kind="altera_iopll"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="gui_active_clk" value="false" />
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
index 281a4c3d46..70a4ab66a1 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
index cf60d4df54..33378d48f5 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index d81c14c199..214a794d79 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_pll_clk200
-hdl_library_clause_name = ip_arria10_e1sg_pll_clk200_altera_iopll_180
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk200_altera_iopll_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_pll_clk200.qip
+ ip_arria10_e1sg_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/ip_arria10_e1sg_pll_clk200.qsys b/libraries/technology/ip_arria10_e1sg/pll_clk200/ip_arria10_e1sg_pll_clk200.qsys
index c3f3936e0c..f835c769ae 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/ip_arria10_e1sg_pll_clk200.qsys
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/ip_arria10_e1sg_pll_clk200.qsys
@@ -106,7 +106,7 @@
<module
name="iopll_0"
kind="altera_iopll"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="gui_active_clk" value="false" />
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
index 278ea6499a..6072afd658 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk25.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
index 525783f424..ef4a1a8184 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index c5e5ebeb0a..0c91441dd8 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_pll_clk25
-hdl_library_clause_name = ip_arria10_e1sg_pll_clk25_altera_iopll_180
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk25_altera_iopll_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_pll_clk25.qip
+ ip_arria10_e1sg_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/ip_arria10_e1sg_pll_clk25.qsys b/libraries/technology/ip_arria10_e1sg/pll_clk25/ip_arria10_e1sg_pll_clk25.qsys
index 3665b4c978..e209c00924 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/ip_arria10_e1sg_pll_clk25.qsys
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/ip_arria10_e1sg_pll_clk25.qsys
@@ -122,7 +122,7 @@
<module
name="iopll_0"
kind="altera_iopll"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="gui_active_clk" value="false" />
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
index 36568c9bf3..14b82a90c7 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_xgmii_mac_clocks.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
index 37e803de61..77f31d835c 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index 927abcb665..4f77d20d79 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_pll_xgmii_mac_clocks
-hdl_library_clause_name = ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
+ ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys
index 74baeb3555..3a2a961e1b 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys
@@ -117,7 +117,7 @@
<module
name="xcvr_fpll_a10_0"
kind="altera_xcvr_fpll_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
diff --git a/libraries/technology/ip_arria10_e1sg/ram/README.txt b/libraries/technology/ip_arria10_e1sg/ram/README.txt
index a9fe41102a..24ad4ab94e 100755
--- a/libraries/technology/ip_arria10_e1sg/ram/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/ram/README.txt
@@ -32,7 +32,7 @@ Contents:
if it need to be modified, because the ip_arria10_ram_*.vhd directly instantiates the altera_syncram component.
- The instantiation is copied manually from the generated/ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
+ The instantiation is copied manually from the ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
diff --git a/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
index a1a766d44d..86a387538b 100755
--- a/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
@@ -33,13 +33,13 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_e1sg_ram_*.vhd directly instantiates
# the altera_syncram component.
-# The instantiation is copied manually from the generated/ip_arria10_e1sg_ram_*/ram_2port_140/sim/ip_arria10_e1sg_ram_*.vhd.
+# The instantiation is copied manually from the ip_arria10_e1sg_ram_*/ram_2port_140/sim/ip_arria10_e1sg_ram_*.vhd.
# It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
# that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg
index 84cf6b8216..11a6f46151 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg
@@ -22,11 +22,3 @@ test_bench_files =
[quartus_project_file]
-
-[generate_ip_libs]
-qsys-generate_ip_files =
- ip_arria10_e1sg_ram_crwk_crw.qsys
- ip_arria10_e1sg_ram_crw_crw.qsys
- ip_arria10_e1sg_ram_cr_cw.qsys
- ip_arria10_e1sg_ram_r_w.qsys
-
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.qsys
index c41f1aa04c..e6b4c25eb2 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.qsys
@@ -67,7 +67,7 @@
<module
name="ram_2port_0"
kind="ram_2port"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
index 3baa3a14e0..5f5dcb6d0e 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
@@ -99,7 +99,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e1sg_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e1sg_ram_cr_cw/ram_2port_140/sim/ip_arria10_e1sg_ram_cr_cw_ram_2port_140_72tpmcy.vhd
+ -- Copied from ip_arria10_e1sg_ram_cr_cw/ram_2port_140/sim/ip_arria10_e1sg_ram_cr_cw_ram_2port_140_72tpmcy.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.qsys
index 879e267780..86b7dccc80 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.qsys
@@ -70,7 +70,7 @@
<module
name="ram_2port_0"
kind="ram_2port"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
index bd96396a6d..509a4f5586 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
@@ -115,7 +115,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e1sg_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e1sg_ram_crw_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
+ -- Copied from ip_arria10_e1sg_ram_crw_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.qsys
index db1029e58f..3d55a54be3 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.qsys
@@ -69,7 +69,7 @@
<module
name="ip_arria10_ram_crwk_crw"
kind="ram_2port"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
index be1ddf85cd..d07aec2232 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
@@ -95,7 +95,7 @@ ARCHITECTURE SYN OF ip_arria10_e1sg_ram_crwk_crw IS
BEGIN
- -- Copied from generated/ip_arria10_e1sg_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
+ -- Copied from ip_arria10_e1sg_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.qsys
index 7b9ab891b0..989d8e074e 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.qsys
@@ -66,7 +66,7 @@
<module
name="ram_2port_0"
kind="ram_2port"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
index 3b9707e7e5..4abdf45bd9 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
@@ -96,7 +96,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e1sg_ram_r_w : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e1sg_ram_r_w/ram_2port_140/sim/ip_arria10_e1sg_ram_r_w_ram_2port_140_hukd7xi.vhd
+ -- Copied from ip_arria10_e1sg_ram_r_w/ram_2port_140/sim/ip_arria10_e1sg_ram_r_w_ram_2port_140_hukd7xi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
index 94b9083df4..9718b9d6eb 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
@@ -29,11 +29,11 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/temp_sense/generated/sim"
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/temp_sense/generated/sim"
-vmap altera_temp_sense_180 ./work/
+vmap altera_temp_sense_170 ./work/
- vlog "$IP_DIR/../altera_temp_sense_180/sim/altera_temp_sense.v" -work altera_temp_sense_180
+ vlog "$IP_DIR/../altera_temp_sense_170/sim/altera_temp_sense.v" -work altera_temp_sense_170
vcom "$IP_DIR/ip_arria10_e1sg_temp_sense.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
index be991c110a..ab8fbc6a74 100755
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index ee2d261c67..3a72010b5e 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_temp_sense
-hdl_library_clause_name = ip_arria10_e1sg_temp_sense_altera_temp_sense_180
+hdl_library_clause_name = ip_arria10_e1sg_temp_sense_altera_temp_sense_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
@@ -15,9 +15,4 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_e1sg_temp_sense.qip
-
-[generate_ip_libs]
-qsys-generate_ip_files =
- ip_arria10_e1sg_temp_sense.qsys
-
+quartus_qip_files = ip_arria10_e1sg_temp_sense.qip
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/ip_arria10_e1sg_temp_sense.qsys b/libraries/technology/ip_arria10_e1sg/temp_sense/ip_arria10_e1sg_temp_sense.qsys
index 7b8c083b6e..5b698e50ad 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/ip_arria10_e1sg_temp_sense.qsys
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/ip_arria10_e1sg_temp_sense.qsys
@@ -71,7 +71,7 @@
<module
name="temp_sense_0"
kind="altera_temp_sense"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
index 63f8171a4b..e98b88b1eb 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
index c4af138a6c..12de447a12 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index 6320ca76b9..b5d432d88e 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_pll_10g
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_atx_pll_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_atx_pll_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,9 +16,4 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_pll_10g.qip
-
-[generate_ip_libs]
-qsys-generate_ip_files =
- ip_arria10_e1sg_transceiver_pll_10g.qsys
-
+ ip_arria10_e1sg_transceiver_pll_10g.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qsys
index 10bfe00209..43c9588dc0 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qsys
@@ -145,7 +145,7 @@
<module
name="xcvr_atx_pll_a10_0"
kind="altera_xcvr_atx_pll_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
index 01c8d37521..678140bfc2 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_1.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
index bdf2f728e8..17e84e3a49 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 74d008c0b0..e8426aa936 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_1
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_1.qip
+ ip_arria10_e1sg_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qsys
index f3228f1b49..cb5c62e4f1 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qsys
@@ -146,7 +146,7 @@
<module
name="xcvr_reset_control_0"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="1" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
index b4cc6457dc..8fb9880e95 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
index 9dc526c3bb..db50fda3d1 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index 2e3128afbe..da3c791351 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_12
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_12.qip
+ ip_arria10_e1sg_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qsys
index 7954d06890..d2eed5f40e 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qsys
@@ -146,7 +146,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="12" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
index 21b8cb5187..97fd1d1678 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
index ab440cf7a0..761d94c869 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index 0ecb1f7021..d6ecda1740 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_24
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_24.qip
+ ip_arria10_e1sg_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qsys
index 40028b0f20..b9c81b794a 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qsys
@@ -146,7 +146,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="24" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
index aed0f2bedc..22bbf7ef66 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
index db457e873c..ed92ce368e 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
index 38bd151d83..c4267c2954 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_3
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,4 +16,4 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_3.qip
+ ip_arria10_e1sg_transceiver_reset_controller_3.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys
index 786d71495f..fad8e19b9a 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys
@@ -143,7 +143,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="3" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
index a4e0bc1b15..bc16814faf 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
index cb635dde75..ad1d84d8d1 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index 16d8fe3686..83fd058fc8 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_4
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_4.qip
+ ip_arria10_e1sg_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qsys
index d05fec4afa..5e62c4549a 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qsys
@@ -146,7 +146,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="4" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
index 7ef9776084..5017d0f346 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
index 9aac11c07a..81f461f352 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index 063f94d4bf..256927382b 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_48
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_48.qip
+ ip_arria10_e1sg_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qsys
index 4878d28ba3..c755b0dcca 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qsys
@@ -146,7 +146,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="48" />
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
index fcc8f3f3cb..835fedcf83 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_gx.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
index e949f73d02..91152f6cd8 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index 78f0ff306f..fc7ebd16d8 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_tse_sgmii_gx
-hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180
+hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170
hdl_lib_uses_synth = common
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_eth_tse_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_eth_tse_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_tse_sgmii_gx.qip
+ ip_arria10_e1sg_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qsys b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qsys
index 2756d70a1d..748cbd7579 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qsys
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qsys
@@ -283,7 +283,7 @@
<module
name="eth_tse_0"
kind="altera_eth_tse"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
index 28a6acf47c..d57ca28bd9 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_lvds.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
index 27c0af99a9..759e004252 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index 2a4918678b..ab4006d191 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_tse_sgmii_lvds
-hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180
+hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170
hdl_lib_uses_synth = common
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_eth_tse_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_eth_tse_170
hdl_lib_technology = ip_arria10_e1sg
@@ -18,7 +18,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_tse_sgmii_lvds.qip
+ ip_arria10_e1sg_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qsys b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qsys
index 5bffe555b9..51fe979317 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qsys
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qsys
@@ -199,7 +199,7 @@
<module
name="eth_tse_0"
kind="altera_eth_tse"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
index 833e8341c5..59e6164425 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
@@ -29,19 +29,19 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/voltage_sense/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap ip_arria10_e1sg_voltage_sense ./work/
-vmap altera_voltage_sensor_180 ./work/
-vmap altera_voltage_sensor_control_180 ./work/
-vmap altera_voltage_sensor_sample_store_180 ./work/
+vmap altera_voltage_sensor_170 ./work/
+vmap altera_voltage_sensor_control_170 ./work/
+vmap altera_voltage_sensor_sample_store_170 ./work/
- vlog -sv "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/altera_voltage_sensor_control.sv" -work altera_voltage_sensor_control_180
- vlog -sv "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/voltage_sensor_avalon_controlr.sv" -work altera_voltage_sensor_control_180
- vlog -sv "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/voltage_sensor_wrapper.sv" -work altera_voltage_sensor_control_180
- vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store.sv" -work altera_voltage_sensor_sample_store_180
- vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store_ram.sv" -work altera_voltage_sensor_sample_store_180
- vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store_register.sv" -work altera_voltage_sensor_sample_store_180
- vcom "$IP_DIR/../altera_voltage_sensor_180/sim/ip_arria10_e1sg_voltage_sense_altera_voltage_sensor_180_hjr63vq.vhd" -work altera_voltage_sensor_180
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/altera_voltage_sensor_control.sv" -work altera_voltage_sensor_control_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/voltage_sensor_avalon_controlr.sv" -work altera_voltage_sensor_control_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/voltage_sensor_wrapper.sv" -work altera_voltage_sensor_control_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store.sv" -work altera_voltage_sensor_sample_store_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store_ram.sv" -work altera_voltage_sensor_sample_store_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store_register.sv" -work altera_voltage_sensor_sample_store_170
+ vcom "$IP_DIR/../altera_voltage_sensor_170/sim/ip_arria10_e1sg_voltage_sense_altera_voltage_sensor_170_hjr63vq.vhd" -work altera_voltage_sensor_170
vcom "$IP_DIR/ip_arria10_e1sg_voltage_sense.vhd" -work ip_arria10_e1sg_voltage_sense
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
index 2aa4ddd7b1..df1e1b6ff7 100755
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index 5e1e7faff9..150159a14e 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_voltage_sense
-hdl_library_clause_name = ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180
+hdl_library_clause_name = ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
@@ -16,7 +16,7 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_e1sg_voltage_sense.qip
+quartus_qip_files = ip_arria10_e1sg_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/ip_arria10_e1sg_voltage_sense.qsys b/libraries/technology/ip_arria10_e1sg/voltage_sense/ip_arria10_e1sg_voltage_sense.qsys
index a1fed7433e..0785279882 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/ip_arria10_e1sg_voltage_sense.qsys
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/ip_arria10_e1sg_voltage_sense.qsys
@@ -132,7 +132,7 @@
<module
name="voltage_sensor_0"
kind="altera_voltage_sensor"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
index 53c76e2b5e..7ae5ccdb01 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
index 66d47d1ae3..109d6d33f6 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_clkbuf_global.qip
+ ip_arria10_e3sge3_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
index 3e33649f60..c9a33bbdfc 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_complex_mult.qip
+ ip_arria10_complex_mult.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
index 7692d23a29..57832897c9 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/complex_mult/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
index 28ead31eed..a9a34dbda0 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_complex_mult.qip
+ ip_arria10_e3sge3_complex_mult.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
index 4a9ef46272..aa2dd948bc 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddio/generated/"
+ set IP_DIR "$env(HDL_BUILD_DIR)/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
index d053102ed7..5c041edb86 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
@@ -18,8 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_ddio_in_1.qip
- generated/ip_arria10_e3sge3_ddio_out_1.qip
+ ip_arria10_e3sge3_ddio_in_1.qip
+ ip_arria10_e3sge3_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
index 6d0ae35297..f9daedf909 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
index 8c69969d8b..960d695d93 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
index 20a085ab64..dd9a5269ec 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_ddr4_4g_1600.qip
+ ip_arria10_e3sge3_ddr4_4g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
index c7213abdc7..4958df3351 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
index a7fa910541..9ee3836145 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
index c23aafef03..e973cfc298 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_ddr4_4g_2000.qip
+ ip_arria10_e3sge3_ddr4_4g_2000.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
index b9cad2a73e..f1b453f200 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
index ced3c0a509..04c2a8b4be 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
index 29715012a3..f8c58abd73 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_ddr4_8g_1600.qip
+ ip_arria10_e3sge3_ddr4_8g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
index 3cefb93ecc..ce6a73617c 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
index 80794294d5..aae9b7d9c1 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
index a433ee5522..61b0187261 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_ddr4_8g_2400.qip
+ ip_arria10_e3sge3_ddr4_8g_2400.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
index cfe2a2a2d8..6db25b6412 100755
--- a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
@@ -38,7 +38,7 @@ Contents:
The IP only needs to be generated with ./generate_ip.sh if it need to be modified, because the ip_arria10_fifo_*.vhd
directly instantiates the altera_mf component.
- The instantiation is copied manually from the generated/ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
+ The instantiation is copied manually from the ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
saved in the <fifo_name>.vhd file. So then the MegaWizard vhd file is overwritten, but that is fine because it is
no longer needed, it could easily be derived from the original in $UNB and it is still as a previous verion in SVN.
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
index 9ba8d5f30f..76d5339e03 100755
--- a/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
@@ -33,7 +33,7 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_e3sge3_fifo_*.vhd directly instantiates
# the FIFO altera_mf component.
-# The instantiation is copied manually from the generated/ip_arria10_e3sge3_ram_*/fifo_140/sim/ip_arria10_e3sge3_fifo_*.vhd.
+# The instantiation is copied manually from the ip_arria10_e3sge3_ram_*/fifo_140/sim/ip_arria10_e3sge3_fifo_*.vhd.
# It appears that the altera_mf FIFO component for Arria10 can be synthesized similar as how it worked for Stratix IV,
# it is not necessary to use the generated qip file.
#
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
index c48cca790f..dca4f15724 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
vmap ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
index 08a9862f73..8158007cdb 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_asmi_parallel.qip
+ ip_arria10_e3sge3_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
index 995703d181..74015b629d 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_core_151 ./work/
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
index ee60d547c8..d86f360f53 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_remote_update.qip
+ ip_arria10_e3sge3_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
index 26d0ca325d..7e094e9376 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
index 70f593d6bb..3206621e21 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_fractional_pll_clk125.qip
+ ip_arria10_e3sge3_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
index 0383174c3b..c0daa81c16 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
index f150a9eff0..8d98ad13a4 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_fractional_pll_clk200.qip
+ ip_arria10_e3sge3_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
index 1809358e9c..c775402d02 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_mac_10g.qip
+ ip_arria10_mac_10g.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
index 23647961fc..5567b55fb3 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated/sim"
-set IP_TBDIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_TBDIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
index 9d03c8de48..1388ee04dd 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
[modelsim_project_file]
@@ -19,7 +19,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_mac_10g.qip
+ ip_arria10_e3sge3_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
index e3aa9bf13c..9f2c5442d7 100644
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mult_add4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
index c58d590f77..e27cf86d7f 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
index d6999a29ee..8e7bc5b458 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_phy_10gbase_r.qip
+ ip_arria10_e3sge3_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
index 7b2e6c3379..4d2d833dae 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
index 2c483639f5..1f8b843ee0 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_phy_10gbase_r_12.qip
+ ip_arria10_e3sge3_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
index 86a711170a..26ba984cb5 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
index 5c2b3e6e59..189f755402 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_phy_10gbase_r_24.qip
+ ip_arria10_e3sge3_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
index 52f79da7b2..76743709b4 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
index 94e1849d1e..16bfd7165f 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_phy_10gbase_r_4.qip
+ ip_arria10_e3sge3_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
index 82b3ff12a7..f80ddb5a8f 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
index 4ea8a12229..7c697c6572 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_phy_10gbase_r_48.qip
+ ip_arria10_e3sge3_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
index 71564250c5..cdad30ae36 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
index 3e61b19f5b..ed9baef7c2 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_pll_clk125.qip
+ ip_arria10_e3sge3_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
index 5418dc79a1..1e38e5900f 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
index 736f98fb0c..ca6a0c6d8b 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_pll_clk200.qip
+ ip_arria10_e3sge3_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
index 07c26baa46..fed8a5ff9a 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk25/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
index 7ddd6210a7..77d805a510 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_pll_clk25.qip
+ ip_arria10_e3sge3_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
index 4e80e99645..10417d22ca 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
index 3241762cfd..bb1bcd9a4f 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_pll_xgmii_mac_clocks.qip
+ ip_arria10_e3sge3_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/README.txt b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
index a9fe41102a..24ad4ab94e 100755
--- a/libraries/technology/ip_arria10_e3sge3/ram/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
@@ -32,7 +32,7 @@ Contents:
if it need to be modified, because the ip_arria10_ram_*.vhd directly instantiates the altera_syncram component.
- The instantiation is copied manually from the generated/ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
+ The instantiation is copied manually from the ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
index a823b95804..502af4187c 100755
--- a/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
@@ -33,7 +33,7 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_e3sge3_ram_*.vhd directly instantiates
# the altera_syncram component.
-# The instantiation is copied manually from the generated/ip_arria10_e3sge3_ram_*/ram_2port_140/sim/ip_arria10_e3sge3_ram_*.vhd.
+# The instantiation is copied manually from the ip_arria10_e3sge3_ram_*/ram_2port_140/sim/ip_arria10_e3sge3_ram_*.vhd.
# It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
# that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
#
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
index 98c7b0550c..a0b6fedf0b 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
@@ -99,7 +99,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e3sge3_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e3sge3_ram_cr_cw/ram_2port_140/sim/ip_arria10_e3sge3_ram_cr_cw_ram_2port_140_72tpmcy.vhd
+ -- Copied from ip_arria10_e3sge3_ram_cr_cw/ram_2port_140/sim/ip_arria10_e3sge3_ram_cr_cw_ram_2port_140_72tpmcy.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
index fc9faba964..e5741a8cbe 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
@@ -115,7 +115,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e3sge3_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e3sge3_ram_crw_crw/ram_2port_140/sim/ip_arria10_e3sge3_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
+ -- Copied from ip_arria10_e3sge3_ram_crw_crw/ram_2port_140/sim/ip_arria10_e3sge3_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
index 8104431000..1656f25328 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
@@ -95,7 +95,7 @@ ARCHITECTURE SYN OF ip_arria10_e3sge3_ram_crwk_crw IS
BEGIN
- -- Copied from generated/ip_arria10_e3sge3_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e3sge3_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
+ -- Copied from ip_arria10_e3sge3_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e3sge3_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
index 00b622447c..033fa02fbf 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
@@ -96,7 +96,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e3sge3_ram_r_w : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e3sge3_ram_r_w/ram_2port_140/sim/ip_arria10_e3sge3_ram_r_w_ram_2port_140_hukd7xi.vhd
+ -- Copied from ip_arria10_e3sge3_ram_r_w/ram_2port_140/sim/ip_arria10_e3sge3_ram_r_w_ram_2port_140_hukd7xi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
index f863a70074..350a3674c8 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/temp_sense/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
index 04b2dc9836..8f96a5f7bb 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
@@ -15,7 +15,7 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_e3sge3_temp_sense.qip
+quartus_qip_files = ip_arria10_e3sge3_temp_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
index 806454fac6..e16ab1bb84 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
index d128486395..afd34643a6 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_pll_10g.qip
+ ip_arria10_e3sge3_transceiver_pll_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
index fd40ff8721..824d03bc0c 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
index df77648d5b..f6fbacfad7 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_reset_controller_1.qip
+ ip_arria10_e3sge3_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
index dda89b41c6..b674c73aa8 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
index 1174e7891a..a0f8d7cfba 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_reset_controller_12.qip
+ ip_arria10_e3sge3_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
index 54f87c5f3f..d9cbccb139 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
index 5568315590..a1b6720a80 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_reset_controller_24.qip
+ ip_arria10_e3sge3_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
index 8ad00f7882..f2d0fa88e7 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
index e5bb6bb856..79a61988aa 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_reset_controller_4.qip
+ ip_arria10_e3sge3_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
index e77af624de..84ad7eb848 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
index 9185b8febc..fddd592bd0 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_reset_controller_48.qip
+ ip_arria10_e3sge3_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
index 38368d2110..216ad6395e 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
index a2022287b2..9745670627 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_tse_sgmii_gx.qip
+ ip_arria10_e3sge3_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
index 41c63a1ae3..add9457301 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
index 5665f5db4c..1f2692dc30 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_tse_sgmii_lvds.qip
+ ip_arria10_e3sge3_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
index 8b61b7eb88..090df9c5c9 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/voltage_sense/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
index 63946dd01b..77801114c9 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_e3sge3_voltage_sense.qip
+quartus_qip_files = ip_arria10_e3sge3_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
index 2690e54a37..59ee3539ca 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
@@ -23,7 +23,8 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
# Get the memory model fro the uphy_4g_* from the ip_stratixiv_ddr3_uphy_4g_800_master example design
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
+#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_example_design
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
index ab5bd65220..0cba85661d 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
index c14c1911ff..c62e33e654 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
index 31f0359c75..56142bcee0 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
index 1ad73c93b5..0130afea23 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
index 7e5924ab38..aae001963a 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
index 0d39d81f1f..adec7b0329 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ ip_stratixiv_ddr3_uphy_4g_800_master.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
index 3cd4b20618..100507af6a 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
index 6a6e860295..96244d1526 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
index 46a856b9a0..8391e40fd9 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ ip_stratixiv_ddr3_uphy_4g_800_slave.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
index 1d878a2a3c..84678948ce 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
index e0786cddeb..6a06571581 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
index c28bd93dd1..e59e8b5ca0 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
index 962b26b7f9..ca5ef73e86 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
index 00f508ab33..755278c849 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
index 6f9285a234..806cd417be 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.qip
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
index 33c1e12bf7..8133ccc7f4 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
@@ -24,7 +24,7 @@
# file msim_setup.tcl.
# tr_xaui is the first module I did this for.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_mac_10g_sim"
#vlib ./work/ ;# Assume library work already exists
#vmap work ./work/
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho
index a5b8a809ae..a839c012dc 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho
@@ -212,7 +212,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout : STD_LOGIC;
@@ -222,7 +222,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout : STD_LOGIC;
@@ -393,7 +393,7 @@
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_390q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_389q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_388q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
- altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_386q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_385q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_421q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout;
@@ -404,7 +404,7 @@
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_380q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_379q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_378q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
- altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_376q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_375q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_420q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout;
@@ -542,7 +542,7 @@
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_321q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_320q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_319q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
- altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_318q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_318q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_317q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_316q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_352q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout;
@@ -553,7 +553,7 @@
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_311q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_310q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_309q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
- altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_308q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_308q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_307q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_306q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_351q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout;
@@ -605,7 +605,7 @@
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout <= in_data(50) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_374q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout <= in_data(49) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_375q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout <= in_data(48) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_376q;
- wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(47) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(47) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout <= in_data(46) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_378q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout <= in_data(45) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_379q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout <= in_data(44) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_380q;
@@ -615,7 +615,7 @@
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout <= in_data(40) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_384q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout <= in_data(39) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_385q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout <= in_data(38) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_386q;
- wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(37) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(37) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout <= in_data(36) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_388q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout <= in_data(35) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_389q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout <= in_data(34) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_390q;
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho
index 73d05546f1..0126c6d7e7 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho
@@ -58,7 +58,7 @@
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q : STD_LOGIC := '0';
- SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_170q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q : STD_LOGIC := '0';
@@ -69,7 +69,7 @@
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q : STD_LOGIC := '0';
- SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_180q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_3_198q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_4_197q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_5_196q : STD_LOGIC := '0';
@@ -225,7 +225,7 @@
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q <= '0';
- altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_170q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q <= '0';
@@ -236,7 +236,7 @@
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q <= '0';
- altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_180q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_3_198q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_4_197q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_5_196q <= '0';
@@ -260,7 +260,7 @@
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_86m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_104m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_85m_dataout;
- altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_170q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_83m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_82m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_81m_dataout;
@@ -271,7 +271,7 @@
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_76m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_103m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_75m_dataout;
- altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_180q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_3_198q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_102m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_4_197q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_101m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_5_196q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_100m_dataout;
@@ -363,7 +363,7 @@
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_103m_dataout <= in_data(2) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_104m_dataout <= in_data(1) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_105m_dataout <= in_data(0) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_0_208q;
- wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout <= in_data(31) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_180q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout <= in_data(31) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_75m_dataout <= in_data(30) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_76m_dataout <= in_data(29) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_77m_dataout <= in_data(28) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_28_173q;
@@ -373,7 +373,7 @@
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_81m_dataout <= in_data(24) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_82m_dataout <= in_data(23) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_83m_dataout <= in_data(22) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q;
- wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout <= in_data(21) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout <= in_data(21) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_170q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_85m_dataout <= in_data(20) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_86m_dataout <= in_data(19) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_87m_dataout <= in_data(18) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_18_183q;
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho
index d84d0eb4fc..d630f56f5c 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho
@@ -285,7 +285,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout : STD_LOGIC;
@@ -295,7 +295,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout : STD_LOGIC;
@@ -885,7 +885,7 @@
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_327q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_326q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_325q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
- altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_324q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_324q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_323q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_322q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_367q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_223m_dataout;
@@ -896,7 +896,7 @@
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_317q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_316q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_315q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
- altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_314q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_314q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_313q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_312q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_366q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_222m_dataout;
@@ -933,7 +933,7 @@
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout <= in_data(60) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_528q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout <= in_data(59) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_529q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout <= in_data(58) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_530q;
- wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(57) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_531q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(57) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_531q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout <= in_data(56) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_532q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout <= in_data(55) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_533q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout <= in_data(54) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_534q;
@@ -943,7 +943,7 @@
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout <= in_data(50) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_538q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout <= in_data(49) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_539q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout <= in_data(48) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_540q;
- wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(47) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_541q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(47) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_541q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout <= in_data(46) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_542q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout <= in_data(45) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_543q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout <= in_data(44) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_544q;
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho
index 5f8525fbeb..324d483ebc 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho
@@ -212,7 +212,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout : STD_LOGIC;
@@ -222,7 +222,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout : STD_LOGIC;
@@ -415,7 +415,7 @@
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_399q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_398q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_397q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
- altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_395q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_394q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_393q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout;
@@ -426,7 +426,7 @@
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_389q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_388q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_387q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
- altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_385q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_384q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_383q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout;
@@ -570,7 +570,7 @@
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_327q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_326q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_325q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
- altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_324q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_324q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_323q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_322q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_321q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout;
@@ -581,7 +581,7 @@
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_317q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_316q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_315q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
- altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_314q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_314q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_313q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_312q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_311q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout;
@@ -620,7 +620,7 @@
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout <= in_data(59) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_383q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout <= in_data(58) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_384q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout <= in_data(57) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_385q;
- wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(56) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(56) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout <= in_data(55) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_387q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout <= in_data(54) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_388q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout <= in_data(53) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_389q;
@@ -630,7 +630,7 @@
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout <= in_data(49) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_393q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout <= in_data(48) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_394q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout <= in_data(47) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_395q;
- wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(46) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(46) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout <= in_data(45) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_397q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout <= in_data(44) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_398q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout <= in_data(43) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_399q;
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho
index 91c65f7c5c..feb85ddf87 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho
@@ -60,7 +60,7 @@
SIGNAL wire_nO_w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout : STD_LOGIC;
SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_177m_dataout : STD_LOGIC;
- SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_181m_dataout : STD_LOGIC;
SIGNAL wire_w_lg_reset258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_uav_readdatavalid257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -93,8 +93,8 @@
wire_nO_w51w(0) <= NOT altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q;
wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout <= wire_w_lg_uav_readdatavalid257w(0) WHEN av_read = '1' ELSE uav_waitrequest;
wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_177m_dataout <= altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q AND NOT((uav_readdatavalid AND altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q));
- wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_180m_dataout <= (wire_w_lg_uav_waitrequest255w(0) AND av_read) AND wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout;
- wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_181m_dataout <= wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_177m_dataout WHEN altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q = '1' ELSE wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_180m_dataout;
+ wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_170m_dataout <= (wire_w_lg_uav_waitrequest255w(0) AND av_read) AND wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout;
+ wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_181m_dataout <= wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_177m_dataout WHEN altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q = '1' ELSE wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_170m_dataout;
END RTL; --altera_merlin_master_translator_0001
--synopsys translate_on
diff --git a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
index da20f4a1a8..47e15241a4 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
@@ -25,7 +25,7 @@ quartus_vhdl_files =
quartus_sdc_files =
quartus_qip_files =
- generated/ip_stratixiv_mac_10g.qip
+ ip_stratixiv_mac_10g.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
index ed22b0d052..3318814203 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
@@ -27,7 +27,7 @@
# correct compile order).
# EK: The model files in phy_xaui_0_sim/ are suitable for all hard xaui IP variants.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_0_sim"
#vlib ./work/ ;# EK: Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
index 7eae3900cf..7e223040ac 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
@@ -27,7 +27,7 @@
# correct compile order). Bonus of this is also that there will be no errors
# when making all_mod without having run the XAUI megawizard first.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_soft_sim"
#vlib ./work/ ;# EK: Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
index 8f8916bf66..ac4ee7014d 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
@@ -33,7 +33,7 @@ quartus_vhdl_files =
quartus_sdc_files =
quartus_qip_files =
- generated/ip_stratixiv_phy_xaui_0.qip
+ ip_stratixiv_phy_xaui_0.qip
ip_stratixiv_phy_xaui_soft.qip
[generate_ip_libs]
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index 157235e48c..c73c25d07a 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -8,7 +8,7 @@ hdl_lib_disclose_library_clause_names =
ip_stratixiv_mac_10g ip_stratixiv_mac_10g_lib
ip_arria10_mac_10g ip_arria10_mac_10g_alt_em10g32_150
ip_arria10_e3sge3_mac_10g ip_arria10_e3sge3_mac_10g_alt_em10g32_151
- ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g_alt_em10g32_180
+ ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g_alt_em10g32_170
synth_files =
tech_mac_10g_component_pkg.vhd
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
index 2acea7c3c2..c41aa27748 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
@@ -21,7 +21,7 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_180;
+LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_170;
LIBRARY IEEE, technology_lib, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index 4f9aec4417..fccd070a50 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -52,7 +52,7 @@ PACKAGE tech_mac_10g_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Copied from entity $RADIOHDL_WORK/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
+ -- Copied from entity $HDL_BUILD_DIR/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
COMPONENT ip_stratixiv_mac_10g IS
PORT (
csr_clk_clk : in std_logic := '0'; -- csr_clk.clk
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 2b3f3f655d..f9ac504fb4 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -17,7 +17,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_mult ip_arria10_mult_lib
ip_arria10_complex_mult ip_arria10_complex_mult_altmult_complex_150
ip_arria10_complex_mult_rtl ip_arria10_complex_mult_rtl_lib
- ip_arria10_e1sg_complex_mult ip_arria10_e1sg_complex_mult_altmult_complex_180
+ ip_arria10_e1sg_complex_mult ip_arria10_e1sg_complex_mult_altmult_complex_170
ip_arria10_e3sge3_mult_add4 ip_arria10_e3sge3_mult_add4_lib
ip_arria10_e1sg_mult_add4 ip_arria10_e1sg_mult_add4_lib
ip_arria10_e1sg_mult_add2 ip_arria10_e1sg_mult_add2_lib
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index 6432cf385e..82975e8341 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -31,7 +31,7 @@ LIBRARY ip_stratixiv_mult_lib;
--LIBRARY ip_arria10_mult_lib;
--LIBRARY ip_arria10_mult_rtl_lib;
LIBRARY ip_arria10_complex_mult_altmult_complex_150;
-LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_180;
+LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_170;
LIBRARY ip_arria10_complex_mult_rtl_lib;
LIBRARY ip_arria10_complex_mult_rtl_canonical_lib;
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index c7b3d55035..4b047fa7c0 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -18,10 +18,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_pll_clk25 ip_arria10_e3sge3_pll_clk25_altera_iopll_151
ip_arria10_e3sge3_pll_clk125 ip_arria10_e3sge3_pll_clk125_altera_iopll_151
ip_arria10_e3sge3_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
- ip_arria10_e1sg_pll_clk200 ip_arria10_e1sg_pll_clk200_altera_iopll_180
- ip_arria10_e1sg_pll_clk25 ip_arria10_e1sg_pll_clk25_altera_iopll_180
- ip_arria10_e1sg_pll_clk125 ip_arria10_e1sg_pll_clk125_altera_iopll_180
- ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180
+ ip_arria10_e1sg_pll_clk200 ip_arria10_e1sg_pll_clk200_altera_iopll_170
+ ip_arria10_e1sg_pll_clk25 ip_arria10_e1sg_pll_clk25_altera_iopll_170
+ ip_arria10_e1sg_pll_clk125 ip_arria10_e1sg_pll_clk125_altera_iopll_170
+ ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170
synth_files =
tech_pll_component_pkg.vhd
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index df94261a83..5cdbbb6be1 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_clk125_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk125_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_180;
+LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_170;
ENTITY tech_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index adf88609a9..4eefc35b6d 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_pll_lib;
LIBRARY ip_arria10_pll_clk200_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk200_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_180;
+LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_170;
ENTITY tech_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index bfb242b469..2521432735 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
LIBRARY ip_stratixiv_pll_clk25_lib;
LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_180;
+LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_170;
ENTITY tech_pll_clk25 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index ca39909423..28f1fa3a1e 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -43,7 +43,7 @@ USE common_lib.common_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180;
+LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170;
ENTITY tech_pll_xgmii_mac_clocks IS
GENERIC (
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index 56d098e9b3..0a5b17d1d1 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -14,8 +14,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_tse_sgmii_gx ip_arria10_tse_sgmii_gx_altera_eth_tse_150
ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
ip_arria10_e3sge3_tse_sgmii_gx ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
- ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180
- ip_arria10_e1sg_tse_sgmii_gx ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180
+ ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170
+ ip_arria10_e1sg_tse_sgmii_gx ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170
synth_files =
tech_tse_component_pkg.vhd
diff --git a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
index 664f3f85ec..4512fe7d9e 100644
--- a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
@@ -28,8 +28,8 @@ USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180;
-LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180;
+LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170;
+LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170;
ENTITY tech_tse_arria10_e1sg IS
GENERIC (
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index 6671ba6f7e..456d59f72b 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -147,7 +147,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim/ip_arria10_tse_sgmii_lvds.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_tse_sgmii_lvds IS
PORT (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
@@ -198,7 +198,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim/ip_arria10_tse_sgmii_gx.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_gx.vhd
COMPONENT ip_arria10_tse_sgmii_gx IS
PORT (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
@@ -265,7 +265,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_e3sge3_tse_sgmii_lvds IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -316,7 +316,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
COMPONENT ip_arria10_e3sge3_tse_sgmii_gx IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -383,7 +383,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_e1sg_tse_sgmii_lvds IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -434,7 +434,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
COMPONENT ip_arria10_e1sg_tse_sgmii_gx IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
--
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