diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index e9680ed83e905cb146ba412cc8cd9aff312ea306..5274dbde5038d22a985445aa564845bc71fbf204 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -42,7 +42,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
$RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index 4e1e86e84b79b96955ab0bb1ca1a60f3a2fa8669..a9fe01c6998deaad4a2dae2b42b3fbc42d3e04fe 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -42,7 +42,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
$RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index a11a44ecae018119c132baa7eae352f93cdd70c8..e5201297eb0dd5bdb1b8f9573c6485339de21915 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -36,7 +36,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_test/doc/README b/boards/uniboard1/designs/unb1_test/doc/README
index bb6725a13e98bf9fdbede3945c84006410068d93..9eca9c326ae3ef0a160f23e4234264c9c77ca751 100644
--- a/boards/uniboard1/designs/unb1_test/doc/README
+++ b/boards/uniboard1/designs/unb1_test/doc/README
@@ -121,7 +121,7 @@ The 2nd tcl file can be created with Quartus. Here are the steps:
- generate the IP's by running: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
- Start synthesis in the Quartus GUI. Only the Analysis step!!
- Then in Quartus click: Tools/TclScripts.
- Open the Tcl file: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
+ Open the Tcl file: $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
Click Run.
- Then Continue synthesis with Fitter, or restart with Analysis.
- Copy the generated build/unb1_test_ddr_MB_I_II.qsf file to ./designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_MB_I_II_pins_constraints.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
index 67096db24e832cab2768d5d87d6e4cd704e2560a..9c83f47a8dd7256d547aaa95a00b8bc5b9a38fb8 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
@@ -41,8 +41,8 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- #$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
index b45e077994fae004797ae94ae77f3b8354ac97f6..14de6969547a38e650fe61774ee632b2e747c5c6 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
@@ -41,8 +41,8 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- #$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
index 984c18f3c3217156bc09c8df7abf3968dcf61fd8..64451014bed47872dd3176a43c4662a0b2dc3fcd 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
@@ -42,7 +42,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
index 0f81d335343749658dff77747959f472baeb44cf..48f3e6132c2271b31a7f22854a61ca3f39dbfe6c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
@@ -41,7 +41,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
index a3dc5f59d03db5ca26ed308fbc06c56a0f7f0256..87fbbf48a8a68f94e071d36b8d90e392ab569ec5 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
@@ -41,7 +41,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
index 3c0d599d00f27dc74d01aed02a779b93e97aff10..92dd925a6646d7477110ba86703149522eaa8ccb 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
@@ -41,7 +41,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
index 2141317b49815d07b95903b43c2a39e0b4fcf437..ffb6a7e81a155d9b9c578d7bed411c916d28acf2 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
@@ -41,7 +41,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
index fc8059c27da1138b6af034ebf7fd24ca64fa56f6..76ca23e4b7d50df2e4aca15005d2b06a73f53d97 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
@@ -40,7 +40,7 @@ quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index fe384d7392455d52937ed2c907c1e9701e225b1c..6b8dd8ebd11710ed5df9e7d90a190639bd2cfc45 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -28,9 +28,9 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
+ $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
+ $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
+ $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index c5353b22629392eedda2458ebc7059fce8b09583..a45392e234e98478c7c185e2fdab4c8b6252cb18 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -121,7 +121,7 @@ PACKAGE ddr3_pkg IS
CONSTANT c_ddr3_seq : t_ddr3_seq := (64, 1, 16, 4, 0, 5);
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -173,7 +173,7 @@ PACKAGE ddr3_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index 6fd0f1dfc474cd08e7ebac4f872060e433a71daa..7b331603b5c1c9b24772511130686ab79544445c 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -41,17 +41,17 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
ip_arria10_e1sg_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
- ip_arria10_e1sg_phy_10gbase_r_3 ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180
- ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180
- ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180
- ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180
- ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180
- ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180
- ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180
- ip_arria10_e1sg_transceiver_reset_controller_3 ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_180
- ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180
- ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180
- ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180
+ ip_arria10_e1sg_phy_10gbase_r_3 ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170
+ ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170
+ ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_3 ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170
synth_files =
sim_10gbase_r.vhd
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
index a7600bb30b0f2ac6f0072a7013780151f34e9079..a4bfba0a13ff5a15840dae36aabe10daa6e0ed53 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
@@ -21,18 +21,18 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_170;
LIBRARY IEEE, tech_pll_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/clkbuf/hdllib.cfg b/libraries/technology/clkbuf/hdllib.cfg
index 8f8e995b7cb826a3c2268fe4501c3930de332712..64d48639a170c7325736e7ee63735b07bb0a3016 100644
--- a/libraries/technology/clkbuf/hdllib.cfg
+++ b/libraries/technology/clkbuf/hdllib.cfg
@@ -7,7 +7,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_clkbuf_global ip_arria10_clkbuf_global_altclkctrl_150
ip_arria10_e3sge3_clkbuf_global ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
- ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_180
+ ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_170
synth_files =
tech_clkbuf_component_pkg.vhd
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index 621bc2a7c2460b59a06a47da2cc5fac0a32d96e5..b55e51bdde3ac19be82aeaed23ccc28841919859 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
-LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_180;
+LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_170;
ENTITY tech_clkbuf IS
GENERIC (
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index c19a8419fdc68e5d91c75e81c992b76a24dcfbb0..f26d4331997d5f4f4ff6c68f24ffa719f605c5f5 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -33,10 +33,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_ddr4_8g_1600 ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151
ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151
ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
- ip_arria10_e1sg_ddr4_4g_1600 ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180
- ip_arria10_e1sg_ddr4_8g_1600 ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180
- ip_arria10_e1sg_ddr4_4g_2000 ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180
- ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180
+ ip_arria10_e1sg_ddr4_4g_1600 ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170
+ ip_arria10_e1sg_ddr4_8g_1600 ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170
+ ip_arria10_e1sg_ddr4_4g_2000 ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170
+ ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170
ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
index 7f86edd95ac1fa3df17df07281a54373525a900b..6564425f2d010587da68966283742e348998e239 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
@@ -34,10 +34,10 @@
-- DDR interface monitoring purposes.
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180;
-LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180;
-LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180;
-LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180;
+LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170;
LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index 64314ddc33cf7363c3ae7c7fc9c394a67b62246f..011b01a5c1ddf503099ccd1ad3faf9d610c260c8 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -83,7 +83,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
@@ -134,7 +134,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -186,7 +186,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS
PORT (
@@ -237,7 +237,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
COMPONENT ip_stratixiv_ddr3_uphy_16g_dual_rank_800 IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -293,7 +293,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim/ip_arria10_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
COMPONENT ip_arria10_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -331,7 +331,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim/ip_arria10_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
COMPONENT ip_arria10_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -373,7 +373,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -449,7 +449,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -491,7 +491,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -567,7 +567,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index 229a8e1824ac0c18c50960c22bd93b3ce967a9c0..e0b73443cc0be208405596661a9760e4b338ea98 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -32,7 +32,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
------------------------------------------------------------------------------
-- Manually derived VHDL entity from Verilog module alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv in:
- -- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
+ -- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en IS
GENERIC (
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index bbb6a855c1ddd20f6665c5c715b41fbca0fc94b4..770dc9a79d5490fd97953c7387ef3806fd09def3 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -16,8 +16,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_remote_update ip_arria10_remote_update_altera_remote_update_150
ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
- ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180
- ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_180
+ ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170
+ ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_170
synth_files =
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index a546364ef186e3b588e1b9e605a909d6f61b772b..8ab92809687d21a2bba519305093e5047a4aa7f8 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
---LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180;
+--LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170;
ENTITY tech_flash_asmi_parallel IS
GENERIC (
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index 8c54bb8882de34ac5f1ed5d1be9dbd2f57396f88..f0949faec28f99afecb7931899a7d0a00c90d2af 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_remote_update_altera_remote_update_150;
LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
-LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_180;
+LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_170;
ENTITY tech_flash_remote_update IS
GENERIC (
diff --git a/libraries/technology/fpga_temp_sens/hdllib.cfg b/libraries/technology/fpga_temp_sens/hdllib.cfg
index 97baab475173f09c03d28879b67dc3f1d4685518..2e5124c781c28e9edeb3eab47a56835202a094f6 100644
--- a/libraries/technology/fpga_temp_sens/hdllib.cfg
+++ b/libraries/technology/fpga_temp_sens/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_temp_sense ip_arria10_temp_sense_altera_temp_sense_150
ip_arria10_e3sge3_temp_sense ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
- ip_arria10_e1sg_temp_sense ip_arria10_e1sg_temp_sense_altera_temp_sense_180
+ ip_arria10_e1sg_temp_sense ip_arria10_e1sg_temp_sense_altera_temp_sense_170
synth_files =
tech_fpga_temp_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index 749310fa3d6bb0ad3dc51d1aaa1abd880551d96c..65a773084abd2ad7ec2b9e97d690833afc61257b 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
-LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_180;
+LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_170;
ENTITY tech_fpga_temp_sens IS
diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg
index a9c9d063c01f162f1d8a2bdb6406bfa6bcf7a68b..03aaf853eda51a0d2cd3708ad0529fd869942e9b 100644
--- a/libraries/technology/fpga_voltage_sens/hdllib.cfg
+++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_voltage_sense ip_arria10_voltage_sense_altera_voltage_sense_150
ip_arria10_e3sge3_voltage_sense ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
- ip_arria10_e1sg_voltage_sense ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180
+ ip_arria10_e1sg_voltage_sense ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170
synth_files =
tech_fpga_voltage_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index f16657aba07348b85c295e2878517ff53c47ca47..bc66f172fd61c55364e1fe5cd3afb81c71fdfb9c 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
-LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180;
+LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170;
ENTITY tech_fpga_voltage_sens IS
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index 4814f9b5de2f475328906e2e8244a4a625d963f5..3c2cf1abd6a0a60053c1236255ee1723c7dcaf05 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -10,8 +10,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_fractional_pll_clk125 ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150
ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151
ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
- ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180
- ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180
+ ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170
+ ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170
synth_files =
tech_fractional_pll_component_pkg.vhd
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index 287a6098d48ea5d2e847716cca7f7592a8824161..cc8f297c07540396431186aace896b4dfc7b2e3f 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170;
ENTITY tech_fractional_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 4a986c4c47ed2d40b2cafb367bbeaa372e76a45e..f30733508e9b2efd2d487f614532c410eb9f9dc4 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170;
ENTITY tech_fractional_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
index ae2df593eb788c1bd856c3ef4ee6bfcc51f31e55..5e5795ffacb7327cc1fb4ee1c912613d8e7685ea 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/clkbuf_global/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
index d3d850ad78af1380552854cf8408013c43a0a0dd..102fa8aac0ac209cbf88c0c064ea56ce7b698256 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_clkbuf_global.qip
+ ip_arria10_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/complex_mult/README.txt b/libraries/technology/ip_arria10/complex_mult/README.txt
index 3e33649f60f2659c1bd624a9ee30584f601033b4..c9a33bbdfc0710640b0f4e967376ce8a5627e40e 100644
--- a/libraries/technology/ip_arria10/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10/complex_mult/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_complex_mult.qip
+ ip_arria10_complex_mult.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
index 6827e855133514c5e2adaf423974175ad78b49f5..43acb41dbef0fb27a4faaabf1a7ba7b8f4b8cab6 100644
--- a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/complex_mult/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
index b61b700ebc14cd241795b4e7c03098aa88475336..962d1268caa23270815d53c69e3a8a9bc9abf2bb 100644
--- a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_complex_mult.qip
+ ip_arria10_complex_mult.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/ddio/compile_ip.tcl b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
index 430497004bbcb70c56ca34534f296ffe2fc3fdf6..64aba5490a1ac644abeabe6b9924bdfe195d15fa 100644
--- a/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddio/generated/"
+ set IP_DIR "$env(HDL_BUILD_DIR)/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_150 ./work/
diff --git a/libraries/technology/ip_arria10/ddio/hdllib.cfg b/libraries/technology/ip_arria10/ddio/hdllib.cfg
index cdf478319d66ac57d73f8f0f9b5768961f614c45..79383ba97bf08f642c78a955cea688ea13047174 100644
--- a/libraries/technology/ip_arria10/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddio/hdllib.cfg
@@ -18,8 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_ddio_in_1.qip
- generated/ip_arria10_ddio_out_1.qip
+ ip_arria10_ddio_in_1.qip
+ ip_arria10_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
index 5dd0355376532c7b3214892a6530bd077cb58587..92b736708c5f397f2669fcabf33f23930c10c4fb 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
index ffbd501ac2f754bbc505a70c1faa6c686c2d72e5..fca54fa81397d5fe2fed6c83f43174c445ec9dc3 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
index cd9ab6a0c9e0e45c06e15eb22b2fd16d59ca00fd..d6d5dd48ae0a9eab63eb23186b74e24c96c9e4ed 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_ddr4_4g_1600.qip
+ ip_arria10_ddr4_4g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
index 3bd52fc0270ab1f1fa7bd13720bcb94c23bf7f5d..ec106dc119f0b937632a4dc67aff6a1c8d679b91 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
index 91add01c14d05f35e42525157fa5332d4264a84b..e0de434cf68a2b36abac305aa1295db9bf676ed6 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
index cf1a8b5f46641490bb5ed65b4beda8bb0d13eeb8..558f712cc221547a469ef2c8f0431ab9b44a2fad 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_ddr4_4g_2000.qip
+ ip_arria10_ddr4_4g_2000.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
index 24bb783efeda7bd7e3e3f9587f1caf695c27371f..748f3779e18a424294a431e7b32a6f6b27d11bf9 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
index e1301d8ab0afd141a15613adc3972036a6da6be8..dca56d5c3c797d693a1497ee635df4ba72270577 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
index 9883e05153ab7b07770370037e779776332aab98..1687d60fabd5619c6ebdb3e158bdc9233d646d35 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_ddr4_8g_2400.qip
+ ip_arria10_ddr4_8g_2400.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/fifo/README.txt b/libraries/technology/ip_arria10/fifo/README.txt
index cfe2a2a2d88c7a058d3596d9b1297941b2b0e8a3..6db25b6412e89ebde6decb09c13f7e14890315b0 100755
--- a/libraries/technology/ip_arria10/fifo/README.txt
+++ b/libraries/technology/ip_arria10/fifo/README.txt
@@ -38,7 +38,7 @@ Contents:
The IP only needs to be generated with ./generate_ip.sh if it need to be modified, because the ip_arria10_fifo_*.vhd
directly instantiates the altera_mf component.
- The instantiation is copied manually from the generated/ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
+ The instantiation is copied manually from the ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
saved in the <fifo_name>.vhd file. So then the MegaWizard vhd file is overwritten, but that is fine because it is
no longer needed, it could easily be derived from the original in $UNB and it is still as a previous verion in SVN.
diff --git a/libraries/technology/ip_arria10/fifo/generate_ip.sh b/libraries/technology/ip_arria10/fifo/generate_ip.sh
index 11005f95c6c894c6e0a9143d58263d6c12f02d30..1607650bfaa0b447ea8126e09cc24763773c6799 100755
--- a/libraries/technology/ip_arria10/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10/fifo/generate_ip.sh
@@ -33,7 +33,7 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_fifo_*.vhd directly instantiates
# the FIFO altera_mf component.
-# The instantiation is copied manually from the generated/ip_arria10_ram_*/fifo_140/sim/ip_arria10_fifo_*.vhd.
+# The instantiation is copied manually from the ip_arria10_ram_*/fifo_140/sim/ip_arria10_fifo_*.vhd.
# It appears that the altera_mf FIFO component for Arria10 can be synthesized similar as how it worked for Stratix IV,
# it is not necessary to use the generated qip file.
#
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
index 94b0a67c51d3bd0140cb7b4d16ac3b26c2ae28b5..7ad84ee07bff1ab5473c734fc53609797e73dec8 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/flash/asmi_parallel/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
vmap ip_arria10_asmi_parallel_altera_asmi_parallel_150 ./work/
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
index fada8c8e4770a5349fdf9420106e5d545013c74d..a9fea8a6d5126608839e13ef938e3796fa2e82b4 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_asmi_parallel.qip
+ ip_arria10_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
index 525eab6a87858831ec23804a673ee3d31db94264..46836c839335b0c1a9a26c7f65d7bd45452a9657 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/flash/remote_update/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
vmap ip_arria10_remote_update_altera_remote_update_core_150 ./work/
vmap ip_arria10_remote_update_altera_remote_update_150 ./work/
diff --git a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
index 464e3bdf685dbac3ff33fbab550e8e57b0e99e46..32cacf3e6b3bb947f5dfa6fc67d9f72d6584545f 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_remote_update.qip
+ ip_arria10_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
index 9611ac9b640e6937da631f0a8e67af2508e6b8f2..80a62c66728cbf85d97b24a84daed153673028b7 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/fractional_pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
index 71d929e9ed0838112dec25ae674a400dee033a2e..f413ae490ea9623608adbb9260f991cb125cb117 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_fractional_pll_clk125.qip
+ ip_arria10_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
index 09f0c82f72c1d92c125e6b881f965cc730ee5896..8d2f641fcc8860bd127d95f956d2d36c11d49292 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/fractional_pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
index 6b6b3cef3a03c45ce48331e26a1885e38240ee23..1f2b25388914d39d7d2c0486ea5f93ada251af38 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_fractional_pll_clk200.qip
+ ip_arria10_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/mac_10g/README.txt b/libraries/technology/ip_arria10/mac_10g/README.txt
index 1809358e9cffbc914b28099a977ad0b8ff8cc4b6..c775402d02b409cbc5f046ee91549577ddf8c52a 100644
--- a/libraries/technology/ip_arria10/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10/mac_10g/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_mac_10g.qip
+ ip_arria10_mac_10g.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
index 0f37f969c407d542e6c39cb771790847d679b240..1865ab2bb04acaf84406cb094a18d831a8c38a89 100644
--- a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/mac_10g/generated/sim"
-set IP_TBDIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_TBDIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
index bd87b3444a62616a3a7658d5b9778262801a0927..4a0011ee35ba95992d898a467858dea8cbbdcf18 100644
--- a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim/ip_arria10_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
[modelsim_project_file]
@@ -19,7 +19,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_mac_10g.qip
+ ip_arria10_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
index f834dcc99eb443ed8c4fb4a82c4d8bba55fb4623..464263f96b1dc6127b43eaa84d9440869022c315 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
@@ -41,7 +41,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_phy_10gbase_r.qip
+ ip_arria10_phy_10gbase_r.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
index a2f5e5be1005fd0c87a9b9d2b4213100f20d2752..05fdc5ebb71331a4d596bfed14fbfb75e1abe958 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
index b4fc8605ca16e4f92ee839784c3819bfd786f10c..dc9cdc38dd58ba6d12a5f4c992fd4ac58860dd2f 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_phy_10gbase_r.qip
+ ip_arria10_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
index 7130d548d2b43fb60c27b172af0354138c42070e..4df7738bdcbbb9259a5ad46048c80e97ed3fa5b6 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
index 52866d708073a7ebe239797d043ad2ad746a26c5..574c29ca06bc1e882bad82ee4c5f757b3b0352f6 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_phy_10gbase_r_12.qip
+ ip_arria10_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
index ecd8cac0a1db77d42b518b869cd7520538d58e4f..5ef95c261f33071aa5333527bd61316d970b3c45 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
index 0c22bfef188eb257abad90e025ee076cd3ae43f5..7aa111c072e30c79be6f672dae7d9af8723b0ad9 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_phy_10gbase_r_24.qip
+ ip_arria10_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
index 319a66812304e280e64a50fbec79edbfc9d25358..4df2e0bdecb96b8ef473082f28af7a7b09c5bf41 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
index 9066174d786492eb41234e3a20b567788675f695..6438682b22c6a49d814176ab71d0968518c8daba 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_phy_10gbase_r_4.qip
+ ip_arria10_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
index 89d1df9134cef0c6b0081d0b886cae0179b5b028..53e06e4de13144c7d5f04c48b2a3668b4b0b3ab3 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/phy_10gbase_r_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
index 3372c4933b0ec4fe8b1816436344ef301630c4fd..d280316c1bd341663c279b03e817751788409eb4 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_phy_10gbase_r_48.qip
+ ip_arria10_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
index ceb880b97151f1e52528716b1e5e3dbf763ad785..ca650eea03c441dd28c7d1db95fe5858d2e1b2b9 100644
--- a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
index 716dc236332a8674c7fa04695779f833b9f8da4e..b6b6d86efd6e6d11947dafbbe66f1e17ec5dc36f 100644
--- a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_pll_clk125.qip
+ ip_arria10_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
index 45f591f9ebf41e504a4c58b319ea086c1af08c90..88558ac77859eb3864cb9657e3f8c21539db39b1 100644
--- a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
index a2cceba6b3982372b58d8759635e927b3e7ef2eb..c3b7fa01be56d79d4a118130f428532ce0100e25 100644
--- a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_pll_clk200.qip
+ ip_arria10_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
index 8d6c1ffe3a9a802a240f3a4ac23ef0f2e77bb616..65f55bd48db30500ebe48bf5dc93e019d032d020 100644
--- a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_clk25/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
index 9254e792929235d2fd918a8f29e26410f513acac..3a1a86267ad5ef185233f4727447e4ed23fafb95 100644
--- a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_pll_clk25.qip
+ ip_arria10_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
index b9f8625f8c0f54a5f49dc8bf7fecafea804b1501..20e438b4c19e1e7c1aca450ab6bc3e439f4c0d49 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
index e868b714afa0b520ed1745bdc02933bc475f2a3d..7fb31eb197dcae6f23a2ffcb726990a76db3eb0a 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_pll_xgmii_mac_clocks.qip
+ ip_arria10_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/ram/README.txt b/libraries/technology/ip_arria10/ram/README.txt
index a9fe41102a7d2cec63b7c2f3846b28447c1b4bc0..24ad4ab94e542bd2d642eaa079f4e18624d8c163 100755
--- a/libraries/technology/ip_arria10/ram/README.txt
+++ b/libraries/technology/ip_arria10/ram/README.txt
@@ -32,7 +32,7 @@ Contents:
if it need to be modified, because the ip_arria10_ram_*.vhd directly instantiates the altera_syncram component.
- The instantiation is copied manually from the generated/ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
+ The instantiation is copied manually from the ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
diff --git a/libraries/technology/ip_arria10/ram/generate_ip.sh b/libraries/technology/ip_arria10/ram/generate_ip.sh
index c1ca91ebd03b0d97ba2f14f2f8740f1c59263ebc..188eef243f8ec88b6a9d055a08bb9e49ee8e08b8 100755
--- a/libraries/technology/ip_arria10/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10/ram/generate_ip.sh
@@ -33,7 +33,7 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_ram_*.vhd directly instantiates
# the altera_syncram component.
-# The instantiation is copied manually from the generated/ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
+# The instantiation is copied manually from the ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
# It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
# that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
#
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
index e8c756ea162cb8320a3ac1c6a45268f64976ad6e..94c873952bb7bca2189c51dd8a9cfa9be8a3580f 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
@@ -99,7 +99,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_ram_cr_cw/ram_2port_140/sim/ip_arria10_ram_cr_cw_ram_2port_140_72tpmcy.vhd
+ -- Copied from ip_arria10_ram_cr_cw/ram_2port_140/sim/ip_arria10_ram_cr_cw_ram_2port_140_72tpmcy.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
index 70e872b00d924ce34749fe3b5554d26709e3b3e9..f1694d54629c187972fda239eb2cecebf547f953 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
@@ -115,7 +115,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_ram_crw_crw/ram_2port_140/sim/ip_arria10_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
+ -- Copied from ip_arria10_ram_crw_crw/ram_2port_140/sim/ip_arria10_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
index 08dce27a6446b37068746fd88b7140bd9ae9cddf..0a9ee2b8314d4d773ded525c924a5bb983db8550 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
@@ -95,7 +95,7 @@ ARCHITECTURE SYN OF ip_arria10_ram_crwk_crw IS
BEGIN
- -- Copied from generated/ip_arria10_ram_crwk_crw/ram_2port_140/sim/ip_arria10_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
+ -- Copied from ip_arria10_ram_crwk_crw/ram_2port_140/sim/ip_arria10_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
index 2399d0eb74c2b7b33018e01418897f5aeffa1cfd..9cd46d0f8ce592a17164ae11b388fd5e2e29c868 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
@@ -96,7 +96,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_ram_r_w : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_ram_r_w/ram_2port_140/sim/ip_arria10_ram_r_w_ram_2port_140_hukd7xi.vhd
+ -- Copied from ip_arria10_ram_r_w/ram_2port_140/sim/ip_arria10_ram_r_w_ram_2port_140_hukd7xi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
index fa0b733b4853cc48862ca4e049c911dce64dff3e..e24b47eab8f26f11b277087e52befb7ed06a3160 100644
--- a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/temp_sense/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
index 743b54a4f88c025ce6b8444137182ec573e67261..7712a5afed2dcd740381c1f2dc839598a742e8ed 100644
--- a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
@@ -15,7 +15,7 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_temp_sense.qip
+quartus_qip_files = ip_arria10_temp_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
index 51e4722bd7e3add5f21714c9bf2351cf5e4341fa..0ca0862832784bf6d305b2a30503b0e76fd964ee 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_pll_10g/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
index be5fa19d53e3a993f37fdb5c2a96423e5bcef3eb..ab125a22db26bb1d563ea3d2274aff56b83b9026 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_pll_10g.qip
+ ip_arria10_transceiver_pll_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
index 69d241877320e2292a00293b4adf82a1827fce59..ede7525a7c82aea577cfeb7fb9f0a8aba1d026b8 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_1/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
index 64be140c28c9f368ea90990d0d1ce26b4b53d8ed..45b9e866eae9942cf3067f8354e1afb0e98770d2 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_reset_controller_1.qip
+ ip_arria10_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
index 22ce7e0c271a82712cf70a260e84be6fe772fae3..7e487453a1f8d57295d9203d6868e04cc2895739 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
index f5aa17bd7710f634a05d28d17a47efdd356bf2ea..8cb43574cbfe737753d50b05a3c84c40e9737e5d 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_reset_controller_12.qip
+ ip_arria10_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
index 1a97798dde2932572b1feead56ca43d71af97743..4b2d7cd58b179c78354392060a21f5d418fd7e4f 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
index f9d08597da5d9b0909157e2e4e86fa44d0406b2c..02bdc47594ad88707371e661ab1b51ca9eb77a90 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_reset_controller_24.qip
+ ip_arria10_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
index 1d2e7d499738e57987f28d28adc2fb8db607b818..2adc9e61a6b8385bc9d5604eeaa9ec630c71e2ef 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
index 7e5fb7f0d3f360fcd134b7e9a7d65554043129f1..e2f5fe2620de365fe520ca0d5de24f117305495a 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_reset_controller_4.qip
+ ip_arria10_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
index 62da163837b3521bc9e2ba2f5cef403c7e4971ee..89dc59e26a28cf196eee9369a1512982901dc64f 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/transceiver_reset_controller_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
index a519b5da8e54582821d1650ec965a7f868bf1e8c..9e5de0cc3ee075243e0c11f59caddaf215236116 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_transceiver_reset_controller_48.qip
+ ip_arria10_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
index 22a2478a6c2c24a7563d556a71e18b11dbe72ebb..97a8f992de1d36397fcd1fb8d80bbec7c3e8806a 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
index 76550d695f72411c7d03f86fe8545706026b5289..f4b67edbe25a7ec4e13713480126b85b45a7aa1a 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_tse_sgmii_gx.qip
+ ip_arria10_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
index 395170e9f5ae765c201cde515fc867c5945bdbee..a9062836f7bbd80f60938f94448f21f763016b54 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
index f840e7826f40f94faec2e6e460df37b1920e9416..a9294f7aa9bf5704a24bcfda2c8824ce78627957 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_tse_sgmii_lvds.qip
+ ip_arria10_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
index 0e319959043dea8f60899f2629bdc3ac11058ec0..03e7c495f2853b87e59a0b396d86a7b86da4b0db 100644
--- a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/voltage_sense/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
index 72730345ecd9e56704f92012704fe397e732117a..bd24313b8416514d4deb34db07a2f44fe9c2d7bf 100644
--- a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_voltage_sense.qip
+quartus_qip_files = ip_arria10_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
deleted file mode 100644
index 169569c196cc4582fc7e6d5d88b3945aad9ba036..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/compile_ip.tcl
+++ /dev/null
@@ -1,149 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
-
-vmap alt_em10g32_180 ./work/
-
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/alt_em10g32.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/alt_em10g32unit.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_clk_rst.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_clock_crosser.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_crc32.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_creg_map.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_creg_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_frm_decoder.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_pipeline_base.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rst_cnt.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_frm_control.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_stat_mem.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_stat_reg.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_flow_control.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_pause_req.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rr_buffer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_sc_fifo.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_altsyncram.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii_ultra.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii_tsu.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii16b_tsu.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_lpm_mult.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_ptp_processor.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_crc328generator.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_crc32ctl8.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_crc32galois8.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii16b_crc_inserter.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/mentor/rtl/alt_em10g32_gmii16b_crc32.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/alt_em10g32_avalon_dc_fifo.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/alt_em10g32_dcfifo_synchronizer_bundle.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/alt_em10g32_std_synchronizer.v" -work alt_em10g32_180
- vlog "$IP_DIR/../alt_em10g32_180/sim/altera_std_synchronizer_nocut.v" -work alt_em10g32_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg
deleted file mode 100644
index 0276da73e5d94054597151b6393c58a4eb82d2af..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_170/hdllib.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_alt_em10g32_180
-hdl_library_clause_name = alt_em10g32_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
- # The generated testbench is listed here to create a simulation configuration for it. However
- # the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
deleted file mode 100644
index 7fab7f0b8ee70103da5cf82415cb1bbd800b1116..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/compile_ip.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap alt_mem_if_jtag_master_180 ./work/
-
- vcom "$IP_DIR/../alt_mem_if_jtag_master_180/sim/ip_arria10_e1sg_ddr4_8g_1600_alt_mem_if_jtag_master_180_biwt3uq.vhd" -work alt_mem_if_jtag_master_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg
deleted file mode 100644
index 21f6ab7cfc4cffde8b55b9d3ca430d1bcad81d5b..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_alt_mem_if_jtag_master_180
-hdl_library_clause_name = alt_mem_if_jtag_master_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_jtag_dc_streaming_180 ip_arria10_e1sg_timing_adapter_180 ip_arria10_e1sg_altera_avalon_sc_fifo_180 ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_180 ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_180 ip_arria10_e1sg_altera_avalon_packets_to_master_180 ip_arria10_e1sg_channel_adapter_180 ip_arria10_e1sg_altera_reset_controller_180
-
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
deleted file mode 100644
index 75d1e499c628497b2ecbf51563c7f28b44d51111..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/compile_ip.tcl
+++ /dev/null
@@ -1,35 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
-
-vmap altclkctrl_180 ./work/
- vcom "$IP_DIR/../altclkctrl_180/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_180_7fwzyby.vhd" -work altclkctrl_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg
deleted file mode 100644
index d16da4aa988dfc2369d7c330401fcc33f33b53b9..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altclkctrl_180
-hdl_library_clause_name = altclkctrl_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
deleted file mode 100644
index 72d66d3bbe729ca03d1510f1f55370aa35fcfe44..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
-
-vmap altera_asmi_parallel_180 ./work/
-
-
- vcom "$IP_DIR/../altera_asmi_parallel_180/sim/ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180_eou4tfa.vhd" -work altera_asmi_parallel_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg
deleted file mode 100644
index 6a653a16896034a3253bb38ef3bab954c82c9e07..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_170/hdllib.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_asmi_parallel_180
-hdl_library_clause_name = altera_asmi_parallel_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
deleted file mode 100644
index 810bc500b8c21635b98b557fd545e143e5483ccc..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/compile_ip.tcl
+++ /dev/null
@@ -1,35 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
-vmap altera_avalon_mm_bridge_180 ./work/
-
- vlog "$IP_DIR/../altera_avalon_mm_bridge_180/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg
deleted file mode 100644
index 97f5b33a724769d4ddab878d345300ced1ec6cf7..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_170/hdllib.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_mm_bridge_180
-hdl_library_clause_name = altera_avalon_mm_bridge_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
- # The generated testbench is listed here to create a simulation configuration for it. However
- # the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
deleted file mode 100644
index c0eaa3adcae603d79f81c6ed9ed31fb6fb3c4fa1..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/compile_ip.tcl
+++ /dev/null
@@ -1,46 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-vmap altera_avalon_onchip_memory2_180 ./work/
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg
deleted file mode 100644
index 3f74f6bb1421b14d8938d11829b1827cd0925ee3..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_onchip_memory2_180
-hdl_library_clause_name = altera_avalon_onchip_memory2_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
deleted file mode 100644
index 0544c814cd5050a4b85cae8991e446f758adb111..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap altera_avalon_packets_to_master_180 ./work/
-
- vlog "$IP_DIR/../altera_avalon_packets_to_master_180/sim/altera_avalon_packets_to_master.v" -work altera_avalon_packets_to_master_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg
deleted file mode 100644
index 3289315446cc383f3eeb84c3163a1cea5dcd7233..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_packets_to_master_180
-hdl_library_clause_name = altera_avalon_packets_to_master_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
deleted file mode 100644
index f852a2af5b1dc350ab349a11215a19154da2ae95..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/compile_ip.tcl
+++ /dev/null
@@ -1,40 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap altera_avalon_sc_fifo_180 ./work/
- vlog "$IP_DIR/../altera_avalon_sc_fifo_180/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_180
-
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg
deleted file mode 100644
index 7bf034a3bcb61e092a479771a27ec097eb27b481..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_sc_fifo_180
-hdl_library_clause_name = altera_avalon_sc_fifo_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
deleted file mode 100644
index 12e257917df39ebd70ee8d61019370ac60e8a371..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap altera_avalon_st_bytes_to_packets_180 ./work/
-
- vlog "$IP_DIR/../altera_avalon_st_bytes_to_packets_180/sim/altera_avalon_st_bytes_to_packets.v" -work altera_avalon_st_bytes_to_packets_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg
deleted file mode 100644
index 55d4345da94d771253e6f80c9d5db7ed48c57449..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_180
-hdl_library_clause_name = altera_avalon_st_bytes_to_packets_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
deleted file mode 100644
index f2897169838f9026d452ab3c83a49caed62008db..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/compile_ip.tcl
+++ /dev/null
@@ -1,39 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-vmap altera_avalon_st_packets_to_bytes_180 ./work/
-
- vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_180/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_180
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg
deleted file mode 100644
index 3b7ae8e33f1351b8105bf70fffe638ce1b9c9f38..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_180
-hdl_library_clause_name = altera_avalon_st_packets_to_bytes_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
deleted file mode 100644
index b2b1fad697082ceb1556fa7ce6eada3f0b122877..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/compile_ip.tcl
+++ /dev/null
@@ -1,162 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-vmap altera_emif_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180_fpxzpei.v" -work altera_emif_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180_e7aaa3y.v" -work altera_emif_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180_zmrgaza.v" -work altera_emif_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180_xxodvzi.v" -work altera_emif_180
-
-vmap altera_emif_arch_nf_180 ./work/
-# ddr4_4g_1600
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti.sv" -work altera_emif_arch_nf_180
-
-# ddr4_4g_2000
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq.sv" -work altera_emif_arch_nf_180
-
-# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei.sv" -work altera_emif_arch_nf_180
-
-# ddr4_8g_2400
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i.sv" -work altera_emif_arch_nf_180
-
-# common dependencies
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_oct.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_180
- vlog "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_180
-
-vmap altera_emif_cal_slave_nf_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-vmap altera_reset_controller_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_180
- vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_180
-
-vmap altera_mm_interconnect_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_3gbam2q.vhd" -work altera_mm_interconnect_180
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_lcqbbfq.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
-vmap altera_avalon_onchip_memory2_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
-
-
-vmap altera_avalon_mm_bridge_180 ./work/
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
- vlog "$IP_DIR/../altera_avalon_mm_bridge_180/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg
deleted file mode 100644
index b934e75cc06f534d7bfb0f830f7724e7b4e94629..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_emif_180
-hdl_library_clause_name = altera_emif_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_180 ip_arria10_e1sg_altera_merlin_slave_translator_180
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
deleted file mode 100644
index e641ceb72f2cac9f5852a7524b03d0e71ac71b15..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/compile_ip.tcl
+++ /dev/null
@@ -1,98 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-vmap altera_emif_arch_nf_180 ./work/
-
-# ddr4_4g_1600
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti.sv" -work altera_emif_arch_nf_180
-
-# ddr4_4g_2000
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_ctgfmtq.sv" -work altera_emif_arch_nf_180
-
-# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_eg5lvei.sv" -work altera_emif_arch_nf_180
-
-# ddr4_8g_2400
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
-
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i_top.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_as3yf3i.sv" -work altera_emif_arch_nf_180
-
-# common dependencies
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_oct.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_180
- vlog "$IP_DIR/../altera_emif_arch_nf_180/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_180
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg
deleted file mode 100644
index 88ddb715cba8b5a8e292acb28df5d0e6f2430cdf..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_170/hdllib.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_emif_arch_nf_180
-hdl_library_clause_name = altera_emif_arch_nf_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
- # The generated testbench is listed here to create a simulation configuration for it. However
- # the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
deleted file mode 100644
index 7e92b4234e60dab59e3f1100ef5115665f5d1cfd..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/compile_ip.tcl
+++ /dev/null
@@ -1,47 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-vmap altera_emif_cal_slave_nf_180 ./work/
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_6qfmevy.v" -work altera_emif_cal_slave_nf_180
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg
deleted file mode 100644
index b7252eec612d79ea014b71db59b1e4455aa17470..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_emif_cal_slave_nf_180
-hdl_library_clause_name = altera_emif_cal_slave_nf_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
deleted file mode 100644
index 0ba63276cac13543bedbf62a4343efd2905dc755..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/compile_ip.tcl
+++ /dev/null
@@ -1,40 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-vmap altera_eth_tse_180 ./work/
-
-# tse_sgmii_gx
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
-vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180_bs6nd6i.vhd" -work altera_eth_tse_180
-
-# tse_sgmii_lvds
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
-vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180_kv2t7sq.vhd" -work altera_eth_tse_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg
deleted file mode 100644
index 06e083362fff352f9c6b5ab461ee3e50bb7e1bf5..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_170/hdllib.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_180
-hdl_library_clause_name = altera_eth_tse_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-ip_arria10_e1sg_altera_eth_tse_mac_180
-ip_arria10_e1sg_altera_eth_tse_avalon_arbiter_180
-ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_phyip_180
-ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_lvds_180
-ip_arria10_e1sg_altera_xcvr_native_a10_180
-ip_arria10_e1sg_altera_eth_tse_nf_phyip_terminator_180
-ip_arria10_e1sg_altera_eth_tse_nf_lvds_terminator_180
-ip_arria10_e1sg_altera_lvds_180
-ip_arria10_e1sg_altera_reset_controller_180
-
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
deleted file mode 100644
index 745643de560cb12de6b0b920fba23e285e37e5b9..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/compile_ip.tcl
+++ /dev/null
@@ -1,33 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
-vmap altera_eth_tse_avalon_arbiter_180 ./work/
- vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_180/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg
deleted file mode 100644
index dfd8b2b09dd4a031fbf041cc21478ce7c319d34b..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_avalon_arbiter_180
-hdl_library_clause_name = altera_eth_tse_avalon_arbiter_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
deleted file mode 100644
index cd0fcdb40a8b1289d0713e52f050431c99c99341..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/compile_ip.tcl
+++ /dev/null
@@ -1,148 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
-
-vmap altera_eth_tse_mac_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_eth_tse_mac.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_clk_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_crc328checker.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_crc328generator.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_crc32ctl8.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_crc32galois8.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_gmii_io.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_lb_read_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_lb_wrt_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_hashing.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_host_control.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_host_control_small.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mac_control.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_register_map.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_register_map_small.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_counter_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_shared_mac_control.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_shared_register_map.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_counter_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_lfsr_10.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_loopback_ff.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_altshifttaps.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_fifoless_mac_rx.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mac_rx.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_fifoless_mac_tx.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mac_tx.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_magic_detection.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mdio.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mdio_clk_gen.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mdio_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_mdio.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mii_rx_if.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_mii_tx_if.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_pipeline_base.v" -work altera_eth_tse_mac_180
- vlog -sv "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_pipeline_stage.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_dpram_16x32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_dpram_8x32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_dpram_ecc_16x32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_fifoless_retransmit_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_retransmit_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rgmii_in1.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rgmii_in4.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_nf_rgmii_module.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rgmii_module.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rgmii_out1.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rgmii_out4.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_ff.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_min_ff.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_ff_cntrl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_ff_cntrl_32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_ff_length.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_rx_stat_extract.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_timing_adapter32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_timing_adapter8.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_timing_adapter_fifo32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_timing_adapter_fifo8.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_1geth.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_fifoless_1geth.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_w_fifo.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_w_fifo_10_100_1000.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_wo_fifo.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_wo_fifo_10_100_1000.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_top_gen_host.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_min_ff.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff_cntrl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff_cntrl_32.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff_length.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_ff_read_cntl.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_tx_stat_extract.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_mac_180
- vlog -sv "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_mac_180
- vlog "$IP_DIR/../altera_eth_tse_mac_180/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_mac_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg
deleted file mode 100644
index 3ca851ab1d2ef90e6cf2b0b793c6710e42756364..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_mac_180
-hdl_library_clause_name = altera_eth_tse_mac_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
deleted file mode 100644
index 01cb1beef867af0eae383e5c496c87ada769840c..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/compile_ip.tcl
+++ /dev/null
@@ -1,40 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
-vmap altera_eth_tse_nf_lvds_terminator_180 ./work/
-
-
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_180
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/mentor/altera_eth_tse_nf_lvds_terminator.v" -work altera_eth_tse_nf_lvds_terminator_180
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_180
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/mentor/altera_tse_nf_lvds_channel_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_180
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/mentor/altera_tse_nf_lvds_common_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_180
- vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_180/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_nf_lvds_terminator_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg
deleted file mode 100644
index 6cc184f5c60d447b5e774aa90425e71ae846bc61..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_nf_lvds_terminator_180
-hdl_library_clause_name = altera_eth_tse_nf_lvds_terminator_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
deleted file mode 100644
index b52152f566e1cf059b6171d50e0398d51dee4322..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/compile_ip.tcl
+++ /dev/null
@@ -1,35 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
-
-vmap altera_eth_tse_nf_phyip_terminator_180 ./work/
-
- vlog "$IP_DIR/../altera_eth_tse_nf_phyip_terminator_180/sim/mentor/altera_eth_tse_nf_phyip_terminator.v" -work altera_eth_tse_nf_phyip_terminator_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg
deleted file mode 100644
index 20e2f82c822650dffeb230becfa7416a1a49e5fd..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_nf_phyip_terminator_180
-hdl_library_clause_name = altera_eth_tse_nf_phyip_terminator_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
deleted file mode 100644
index 60f0c2d8ee10036429592ab4f95b82e8fbc6ad73..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/compile_ip.tcl
+++ /dev/null
@@ -1,114 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
-
-vmap altera_eth_tse_pcs_pma_nf_lvds_180 ./work/
-
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_eth_tse_pcs_pma_nf_lvds.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_lvds_reset_sequencer.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_lvds_reverse_loopback.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_pma_lvds_rx_av.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_pma_lvds_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_pma_lvds_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ph_calculator.sv" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg
deleted file mode 100644
index e32f89526d82d3d49ee09b86d0a44e44fe2f2420..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_lvds_180
-hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_lvds_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
deleted file mode 100644
index 3cd6e2eef40b8290a34a6a6cd766b3a6d3057436..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/compile_ip.tcl
+++ /dev/null
@@ -1,116 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
-
-
-vmap altera_eth_tse_pcs_pma_nf_phyip_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
-
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_eth_tse_pcs_pma_nf_phyip.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_reset_sequencer.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_reset_ctrl_lego.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_xcvr_resync.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_gxb_aligned_rxsync.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg
deleted file mode 100644
index 37eeea420586c91ae99ab0d51d5bc775c2eb8b77..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_eth_tse_pcs_pma_nf_phyip_180
-hdl_library_clause_name = altera_eth_tse_pcs_pma_nf_phyip_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
deleted file mode 100644
index 1f120ec18e4fb5dfd7ffb8281b170277b0dbfd9e..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/compile_ip.tcl
+++ /dev/null
@@ -1,41 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-vmap altera_iopll_180 ./work/
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
- vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_180_7lq52ua.vo" -work altera_iopll_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
- vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_180_3a4ewza.vo" -work altera_iopll_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
- vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_180_bqwoevq.vo" -work altera_iopll_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg
deleted file mode 100644
index cd252f68f6b28d98d5fbc0fd5431ecccac466b12..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_iopll_180
-hdl_library_clause_name = altera_iopll_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
deleted file mode 100644
index b6b2f7ec3a8f9d02e2cd73905e470569697081d9..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap altera_ip_col_if_180 ./work/
-
- vlog "$IP_DIR/../altera_ip_col_if_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_ip_col_if_180_bnb3mmy.v" -work altera_ip_col_if_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg
deleted file mode 100644
index 3ba5bffd7c613ab3460c0c1bbba5dea87232e7c0..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_ip_col_if_180
-hdl_library_clause_name = altera_ip_col_if_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
deleted file mode 100644
index 31fd2798556e69df0894eb6a5db26754dfb2a49d..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/compile_ip.tcl
+++ /dev/null
@@ -1,45 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap altera_jtag_dc_streaming_180 ./work/
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_jtag_dc_streaming.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_jtag_sld_node.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_jtag_streaming.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_clock_crosser.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_std_synchronizer_nocut.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_pipeline_base.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_idle_remover.v" -work altera_jtag_dc_streaming_180
- vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_idle_inserter.v" -work altera_jtag_dc_streaming_180
- vlog -sv "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_pipeline_stage.sv" -work altera_jtag_dc_streaming_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg
deleted file mode 100644
index 9ab2d1bf1181f09457185a3c2c3c31397b7f9184..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_jtag_dc_streaming_180
-hdl_library_clause_name = altera_jtag_dc_streaming_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
deleted file mode 100644
index c015c3a84bb05ff4087060907e49a02cef3a6310..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/compile_ip.tcl
+++ /dev/null
@@ -1,34 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
-vmap altera_lvds_180 ./work/
- vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_m5pqrlq.vhd" -work altera_lvds_180
- vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_o42lhkq.vhd" -work altera_lvds_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg
deleted file mode 100644
index c9f081b5e9ab2420e0ff9abfd97dbfa7984e8743..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_lvds_180
-hdl_library_clause_name = altera_lvds_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_lvds_core20_180
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
deleted file mode 100644
index 9b8d787a34246602464baa377415f7da43fbb64b..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/compile_ip.tcl
+++ /dev/null
@@ -1,39 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
-vmap altera_lvds_core20_180 ./work/
-
-
- vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_180
- vlog "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
- vcom "$IP_DIR/../altera_lvds_core20_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_180_qagiwoa.vhd" -work altera_lvds_core20_180
- vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_180
- vlog "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
- vcom "$IP_DIR/../altera_lvds_core20_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_180_o4ldvbi.vhd" -work altera_lvds_core20_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg
deleted file mode 100644
index 7c32b3d8096cb666f8cd6647647cf80f5da0055d..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_lvds_core20_180
-hdl_library_clause_name = altera_lvds_core20_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
deleted file mode 100644
index 463209d51de1637445d391a0f1a8b426e6fd8e54..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/compile_ip.tcl
+++ /dev/null
@@ -1,36 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
-vmap altera_merlin_master_translator_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_merlin_master_translator_180/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg
deleted file mode 100644
index 2b22aa3b9bab2038ce187766a3eeed776b5dc003..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_merlin_master_translator_180
-hdl_library_clause_name = altera_merlin_master_translator_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
deleted file mode 100644
index 88f541d2deda694082988e61367679804dbc9587..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/compile_ip.tcl
+++ /dev/null
@@ -1,36 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
-vmap altera_merlin_slave_translator_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_merlin_slave_translator_180/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg
deleted file mode 100644
index 91f77c91d4b20c333d22748539109255b9ec0980..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_merlin_slave_translator_180
-hdl_library_clause_name = altera_merlin_slave_translator_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
deleted file mode 100644
index eaafd3dcc557663a5191d087e4b42811b648d18b..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/compile_ip.tcl
+++ /dev/null
@@ -1,46 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-vmap altera_mm_interconnect_180 ./work/
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_3gbam2q.vhd" -work altera_mm_interconnect_180
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_lcqbbfq.vhd" -work altera_mm_interconnect_180
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
- vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_o2ys4ki.vhd" -work altera_mm_interconnect_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg
deleted file mode 100644
index 73f5fa237c14155ceb1562acc27f9bc2365ad5b7..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_mm_interconnect_180
-hdl_library_clause_name = altera_mm_interconnect_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_180 ip_arria10_e1sg_altera_merlin_slave_translator_180
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
deleted file mode 100644
index 33ac71fc504760d4175211b95f5abb86148f7fb9..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
-
-vmap altera_remote_update_180 ./work/
-
- vcom "$IP_DIR/../altera_remote_update_180/sim/ip_arria10_e1sg_remote_update_altera_remote_update_180_hsvaqga.vhd" -work altera_remote_update_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg
deleted file mode 100644
index 699861d08871f499d913760cc635f80cf95fce69..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_170/hdllib.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_remote_update_180
-hdl_library_clause_name = altera_remote_update_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_remote_update_core_180
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
deleted file mode 100644
index 2aeb0314850a68468cc954a987088bf6b393a7da..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/compile_ip.tcl
+++ /dev/null
@@ -1,40 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
-
-
-vmap altera_remote_update_core_180 ./work/
-
-
- vlog "$IP_DIR/../altera_remote_update_core_180/sim/mentor/altera_remote_update_core.sv" -work altera_remote_update_core_180
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg
deleted file mode 100644
index 92dcbaea09fc47c3e4c54fa832a508ad6a2001b6..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_170/hdllib.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_remote_update_core_180
-hdl_library_clause_name = altera_remote_update_core_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
deleted file mode 100644
index 1696fa3810023a6c8258ca1a6c6edf2d2918a44d..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/compile_ip.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
-
-vmap altera_reset_controller_180 ./work/
-
- vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_180
- vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg
deleted file mode 100644
index 048e59748f41635bcb9512ae33b540ae59b466aa..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_reset_controller_180
-hdl_library_clause_name = altera_reset_controller_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
deleted file mode 100644
index f0fadccebe3fb8ffeac074e8737d7861493ae913..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/compile_ip.tcl
+++ /dev/null
@@ -1,55 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
-
-vmap altera_common_sv_packages ./work/
-vmap altera_xcvr_atx_pll_a10_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_atx_pll_rcfg_opt_logic_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg
deleted file mode 100644
index 595a260842eec6a10f6cce32b8b94699306e5160..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_xcvr_atx_pll_a10_180
-hdl_library_clause_name = altera_xcvr_atx_pll_a10_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
deleted file mode 100644
index 4b48dd94a1cb96cd1d8df76253133875d40e9b00..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/compile_ip.tcl
+++ /dev/null
@@ -1,50 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
-
-vmap altera_xcvr_fpll_a10_180 ./work/
-
-#pll_xgmii_mac_clocks
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/mentor/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/mentor/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/a10_avmm_h.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/alt_xcvr_native_avmm_nf.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_180/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_180
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg
deleted file mode 100644
index 06f182471af951ce942b9aacb024d1315fa19bf0..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_170/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_xcvr_fpll_a10_180
-hdl_library_clause_name = altera_xcvr_fpll_a10_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
deleted file mode 100644
index 5a7cfcddb35cad8dfb5115ba6d248c1d4e7ed7b8..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/compile_ip.tcl
+++ /dev/null
@@ -1,98 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-vmap altera_xcvr_native_a10_180 ./work/
-vmap altera_common_sv_packages ./work/
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
-
-# common dependencies
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r_48
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r_24
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r_12
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r_4
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r_3
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# phy_10gbase_r
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
-
-# tse_sgmii_gx
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg
deleted file mode 100644
index eb5db3082a4b3930a9ea7375cadc8d1603538fca..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_xcvr_native_a10_180
-hdl_library_clause_name = altera_xcvr_native_a10_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
deleted file mode 100644
index c2e9b1f72dc71b7d4f9842d11d0db8d66ccb72eb..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/compile_ip.tcl
+++ /dev/null
@@ -1,44 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
-
-vmap altera_xcvr_reset_control_180 ./work/
-
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/mentor/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_180
- vlog -sv "$IP_DIR/../altera_xcvr_reset_control_180/sim/mentor/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_180
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg
deleted file mode 100644
index fe27ceef663f34a181c37534217f083153ea9d5c..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_altera_xcvr_reset_control_180
-hdl_library_clause_name = altera_xcvr_reset_control_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
deleted file mode 100644
index adeb79939f04f30c2b5748f06244e8511d6f3812..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/compile_ip.tcl
+++ /dev/null
@@ -1,40 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap channel_adapter_180 ./work/
-
- vlog -sv "$IP_DIR/../channel_adapter_180/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_180_bsi6toa.sv" -work channel_adapter_180
- vlog -sv "$IP_DIR/../channel_adapter_180/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_180_xbvi4ny.sv" -work channel_adapter_180
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg
deleted file mode 100644
index 553bb719ff1707b0b57f6d5102ec0cfac0e1ec79..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_channel_adapter_180
-hdl_library_clause_name = channel_adapter_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
deleted file mode 100644
index c721f083bd174f0c449ed3cecee604a0cfcc285f..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/compile_ip.tcl
+++ /dev/null
@@ -1,39 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/ ;# Assume library work already exist
-#
-
-
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
-
-vmap timing_adapter_180 ./work/
-
- vlog -sv "$IP_DIR/../timing_adapter_180/sim/ip_arria10_e1sg_ddr4_8g_1600_timing_adapter_180_osazali.sv" -work timing_adapter_180
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg
deleted file mode 100644
index 342089f106b5e0e44d6519ee855b20169b767440..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_170/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_e1sg_timing_adapter_180
-hdl_library_clause_name = timing_adapter_180
-hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
-synth_files =
-
-test_bench_files =
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
-
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
index 3ec2cd3bae0752cf489d438d600d0c3ceb7db2b9..252951861f9ca3ab5b35776197e58612f0661aa8 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index 0f031bde49a542f097e9d4f0ac44256925a630ba..9e1a2696f18af602ebbca6459ae455975896c9a5 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_clkbuf_global
-hdl_library_clause_name = ip_arria10_e1sg_clkbuf_global_altclkctrl_180
+hdl_library_clause_name = ip_arria10_e1sg_clkbuf_global_altclkctrl_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altclkctrl_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altclkctrl_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_clkbuf_global.qip
+ ip_arria10_e1sg_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys b/libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys
index 1cf25870c59b9b0f9ebf52e440f0ac70f4235924..fba6d6240d4474f8a9d40b51fb5cc7855f3c869a 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys
@@ -62,7 +62,7 @@
<module
name="altclkctrl_0"
kind="altclkctrl"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CLOCK_TYPE" value="1" />
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
index 3e33649f60f2659c1bd624a9ee30584f601033b4..c9a33bbdfc0710640b0f4e967376ce8a5627e40e 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_complex_mult.qip
+ ip_arria10_complex_mult.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
index 39c4b986148b4533268d1a5e27cd35494241f268..f9948fbc5e3c7baca8ad5b3306ddd48f0f972c16 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -29,9 +29,8 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/complex_mult/generated/sim"
- vmap altmult_complex_180 ./work/
-
- vlog "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_altmult_complex_180_myrk3hi.v" -work altmult_complex_180
-
-vlog "$IP_DIR/ip_arria10_e1sg_complex_mult.v"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
+vmap altmult_complex_170 ./work/
+ #vlog "$IP_DIR/../altmult_complex_170/sim/ip_arria10_e1sg_complex_mult_altmult_complex_170_myrk3hi.v" -work altmult_complex_170
+ vlog "$IP_DIR/../altmult_complex_170/synth/ip_arria10_e1sg_complex_mult_altmult_complex_170_myrk3hi.v" -work altmult_complex_170
+ #vlog "$IP_DIR/ip_arria10_e1sg_complex_mult_bb.v"
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
index c09f8f660fabe8930db6ffcea74be99cc0fb32d3..96be7f292600bd729d715fc0547932a51a884082 100755
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index bab3a669b232d9d650d41b2d8a3826d0eb4e6b9f..792d355bb4d0efa37cef0c9a1851f65e6e08589c 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_complex_mult
-hdl_library_clause_name = ip_arria10_e1sg_complex_mult_altmult_complex_180
+hdl_library_clause_name = ip_arria10_e1sg_complex_mult_altmult_complex_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_complex_mult.qip
+ ip_arria10_e1sg_complex_mult.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys b/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys
index 6156e6a7a678f7db192902f06ddcdd91e6a5832c..4c2b48c320c646ca6b0dfcede2ec1f1df80a18c1 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys
@@ -69,7 +69,7 @@
<module
name="altmult_complex_0"
kind="altmult_complex"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
index dbab4802e06e7a85e77241dfb0dc361040979b68..0cf7bb1d96d0e205fed5846d44f758f7996d0d20 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# OUTDATED AND NOT USED!!
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddio/generated/"
+ set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_150 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
index 389f44f5116766060cb0cb93ad685fa72bde71dc..38843a33037ea6f47ed7430e5ab1ce4d9a996502 100755
--- a/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
@@ -34,7 +34,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index 4b67f37fb858dbf912e4655ab5396f1be7fe655a..f2b64c3ae4e638f42d33e5e59a716b8107e00b42 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -18,8 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_ddio_in_1.qip
- generated/ip_arria10_e1sg_ddio_out_1.qip
+ ip_arria10_e1sg_ddio_in_1.qip
+ ip_arria10_e1sg_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys
index 0183a6f254443a99b9ead1cd5a454791f9d43c42..5561d1ae469ac5f25620b8e4b2931441361b674b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys
@@ -82,7 +82,7 @@
<module
name="ip_arria10_ddio_in_1"
kind="altera_gpio"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys
index 42fa9f2705de5bd485e7e1224b5d2602e15f3371..e212acf8eb33f43bf0018934f01ea7246163f977 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys
@@ -84,7 +84,7 @@
<module
name="ip_arria10_ddio_out_1"
kind="altera_gpio"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
index 46dff72ef5d8321a872ef7c08bb2f2f9cbe7c8a9..557a2cee6bc6ef567b2f7ba444044d119032baad 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
index 82efc278ce0f223c21003229d19c59d63a5eb4e1..710e1fb69caf0027cbe50a21396ebc375519fd94 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,12 +22,12 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
- file copy -force $IP_DIR/../altera_avalon_onchip_memory2_180/sim/seq_cal_soft_m20k.hex ./
- file copy -force $IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_seq_cal.hex ./
- file copy -force $IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_seq_params_sim.hex ./
- file copy -force $IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_6dhhhti_seq_params_synth.hex ./
+ file copy -force $IP_DIR/../altera_avalon_onchip_memory2_170/sim/seq_cal_soft_m20k.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_seq_cal.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_seq_params_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_seq_params_synth.hex ./
}
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
index 9e63a80dc1b25adab2fe4421e7810403b5eae868..9d98e72bcecf2225560e012317310689f02c6eee 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index 84d8e84cf00913102d41510c8e96640cfc3f6f7b..275820f5ff4a422634b9bd1f554d6dac51fd30c7 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_4g_1600
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_emif_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_emif_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_ddr4_4g_1600.qip
+ ip_arria10_e1sg_ddr4_4g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qsys
index 85a36dd86cbf0dbf3217012b1d40e64bf5c9be1b..f00d65e364a61380bf69b0c9ff72933243e47f4f 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qsys
@@ -152,7 +152,7 @@
<module
name="emif_0"
kind="altera_emif"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
index 9497e3c7cc7147645711e3e93c60b78aedee6453..70199c12f6c36eea29ee6b84339a3e62126d02a9 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
index 44a321affd24f73f3c64029e30bd6afd2b399b85..2063dbbb243b56e93f416e79f3e6ed35e7b412ff 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
index bbbc8b7d3aba357cd67070648e8a20a71822bce9..64364ce034a0cc001573064b4e3faf8751f931c8 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index 55e704816ea0711031170b91030cb90e1280cc42..20bde73a26a738087e0fef92ade0d8f7011ee8ff 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_4g_2000
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_180 ip_arria10_e1sg_altera_emif_cal_slave_nf_180 ip_arria10_e1sg_altera_avalon_onchip_memory2_180 ip_arria10_e1sg_altera_mm_interconnect_180 ip_arria10_e1sg_altera_reset_controller_180 ip_arria10_e1sg_altera_emif_arch_nf_180 ip_arria10_e1sg_altera_emif_180 ip_arria10_e1sg_altera_avalon_mm_bridge_180 ip_arria10_e1sg_altera_merlin_slave_translator_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_170 ip_arria10_e1sg_altera_emif_cal_slave_nf_170 ip_arria10_e1sg_altera_avalon_onchip_memory2_170 ip_arria10_e1sg_altera_mm_interconnect_170 ip_arria10_e1sg_altera_reset_controller_170 ip_arria10_e1sg_altera_emif_arch_nf_170 ip_arria10_e1sg_altera_emif_170 ip_arria10_e1sg_altera_avalon_mm_bridge_170 ip_arria10_e1sg_altera_merlin_slave_translator_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_ddr4_4g_2000.qip
+ ip_arria10_e1sg_ddr4_4g_2000.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qsys
index cc070e9d3891d6f60a4126ac435f54d8cb3dcfd4..58c2d117c77c3a6596a1de5a7b188153c95d7b7f 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qsys
@@ -152,7 +152,7 @@
<module
name="emif_0"
kind="altera_emif"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
index ef04250d0394ce6a84ea1163b80eef291e8d0bd2..529636a9ca1830f8688fe7fd4c8fe436d7f5bef2 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
index d384a4b5ea1bd06de5397111cb534b94d8e7c208..68e998bc99a6721279bace4a6dd4474f78e47d3e 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
index 92679228d07f5e9c5db6de3ee92f3ac367394f9b..cf24b8c0fc07ed16ecd535e3207b97793ffa5e4b 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index f77c4027e81d23165bf841059915fb2f00bcaf37..a1e0f76ebad8306d618fb203b9415aeeb017409a 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_8g_1600
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_180 ip_arria10_e1sg_altera_emif_cal_slave_nf_180 ip_arria10_e1sg_altera_avalon_onchip_memory2_180 ip_arria10_e1sg_altera_mm_interconnect_180 ip_arria10_e1sg_altera_reset_controller_180 ip_arria10_e1sg_altera_emif_arch_nf_180 ip_arria10_e1sg_altera_emif_180 ip_arria10_e1sg_altera_avalon_mm_bridge_180 ip_arria10_e1sg_altera_merlin_slave_translator_180 ip_arria10_e1sg_altera_avalon_sc_fifo_180 ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_180 ip_arria10_e1sg_altera_ip_col_if_180 ip_arria10_e1sg_altera_jtag_dc_streaming_180 ip_arria10_e1sg_alt_mem_if_jtag_master_180 ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_180 ip_arria10_e1sg_altera_avalon_packets_to_master_180 ip_arria10_e1sg_channel_adapter_180 ip_arria10_e1sg_timing_adapter_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_170 ip_arria10_e1sg_altera_emif_cal_slave_nf_170 ip_arria10_e1sg_altera_avalon_onchip_memory2_170 ip_arria10_e1sg_altera_mm_interconnect_170 ip_arria10_e1sg_altera_reset_controller_170 ip_arria10_e1sg_altera_emif_arch_nf_170 ip_arria10_e1sg_altera_emif_170 ip_arria10_e1sg_altera_avalon_mm_bridge_170 ip_arria10_e1sg_altera_merlin_slave_translator_170 ip_arria10_e1sg_altera_avalon_sc_fifo_170 ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_170 ip_arria10_e1sg_altera_ip_col_if_170 ip_arria10_e1sg_altera_jtag_dc_streaming_170 ip_arria10_e1sg_alt_mem_if_jtag_master_170 ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_170 ip_arria10_e1sg_altera_avalon_packets_to_master_170 ip_arria10_e1sg_channel_adapter_170 ip_arria10_e1sg_timing_adapter_170
hdl_lib_technology = ip_arria10_e1sg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_ddr4_8g_1600.qip
+ ip_arria10_e1sg_ddr4_8g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
index ab388d3ab2af3cc74d1ad20837ef2fd95a30993b..a252c4e3053ef132c7d6468c8fd85b4d79d59ee5 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
@@ -189,7 +189,7 @@
<module
name="emif_0"
kind="altera_emif"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
index 5798a026b414db3f79f7068f52ed8d56dd2bba27..9fc229d78e74f11fa0041ffe90f0771e0825e9f2 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
index c8089fe8591a6915d44e7381375adb56704a9671..668144a2846c594937bc0b1ccbba249873dce397 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
index 14eafe55890689b7f67158285dc8355731d25260..b1212614046a9bc1491c10d7e1fa6c4c74394290 100755
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index 9aaaa7d73e982c45d7eeac9554f082d7d5f95a14..305e04c17e4eb92033a4e4b8056d677bd4f16341 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_8g_2400
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_180 ip_arria10_e1sg_altera_emif_cal_slave_nf_180 ip_arria10_e1sg_altera_avalon_onchip_memory2_180 ip_arria10_e1sg_altera_mm_interconnect_180 ip_arria10_e1sg_altera_reset_controller_180 ip_arria10_e1sg_altera_emif_arch_nf_180 ip_arria10_e1sg_altera_emif_180 ip_arria10_e1sg_altera_avalon_mm_bridge_180 ip_arria10_e1sg_altera_merlin_slave_translator_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_170 ip_arria10_e1sg_altera_emif_cal_slave_nf_170 ip_arria10_e1sg_altera_avalon_onchip_memory2_170 ip_arria10_e1sg_altera_mm_interconnect_170 ip_arria10_e1sg_altera_reset_controller_170 ip_arria10_e1sg_altera_emif_arch_nf_170 ip_arria10_e1sg_altera_emif_170 ip_arria10_e1sg_altera_avalon_mm_bridge_170 ip_arria10_e1sg_altera_merlin_slave_translator_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_ddr4_8g_2400.qip
+ ip_arria10_e1sg_ddr4_8g_2400.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qsys
index e6d718357be18f390a6924bc53428e13c7052a5f..c2ee5866f903ba75a4a9d35756a7af3d97ba627b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qsys
@@ -160,7 +160,7 @@
<module
name="ddr4_inst"
kind="altera_emif"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/README.txt b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
index cfe2a2a2d88c7a058d3596d9b1297941b2b0e8a3..6db25b6412e89ebde6decb09c13f7e14890315b0 100755
--- a/libraries/technology/ip_arria10_e1sg/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
@@ -38,7 +38,7 @@ Contents:
The IP only needs to be generated with ./generate_ip.sh if it need to be modified, because the ip_arria10_fifo_*.vhd
directly instantiates the altera_mf component.
- The instantiation is copied manually from the generated/ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
+ The instantiation is copied manually from the ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
saved in the <fifo_name>.vhd file. So then the MegaWizard vhd file is overwritten, but that is fine because it is
no longer needed, it could easily be derived from the original in $UNB and it is still as a previous verion in SVN.
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
index 0a36be76c247ce189f600382c2e4aa58bea87b46..99b5070d9b65a3b4752d954b34f0821388d2d43b 100755
--- a/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
@@ -33,13 +33,13 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_e1sg_fifo_*.vhd directly instantiates
# the FIFO altera_mf component.
-# The instantiation is copied manually from the generated/ip_arria10_e1sg_ram_*/fifo_140/sim/ip_arria10_e1sg_fifo_*.vhd.
+# The instantiation is copied manually from the ip_arria10_e1sg_ram_*/fifo_140/sim/ip_arria10_e1sg_fifo_*.vhd.
# It appears that the altera_mf FIFO component for Arria10 can be synthesized similar as how it worked for Stratix IV,
# it is not necessary to use the generated qip file.
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.qsys b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.qsys
index c32f172ac8b37941d9b7e5466cbdd6a021b492f8..b3b1e81c48be3b75ae143a77c48090cef600d8df 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.qsys
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.qsys
@@ -71,7 +71,7 @@
<module
name="ip_arria10_fifo_dc"
kind="fifo"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.qsys b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.qsys
index fa9a47f2104a2c5c7ee765623ac504e587ebb743..1bf9442eec5497245bca8fb50803b9e176bc097d 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.qsys
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.qsys
@@ -71,7 +71,7 @@
<module
name="ip_arria10_fifo_dc_mixed_widths"
kind="fifo"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.qsys b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.qsys
index 7126359e3d2541c38b38ced4d8609255379e7b87..a695a2c1f1aa32157288f701814aebe025972e67 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.qsys
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.qsys
@@ -69,7 +69,7 @@
<module
name="ip_arria10_fifo_sc"
kind="fifo"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
index 381c1944ae2303a406eb431687bc2f7ea6d94bf4..542532efc514ad9f7d2b0f2a68598d2a290c5099 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
index 6bac379b60d17aa26e6c87e045b2e288468a3986..c5d32303594607539ab7115f55e9094052c50054 100755
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index 43fae1307c1e72f51297b42ebb0532da24497694..63faeffb57e4b467031ecf483ba9dab407a57786 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_asmi_parallel
-hdl_library_clause_name = ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180
+hdl_library_clause_name = ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_asmi_parallel_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_asmi_parallel_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_asmi_parallel.qip
+ ip_arria10_e1sg_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/ip_arria10_e1sg_asmi_parallel.qsys b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/ip_arria10_e1sg_asmi_parallel.qsys
index 459e8dd2909a581eacea94d99bd18f989298ba78..7cd26610f9480f4f2bb1f3b682e4f362f7615a4d 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/ip_arria10_e1sg_asmi_parallel.qsys
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/ip_arria10_e1sg_asmi_parallel.qsys
@@ -144,7 +144,7 @@
<module
name="asmi_parallel_0"
kind="altera_asmi_parallel"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
index 71a2b64c03778c01e9f8bb3b15bec0e26f5874b8..758af045ba9ba6c8dca1890edddaf80a2561f48d 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
index fdc94c04b3261ea07d23656add6452bcd1cdd103..f9d585f8bb83069e338337a5dd7892a869ea1b72 100755
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index 90a4be835a700394d83235a9d5b553c36833857d..dd59deef2fe4eb7f0d16b3cc011118682c5d4e83 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_remote_update
-hdl_library_clause_name = ip_arria10_e1sg_remote_update_altera_remote_update_180
+hdl_library_clause_name = ip_arria10_e1sg_remote_update_altera_remote_update_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_remote_update_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_remote_update_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_remote_update.qip
+ ip_arria10_e1sg_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/ip_arria10_e1sg_remote_update.qsys b/libraries/technology/ip_arria10_e1sg/flash/remote_update/ip_arria10_e1sg_remote_update.qsys
index 122c6cd3dc0b2b59df408727ea57ad9f6d4290c3..566f27ac6dde1667e544488338001abb178f6080 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/ip_arria10_e1sg_remote_update.qsys
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/ip_arria10_e1sg_remote_update.qsys
@@ -113,7 +113,7 @@
<module
name="remote_update_0"
kind="altera_remote_update"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
index 6f767532c6ebc07ad9a9a3e7d61c006dbb22c588..dbdd811b48868305daff48eb4344d09486017c65 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
index 739ce3f27efc0f9fcd25939b433b385a61bf4e2c..a64d398529413e191b164a5a64c1f2e0a13730f4 100755
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index e3acc9f80d480f588ba8314286677ff7d41efe31..bd4e4eff0a12e8454caa3cd461a4bbc95967a1f9 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_fractional_pll_clk125
-hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_fractional_pll_clk125.qip
+ ip_arria10_e1sg_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qsys b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qsys
index d26f1522677c7ea851cf860675ad14b372922d53..5d978f4e94c999fabddf43af3dbaef9288088884 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qsys
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qsys
@@ -161,7 +161,7 @@
<module
name="xcvr_fpll_a10_0"
kind="altera_xcvr_fpll_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
index 5c8674a583e8f07a28241f7d66216cb166e01df2..46788a5560a9cfd179d8597bd11e2851093f59ee 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
index b5aa72958821b47ba664842561a72e3b3a410a9a..10802670a735484a08fb1aca9eb9bc54aed6a010 100755
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index 7d8bf1759becd181bb699d1b81cc02c65ee34df2..0b2de2be9b8a028e017091798a72204ddb256c45 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_fractional_pll_clk200
-hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_fractional_pll_clk200.qip
+ ip_arria10_e1sg_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qsys b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qsys
index 9ca6a9ba35f1b1a41731976c8c66ed64772e9228..9d07e994b96e751585ad5529742d30f0935f69c6 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qsys
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qsys
@@ -141,7 +141,7 @@
<module
name="xcvr_fpll_a10_0"
kind="altera_xcvr_fpll_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
index 1809358e9cffbc914b28099a977ad0b8ff8cc4b6..c775402d02b409cbc5f046ee91549577ddf8c52a 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_mac_10g.qip
+ ip_arria10_mac_10g.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
index afd8e94094f136d9e28b77d62ef95bd1bd50b558..311722c106b8d981b268dd4df96fd89f5e3df21e 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_mac_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
index 2cfec0ecc4d8508d801ba069ccb5b829639b30f6..510c550c2cde57fafd8285beecd7edfdd9c5c951 100755
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2a" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index 7b92d3e261a43f1c62e0f53ec9ea6ad5150bf469..8e576bcb2afb45ca95bed3f02aed5fb083e571a1 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_mac_10g
-hdl_library_clause_name = ip_arria10_e1sg_mac_10g_alt_em10g32_180
+hdl_library_clause_name = ip_arria10_e1sg_mac_10g_alt_em10g32_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_alt_em10g32_180
+hdl_lib_uses_sim = ip_arria10_e1sg_alt_em10g32_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
@@ -19,7 +19,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_mac_10g.qip
+ ip_arria10_e1sg_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/ip_arria10_e1sg_mac_10g.qsys b/libraries/technology/ip_arria10_e1sg/mac_10g/ip_arria10_e1sg_mac_10g.qsys
index 197ff78c075968e0015721ade0100b91bf51cbfd..5f0f03560f09dc265fb23833c704ef9897cbcf19 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/ip_arria10_e1sg_mac_10g.qsys
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/ip_arria10_e1sg_mac_10g.qsys
@@ -226,7 +226,7 @@
<module
name="alt_em10g32_0"
kind="alt_em10g32"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="ANLG_VOLTAGE" value="1_0V" />
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
index 67f2e7f33ebfb826d99049f0c64c0eb9d3a1229e..bd817b8d2cd20551226ebd95aba027838cb867cd 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
@@ -29,11 +29,11 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/mult_add4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap ip_arria10_e1sg_mult_add4 ./work/
-vmap altera_mult_add_180 ./work/
+vmap altera_mult_add_170 ./work/
- vcom "$IP_DIR/../altera_mult_add_180/sim/ip_arria10_e1sg_mult_add4_altera_mult_add_180_dl6xbqi.vhd" -work altera_mult_add_180
+ vcom "$IP_DIR/../altera_mult_add_170/sim/ip_arria10_e1sg_mult_add4_altera_mult_add_170_dl6xbqi.vhd" -work altera_mult_add_170
vcom "$IP_DIR/ip_arria10_e1sg_mult_add4.vhd" -work ip_arria10_e1sg_mult_add4
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
index b52b5b14f7ce153c51e4d79b634da2d32ce24dea..7e679ec72fb2adcb72f24126a5787db94a765e6b 100755
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4.qsys b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4.qsys
index 5cbdca8d075a45f8f87abd9d9decbc2ce4088806..833254f3e006c414c9ebbbbe4b1c9c4725b71aad 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4.qsys
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4.qsys
@@ -88,7 +88,7 @@
<module
name="mult_add_0"
kind="altera_mult_add"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="accum_direction" value="ADD" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
index 41b87622bf791973ba65e36ee30cfe3553688903..4af0090eb67e15cf0b92f928b9b96cb073b02fd2 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
index 310c756aee8f1077260d28b8c9c81b0481f723c1..7f651810baa949a80b1f767b82d0dab38eb6a9c7 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index 0dd4c8210f4d3e8acd320c81a99290f4b1afc82e..29c2cd4a068770e35a594ca53ff4b7cc26e20739 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r.qip
+ ip_arria10_e1sg_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qsys
index d35d88f6c01370d7e100f36a1621e5e25569e3a1..bfd82d2a4e7a8ea9b50850bef709d35ce65f13a3 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qsys
@@ -342,7 +342,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
index 32a75009b879b0781360e5b508fae141461c6ff0..fa707de56d193d75b1d11a379d6acadaf043268f 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
index 0102778d11366e4bfbd71d13d75eeab70694d386..0ecdbd7fef0dbff418e3b608dcd9b4d52f40efa2 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index 37eab001c9dd01855a144a65122a09d409d1db25..adcef5d58ce4b826862069d9d90f8adb80130a51 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_12
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r_12.qip
+ ip_arria10_e1sg_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qsys
index 65d72ddf0c91aef04c57d1261fb79b5e17b1bf74..7a766f54c37d533f4dfeba99a9d9d4e9ee8ad25a 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qsys
@@ -365,7 +365,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
index 9cc7830fe8844557b589aeecb23e95ef7125f184..6c29765871e3cf5a018e61d14f84dcaa9b818458 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
index 58b28fabec4df5c2560be749a258201053ea0123..32c3254360f24ef9a15f1372ca50500e1be94abc 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index 80f43504e4df8852e5ce06d4e46ee4bb51bf89cd..84069a7a0dd4c0e7bbb3fff7d886f23857d6b1a0 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_24
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r_24.qip
+ ip_arria10_e1sg_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qsys
index bf0575a0f086b2eeb846099399ef397c9d299f07..8a5f4c9e7bb1d6443c31335454626c8173b2a593 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qsys
@@ -365,7 +365,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
index 4a869f57e294a9b6176048af1b831e03e817c540..c14dae50ea529093b6a02d8f1fada3df281e31b7 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
index 1bb64ac723956180d9e4602cdf252553892956d4..3240ee8311c58bb31337e23b87fc67f251ebf133 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
index 8cf820104d501cff9db6df2779c4961bbef211e3..72f4164679e9399945d6dfe164cbd5f840f2c17e 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_3
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,4 +16,9 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r_3.qip
+ ip_arria10_e1sg_phy_10gbase_r_3.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e1sg_phy_10gbase_r_3.qsys
+
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys
index 896e306c1e956daf7aed104b58c205e410fa1d6f..8eebf9a668697b20b4ab75e28bac0ba4af2ee66d 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys
@@ -362,7 +362,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
index 4f4b143abd07af4b14d7ddf5dd457be853d7ee04..0d32e10667d0112a80bf821034e4b7b25a45f2f8 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
index ee4b74eceb498217f48d2c270e7c5562aafa367b..445f2fed57c45685fc5e2a62706da6e6f271a308 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index 6fd79d3c85dc251f15c6d7ca199c98f080a11ed3..40308d30b68679fb886a232e941d7c24310b6ea1 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_4
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r_4.qip
+ ip_arria10_e1sg_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qsys
index 1b79db2c9048d57f196ea65a4d35ffce48df72d6..bcc15326c1b4a8e091c27af4549ecdc19311df2d 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qsys
@@ -365,7 +365,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
index f9487e1a4f415cefacc85f516d18a398a2d04f1e..0e3facb2982fbc63dcc7a796dcc53d8ca50fce2f 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
index c0fc1047afd6bf1b1b19a135622dfd3c3e0a7825..552a7a512e3009ede312770acde9f9377922acc8 100755
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index 78002d0526fe6b8e98a11f90758cfb4ea6413184..a439f350cf4550de5ae878e677cdcdc3357b3ac2 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_48
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_phy_10gbase_r_48.qip
+ ip_arria10_e1sg_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qsys
index 8f2f6de609a423c1003bb9a42571518abb6ca288..78c428793e49c141363a61efbe17a76aa676c763 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qsys
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qsys
@@ -365,7 +365,7 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="anlg_enable_rx_default_ovr" value="0" />
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
index 643d6d409661103826c47e907c4209d7157c97c6..5f91ef1076a26c387eb4405eb60452bf9cb8284b 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
index a00ef44c622996885b9eeb43b2850f383a7fab13..17e6673b38fc72cc8c74d22859e0d0d01adcdd88 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index 80efe2ac97cf137a6f2c661631f51c555101ae08..4be460501521dd1555de1c8aeed26918f8e5263e 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_pll_clk125
-hdl_library_clause_name = ip_arria10_e1sg_pll_clk125_altera_iopll_180
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk125_altera_iopll_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_pll_clk125.qip
+ ip_arria10_e1sg_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/ip_arria10_e1sg_pll_clk125.qsys b/libraries/technology/ip_arria10_e1sg/pll_clk125/ip_arria10_e1sg_pll_clk125.qsys
index 4ec5c79a3ec0c3d64dc7ad756e14237a4b9ce1c9..55d16c8d49926b812423ef5706b9f7aa675e185d 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/ip_arria10_e1sg_pll_clk125.qsys
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/ip_arria10_e1sg_pll_clk125.qsys
@@ -122,7 +122,7 @@
<module
name="iopll_0"
kind="altera_iopll"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="gui_active_clk" value="false" />
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
index 281a4c3d46f377ddc12a9d0f1ccabb0c94fcbee6..70a4ab66a1736b50d1b62dee04122bb0f90bc0a5 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
index cf60d4df54f999d0e1e0ad17bc20c97afd0d79fb..33378d48f5938d5fdae540eb07aae6262bf7772c 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index d81c14c1995e51a646ac85b5ab45c7094e005fe6..214a794d798361aadcfa5766d402f8b67c798f00 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_pll_clk200
-hdl_library_clause_name = ip_arria10_e1sg_pll_clk200_altera_iopll_180
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk200_altera_iopll_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_pll_clk200.qip
+ ip_arria10_e1sg_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/ip_arria10_e1sg_pll_clk200.qsys b/libraries/technology/ip_arria10_e1sg/pll_clk200/ip_arria10_e1sg_pll_clk200.qsys
index c3f3936e0c8688b287e2cc99e7acdc8f2e52fb09..f835c769ae1f9779c3730f9fb975eab2ea699656 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/ip_arria10_e1sg_pll_clk200.qsys
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/ip_arria10_e1sg_pll_clk200.qsys
@@ -106,7 +106,7 @@
<module
name="iopll_0"
kind="altera_iopll"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="gui_active_clk" value="false" />
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
index 278ea6499a777256e438d3135cb842e2f2b969ea..6072afd658dbdf8a395def0cb7fe1156729d30a7 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk25.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
index 525783f424d60b6f4bd8baeb046ac03612b9a5e5..ef4a1a818453dc0c080036ebb3fa20c7e51f4a47 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index c5e5ebeb0a694ba7efa89de4cd568531e2e93eee..0c91441dd89419cb549eafd9ed7622576c07f2dc 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_pll_clk25
-hdl_library_clause_name = ip_arria10_e1sg_pll_clk25_altera_iopll_180
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk25_altera_iopll_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_iopll_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_pll_clk25.qip
+ ip_arria10_e1sg_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/ip_arria10_e1sg_pll_clk25.qsys b/libraries/technology/ip_arria10_e1sg/pll_clk25/ip_arria10_e1sg_pll_clk25.qsys
index 3665b4c978c98f0b76196b7fe897e341316f4c59..e209c009248a1ed9c686a8f482a869fcf180c684 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/ip_arria10_e1sg_pll_clk25.qsys
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/ip_arria10_e1sg_pll_clk25.qsys
@@ -122,7 +122,7 @@
<module
name="iopll_0"
kind="altera_iopll"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="gui_active_clk" value="false" />
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
index 36568c9bf3567d9b7022bbb4382eb89145f089d1..14b82a90c79bd1f39eea676476d2dcfb58438b8c 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_xgmii_mac_clocks.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
index 37e803de614ae1bfdf99137ad3bbee1db21f944a..77f31d835c09eb748bbf8d85c9d4b808bdd3cdfa 100755
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index 927abcb66594d08b2ba9c5e3b50aba08cbed0bf6..4f77d20d79315951e829e76b2b2059122749ce31 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_pll_xgmii_mac_clocks
-hdl_library_clause_name = ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_fpll_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
+ ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys
index 74baeb3555dfee5e9bd5df6c80513166802361a7..3a2a961e1b86de4138fff39259a779b2cebcea7b 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys
@@ -117,7 +117,7 @@
<module
name="xcvr_fpll_a10_0"
kind="altera_xcvr_fpll_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
diff --git a/libraries/technology/ip_arria10_e1sg/ram/README.txt b/libraries/technology/ip_arria10_e1sg/ram/README.txt
index a9fe41102a7d2cec63b7c2f3846b28447c1b4bc0..24ad4ab94e542bd2d642eaa079f4e18624d8c163 100755
--- a/libraries/technology/ip_arria10_e1sg/ram/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/ram/README.txt
@@ -32,7 +32,7 @@ Contents:
if it need to be modified, because the ip_arria10_ram_*.vhd directly instantiates the altera_syncram component.
- The instantiation is copied manually from the generated/ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
+ The instantiation is copied manually from the ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
diff --git a/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
index a1a766d44dbaf7e52a90f41edb926a99ed423840..86a387538bc41b25ef667441212a32fd50a7a8e2 100755
--- a/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
@@ -33,13 +33,13 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_e1sg_ram_*.vhd directly instantiates
# the altera_syncram component.
-# The instantiation is copied manually from the generated/ip_arria10_e1sg_ram_*/ram_2port_140/sim/ip_arria10_e1sg_ram_*.vhd.
+# The instantiation is copied manually from the ip_arria10_e1sg_ram_*/ram_2port_140/sim/ip_arria10_e1sg_ram_*.vhd.
# It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
# that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg
index 84cf6b82163e82efbe0b3069721d1bb4c89dd9fb..11a6f461518fbf997aadf12bf0b161adf4deaff5 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg
@@ -22,11 +22,3 @@ test_bench_files =
[quartus_project_file]
-
-[generate_ip_libs]
-qsys-generate_ip_files =
- ip_arria10_e1sg_ram_crwk_crw.qsys
- ip_arria10_e1sg_ram_crw_crw.qsys
- ip_arria10_e1sg_ram_cr_cw.qsys
- ip_arria10_e1sg_ram_r_w.qsys
-
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.qsys
index c41f1aa04cb1b28a4dcd37464f1224f81a4f926d..e6b4c25eb21de5744781ba30c508f8afd28b29a5 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.qsys
@@ -67,7 +67,7 @@
<module
name="ram_2port_0"
kind="ram_2port"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
index 3baa3a14e0b0a9ec4a20e5177b75c42d02d16d55..5f5dcb6d0e8ae9c0c378f6905943a4ed94b6a836 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
@@ -99,7 +99,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e1sg_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e1sg_ram_cr_cw/ram_2port_140/sim/ip_arria10_e1sg_ram_cr_cw_ram_2port_140_72tpmcy.vhd
+ -- Copied from ip_arria10_e1sg_ram_cr_cw/ram_2port_140/sim/ip_arria10_e1sg_ram_cr_cw_ram_2port_140_72tpmcy.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.qsys
index 879e2677806b245d64de57698793f23fce63bd96..86b7dccc80b37c2569cd937d51895c3d4755a806 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.qsys
@@ -70,7 +70,7 @@
<module
name="ram_2port_0"
kind="ram_2port"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
index bd96396a6d3af597ad880231cf532864d444cb54..509a4f558637055114541f5dfb39d98cebcb5e22 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
@@ -115,7 +115,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e1sg_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e1sg_ram_crw_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
+ -- Copied from ip_arria10_e1sg_ram_crw_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.qsys
index db1029e58fc6e3b3315b4336f0cc8edbccbd20fa..3d55a54be3b06c785420a70245769e1932b9fc5a 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.qsys
@@ -69,7 +69,7 @@
<module
name="ip_arria10_ram_crwk_crw"
kind="ram_2port"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
index be1ddf85cda316dfac5056ad845597a954dea5e8..d07aec2232cc1a272460267d0318fae56bb73121 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
@@ -95,7 +95,7 @@ ARCHITECTURE SYN OF ip_arria10_e1sg_ram_crwk_crw IS
BEGIN
- -- Copied from generated/ip_arria10_e1sg_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
+ -- Copied from ip_arria10_e1sg_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.qsys
index 7b9ab891b0f36d695746f497185f419aa22b67d4..989d8e074ebf9ffe3ac60a47d47c637cb69e7bd6 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.qsys
@@ -66,7 +66,7 @@
<module
name="ram_2port_0"
kind="ram_2port"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
index 3b9707e7e5c29ef5d09d4063871b49e9d3213633..4abdf45bd9f0eea2ac94612d7d51d43faeac95ca 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
@@ -96,7 +96,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e1sg_ram_r_w : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e1sg_ram_r_w/ram_2port_140/sim/ip_arria10_e1sg_ram_r_w_ram_2port_140_hukd7xi.vhd
+ -- Copied from ip_arria10_e1sg_ram_r_w/ram_2port_140/sim/ip_arria10_e1sg_ram_r_w_ram_2port_140_hukd7xi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
index 94b9083df43cb6ca7b4128d4cb4b644993e11fc4..9718b9d6eb70f446e6ae622866ff750edaee38a5 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
@@ -29,11 +29,11 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/temp_sense/generated/sim"
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/temp_sense/generated/sim"
-vmap altera_temp_sense_180 ./work/
+vmap altera_temp_sense_170 ./work/
- vlog "$IP_DIR/../altera_temp_sense_180/sim/altera_temp_sense.v" -work altera_temp_sense_180
+ vlog "$IP_DIR/../altera_temp_sense_170/sim/altera_temp_sense.v" -work altera_temp_sense_170
vcom "$IP_DIR/ip_arria10_e1sg_temp_sense.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
index be991c110a1a3a0163771a5a066f9fe4cb0c18d6..ab8fbc6a740fbfb1b4f48a70f96ec45a4b5d0006 100755
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index ee2d261c6731446f421a61e7f42ec872e6086b8d..3a72010b5e1f14fc478b5323c35a49670557c9a9 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_temp_sense
-hdl_library_clause_name = ip_arria10_e1sg_temp_sense_altera_temp_sense_180
+hdl_library_clause_name = ip_arria10_e1sg_temp_sense_altera_temp_sense_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
@@ -15,9 +15,4 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_e1sg_temp_sense.qip
-
-[generate_ip_libs]
-qsys-generate_ip_files =
- ip_arria10_e1sg_temp_sense.qsys
-
+quartus_qip_files = ip_arria10_e1sg_temp_sense.qip
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/ip_arria10_e1sg_temp_sense.qsys b/libraries/technology/ip_arria10_e1sg/temp_sense/ip_arria10_e1sg_temp_sense.qsys
index 7b8c083b6e902df40b09f85c617530d46efa774a..5b698e50ad85387b3fd8e56d8cd8ba761d471361 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/ip_arria10_e1sg_temp_sense.qsys
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/ip_arria10_e1sg_temp_sense.qsys
@@ -71,7 +71,7 @@
<module
name="temp_sense_0"
kind="altera_temp_sense"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
index 63f8171a4bf4727b6a3e1038b32adab99cf003d0..e98b88b1eb1e257119ab091ea1c60683e39cbf69 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
index c4af138a6c65124de1d44c21ae9504a8bd0014e6..12de447a123ef957c2f267135432bb1c783a31c9 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index 6320ca76b9f45bea2158e21e3842e9a17eec6c93..b5d432d88ed46cad07bcc8c9eaa3a52e350d5646 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_pll_10g
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_atx_pll_a10_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_atx_pll_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,9 +16,4 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_pll_10g.qip
-
-[generate_ip_libs]
-qsys-generate_ip_files =
- ip_arria10_e1sg_transceiver_pll_10g.qsys
-
+ ip_arria10_e1sg_transceiver_pll_10g.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qsys
index 10bfe002093b4e203afcaad95eeeac029a833488..43c9588dc0f7dd6a41150e697b43ac039d84db54 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qsys
@@ -145,7 +145,7 @@
<module
name="xcvr_atx_pll_a10_0"
kind="altera_xcvr_atx_pll_a10"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
index 01c8d37521f992435ab8396cf90db3ee96a0f3b6..678140bfc245d49047c3edcbdb4a7a71199cfa32 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_1.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
index bdf2f728e8449b0d21584605d12dbef6e03b8b50..17e84e3a490d62221312a8fcd6301aa6a4c23561 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 74d008c0b0570beb81710e40ef9d5ae0e7faa238..e8426aa9360de1aa0b918a3ad0bf0c4a0a7a3694 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_1
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_1.qip
+ ip_arria10_e1sg_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qsys
index f3228f1b49a173a3e19b5f2ea6b37405315151f3..cb5c62e4f1fb3583bcc307165b9debc1a5f2187c 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qsys
@@ -146,7 +146,7 @@
<module
name="xcvr_reset_control_0"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="1" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
index b4cc6457dcd4c57e6b57dbea613e3b513c8031d8..8fb9880e95d441d8d63a9918a8c5614d8574a989 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
index 9dc526c3bb016f14dcb303f4b6696292e9c144da..db50fda3d1c23b1fba99b29b706585e04f519493 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index 2e3128afbed942cf97b58100729f5106f6a789d5..da3c79135144752e96e7f8f0772098d2440287b5 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_12
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_12.qip
+ ip_arria10_e1sg_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qsys
index 7954d06890b644b18c7e85f237e73af599b9aeed..d2eed5f40e45a4faf0315a3da3047c6f895a9104 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qsys
@@ -146,7 +146,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="12" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
index 21b8cb5187edd66c106dc61f19d2d268d77707b9..97fd1d1678d0a3d3541741997b6a3510d21ba8d2 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
index ab440cf7a0b3648362abd11490c50654fe6e7af4..761d94c86955a2bfa768b6d837eb61929e4c33eb 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index 0ecb1f702169e10eec7a8c87c3f626438f6e210d..d6ecda1740e2f11131ac7bbd4160da6961e53e3b 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_24
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_24.qip
+ ip_arria10_e1sg_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qsys
index 40028b0f20493ca200524e441f1b910fb3fffdda..b9c81b794ab9ae7c0a24de1354d0bd2acadfc416 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qsys
@@ -146,7 +146,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="24" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
index aed0f2bedc861a172f400a7b033fc16ee0c4c31c..22bbf7ef66677c2855dfb66b67bb444dc710b195 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
index db457e873cb8006eed2d2041e12c506a2053c706..ed92ce368e17e8b8bf6acf9fefcfe24075b18816 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
index 38bd151d83cc4501c75b9252039996355014a3b6..c4267c2954070e7d4c923861ce16605cae150ead 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_3
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,4 +16,4 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_3.qip
+ ip_arria10_e1sg_transceiver_reset_controller_3.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys
index 786d71495f5766a8d4074b7d1e7b0f6057610a5d..fad8e19b9afb31ddf77798dc836c97285810e38d 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys
@@ -143,7 +143,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="3" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
index a4e0bc1b15fdf7df5c6278a223d9e2c5819f79c8..bc16814fafb26b87f94dd01f96af62c511511bd0 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
index cb635dde75cc1dcfefbf57ef9d0468b25c364e98..ad1d84d8d18b04d91936446ff8dfbdf90c3448eb 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index 16d8fe368695dbf38fb4ccb641beddbc9fc20bcc..83fd058fc887281ab32326c47a49742272d3ff0f 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_4
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_4.qip
+ ip_arria10_e1sg_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qsys
index d05fec4afa392e37fba1a7dcea9a188716bb74fe..5e62c4549af4e2d739a118472fccd0aba2fc4038 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qsys
@@ -146,7 +146,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="4" />
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
index 7ef9776084c464a25bafca2158d2c0e23e9e54ea..5017d0f346ce8b63f2e186bc175664be6a001ae1 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
index 9aac11c07a0f4e0f5737a7ff00070133a58c5e4b..81f461f352dfdcb41c9d6b086edea7f1b2c374b7 100755
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index 063f94d4bfd56ffd8469c0c067293f631bb17622..256927382bf0ba63de15290146211e16e58f0f6f 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_48
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_transceiver_reset_controller_48.qip
+ ip_arria10_e1sg_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qsys
index 4878d28ba3e59f9e1362546417d5f126ed41a524..c755b0dcca123486c8b30aff389ac8299d95dd13 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qsys
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qsys
@@ -146,7 +146,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="48" />
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
index fcc8f3f3cb628213365ad645c6cf00e17de43a55..835fedcf83125f212e39bb434eb79833811655ac 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_gx.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
index e949f73d028b9df820fbd5f549a5538d4c1bc84b..91152f6cd89e4dad4f848dd56816f60f2499bb8d 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index 78f0ff306fdf011ded939709d3f2748b8d855521..fc7ebd16d8d8f237648e24623e5568530c44b69e 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_tse_sgmii_gx
-hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180
+hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170
hdl_lib_uses_synth = common
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_eth_tse_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_eth_tse_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_tse_sgmii_gx.qip
+ ip_arria10_e1sg_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qsys b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qsys
index 2756d70a1d47b2d2aa440dac84fd53ff95937995..748cbd757908a93619246e421dba64690d8a3647 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qsys
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qsys
@@ -283,7 +283,7 @@
<module
name="eth_tse_0"
kind="altera_eth_tse"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
index 28a6acf47c7a62f3574f8c9277d30ac644faa22e..d57ca28bd96dae9bc9b2ec49e9737dad89381d9f 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_lvds.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
index 27c0af99a90f57741a253723098cd21a66b36dcc..759e0042528a23b777bec5d2baed1fc684275a83 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index 2a4918678b62fdca47657c1453a1108a87299026..ab4006d1918b427283c9cc142d6cc74069c47356 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e1sg_tse_sgmii_lvds
-hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180
+hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170
hdl_lib_uses_synth = common
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_eth_tse_180
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_eth_tse_170
hdl_lib_technology = ip_arria10_e1sg
@@ -18,7 +18,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e1sg_tse_sgmii_lvds.qip
+ ip_arria10_e1sg_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qsys b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qsys
index 5bffe555b9181baaf071a1399621a0696cfea1a2..51fe979317c23112d3ae9ed67fa1a7c2b784fe65 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qsys
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qsys
@@ -199,7 +199,7 @@
<module
name="eth_tse_0"
kind="altera_eth_tse"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
index 833e8341c5f08a098656ebc3fdad43d9edafe880..59e6164425ff4c6a238c56fe59f5d253936c6af8 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
@@ -29,19 +29,19 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/voltage_sense/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/sim"
vmap ip_arria10_e1sg_voltage_sense ./work/
-vmap altera_voltage_sensor_180 ./work/
-vmap altera_voltage_sensor_control_180 ./work/
-vmap altera_voltage_sensor_sample_store_180 ./work/
+vmap altera_voltage_sensor_170 ./work/
+vmap altera_voltage_sensor_control_170 ./work/
+vmap altera_voltage_sensor_sample_store_170 ./work/
- vlog -sv "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/altera_voltage_sensor_control.sv" -work altera_voltage_sensor_control_180
- vlog -sv "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/voltage_sensor_avalon_controlr.sv" -work altera_voltage_sensor_control_180
- vlog -sv "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/voltage_sensor_wrapper.sv" -work altera_voltage_sensor_control_180
- vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store.sv" -work altera_voltage_sensor_sample_store_180
- vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store_ram.sv" -work altera_voltage_sensor_sample_store_180
- vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store_register.sv" -work altera_voltage_sensor_sample_store_180
- vcom "$IP_DIR/../altera_voltage_sensor_180/sim/ip_arria10_e1sg_voltage_sense_altera_voltage_sensor_180_hjr63vq.vhd" -work altera_voltage_sensor_180
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/altera_voltage_sensor_control.sv" -work altera_voltage_sensor_control_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/voltage_sensor_avalon_controlr.sv" -work altera_voltage_sensor_control_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/voltage_sensor_wrapper.sv" -work altera_voltage_sensor_control_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store.sv" -work altera_voltage_sensor_sample_store_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store_ram.sv" -work altera_voltage_sensor_sample_store_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store_register.sv" -work altera_voltage_sensor_sample_store_170
+ vcom "$IP_DIR/../altera_voltage_sensor_170/sim/ip_arria10_e1sg_voltage_sense_altera_voltage_sensor_170_hjr63vq.vhd" -work altera_voltage_sensor_170
vcom "$IP_DIR/ip_arria10_e1sg_voltage_sense.vhd" -work ip_arria10_e1sg_voltage_sense
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
index 2aa4ddd7b16c29497d49708cc8d0a65c6513aabc..df1e1b6ff727ca0cd5c9bc91047f547d0ff2fb9b 100755
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
@@ -31,7 +31,7 @@
#
# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL_GEAR}/quartus/set_quartus unb2b
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index 5e1e7faff9dfdb4948a06960f9645695bca7c5f6..150159a14e5e445da6e35f14729731734d5b0818 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_voltage_sense
-hdl_library_clause_name = ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180
+hdl_library_clause_name = ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
@@ -16,7 +16,7 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_e1sg_voltage_sense.qip
+quartus_qip_files = ip_arria10_e1sg_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/ip_arria10_e1sg_voltage_sense.qsys b/libraries/technology/ip_arria10_e1sg/voltage_sense/ip_arria10_e1sg_voltage_sense.qsys
index a1fed7433ec56fd49fbd75bd01ff03573d1a7bf1..0785279882884e626aebcb81d18313454706cbf1 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/ip_arria10_e1sg_voltage_sense.qsys
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/ip_arria10_e1sg_voltage_sense.qsys
@@ -132,7 +132,7 @@
<module
name="voltage_sensor_0"
kind="altera_voltage_sensor"
- version="18.0"
+ version="17.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
index 53c76e2b5ea78f85a2131a8aae684dd5015cd30a..7ae5ccdb0110507c116a5516c53b54a7644de291 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/clkbuf_global/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
index 66d47d1ae30c2ee355111b4bec569c5a9625eef2..109d6d33f6e69eeb5ff6ea97c62d103cbe51ed8a 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_clkbuf_global.qip
+ ip_arria10_e3sge3_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
index 3e33649f60f2659c1bd624a9ee30584f601033b4..c9a33bbdfc0710640b0f4e967376ce8a5627e40e 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_complex_mult.qip
+ ip_arria10_complex_mult.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
index 7692d23a29ff8badebfed871757a5b20b7d21ad5..57832897c9e03dacb771638be58eac6e5f950b5e 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/complex_mult/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
index 28ead31eedbea2ad2a508de5fc900db275c578b8..a9a34dbda047cd800f4a536b461a62de82b713b2 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_complex_mult.qip
+ ip_arria10_e3sge3_complex_mult.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
index 4a9ef46272c8d914fcb19512e69b2798f61447a8..aa2dd948bc10c19bcbf6eca5f43b580cc89e8c57 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddio/generated/"
+ set IP_DIR "$env(HDL_BUILD_DIR)/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
index d053102ed70097bc9fb20a72fa3c22aeb06938ec..5c041edb861d2ce9b4b87e35ee81629134c6fa2b 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
@@ -18,8 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_ddio_in_1.qip
- generated/ip_arria10_e3sge3_ddio_out_1.qip
+ ip_arria10_e3sge3_ddio_in_1.qip
+ ip_arria10_e3sge3_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
index 6d0ae35297df83f743aa2bd2865b44e355b95eda..f9daedf909c3374e88c54a2db2a5788038997cdf 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
index 8c69969d8b207d4fd80cea4b663f74e91b07b3b0..960d695d93ac14ac14d9fca19cb02da3dde50874 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
index 20a085ab6473103e6ee3f9a3078f5c2695a518d3..dd9a5269ec2975720a5adb4402f5d17b2a6292d4 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_ddr4_4g_1600.qip
+ ip_arria10_e3sge3_ddr4_4g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
index c7213abdc72e8387a1c22c6dc882fc76d0a6bb4d..4958df3351a1a1f8f3802460d8e7f0321d2f2917 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
index a7fa910541183ffb7bbb395e0ea13d8f1f779f4f..9ee3836145e3eeae78859b7d60f8325a0d8d0848 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
index c23aafef03b22c62fc2f272aa04920e709d12375..e973cfc298313ed0bb5e3163f94eacd4b9b0a4f0 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_ddr4_4g_2000.qip
+ ip_arria10_e3sge3_ddr4_4g_2000.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
index b9cad2a73e9ac340ab98957b37bc64677c03a90a..f1b453f200164d5d78459ead9a893ce00b1db24e 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
index ced3c0a509e3d6e73ec30a150057b6d9ba8b0ddf..04c2a8b4be31e4d5f5ef249a650466322d8b90f7 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
index 29715012a363b91cc0228f63a2c20e9b82a9fee3..f8c58abd7306b4b20930834c6dd1037463b66c29 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_ddr4_8g_1600.qip
+ ip_arria10_e3sge3_ddr4_8g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
index 3cefb93eccdb88a5e36d64f5ceaf7d8077e94448..ce6a73617cf8953e1e92e06aed99720360d50beb 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
index 80794294d5c0968caa85c768817df202f7d6e8e6..aae9b7d9c164ae06e67a2c7f461da36003ebce98 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
index a433ee55229367e93046d038914594c6e1db47cc..61b0187261993f78a56afb9aa4432fcb871c4724 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_ddr4_8g_2400.qip
+ ip_arria10_e3sge3_ddr4_8g_2400.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
index cfe2a2a2d88c7a058d3596d9b1297941b2b0e8a3..6db25b6412e89ebde6decb09c13f7e14890315b0 100755
--- a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
@@ -38,7 +38,7 @@ Contents:
The IP only needs to be generated with ./generate_ip.sh if it need to be modified, because the ip_arria10_fifo_*.vhd
directly instantiates the altera_mf component.
- The instantiation is copied manually from the generated/ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
+ The instantiation is copied manually from the ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
saved in the <fifo_name>.vhd file. So then the MegaWizard vhd file is overwritten, but that is fine because it is
no longer needed, it could easily be derived from the original in $UNB and it is still as a previous verion in SVN.
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
index 9ba8d5f30fe645c8598c0bc36f533a35e2ea3be6..76d5339e030c9d7eaac1fae1f296573df78a9c62 100755
--- a/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/generate_ip.sh
@@ -33,7 +33,7 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_e3sge3_fifo_*.vhd directly instantiates
# the FIFO altera_mf component.
-# The instantiation is copied manually from the generated/ip_arria10_e3sge3_ram_*/fifo_140/sim/ip_arria10_e3sge3_fifo_*.vhd.
+# The instantiation is copied manually from the ip_arria10_e3sge3_ram_*/fifo_140/sim/ip_arria10_e3sge3_fifo_*.vhd.
# It appears that the altera_mf FIFO component for Arria10 can be synthesized similar as how it worked for Stratix IV,
# it is not necessary to use the generated qip file.
#
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
index c48cca790f2bad26ffc6a28a3aee631c4f4c07e6..dca4f15724202af79962351ed84c4c74b7e698ff 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
vmap ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
index 08a9862f736d5b73b9bcb103c314ec74fdfe3b61..8158007cdb873e2d4e2ab3ce592fe8f529c1cdba 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_asmi_parallel.qip
+ ip_arria10_e3sge3_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
index 995703d1817b63abd3742837ce6a1ea94e6eb555..74015b629d77fa5bb93635d791d424e2c431c3e4 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/flash/remote_update/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_core_151 ./work/
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
index ee60d547c8ee724cfd40c6ff81e45e9c56c31785..d86f360f5343b5477c35ed1eaffd53207cdf13b7 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_remote_update.qip
+ ip_arria10_e3sge3_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
index 26d0ca325d333b3e8c6da2d10ecbba57bcd3cbd1..7e094e9376d12c2d669bd1f866df2cc8e050d012 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
index 70f593d6bb33201bcb9b307b81a2d105c10e861c..3206621e21ad428d93007250e5f8b547abf67029 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_fractional_pll_clk125.qip
+ ip_arria10_e3sge3_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
index 0383174c3bf4520da2b5c97b6293331bd4d214f4..c0daa81c16aead7d28d9c9c4a02a89d671be52e7 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
index f150a9eff002da8700bdfb6d62a68fba50253b49..8d98ad13a49efc499b251b8f19b0f90a616acf2d 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_fractional_pll_clk200.qip
+ ip_arria10_e3sge3_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
index 1809358e9cffbc914b28099a977ad0b8ff8cc4b6..c775402d02b409cbc5f046ee91549577ddf8c52a 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
@@ -37,7 +37,7 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- generated/ip_arria10_mac_10g.qip
+ ip_arria10_mac_10g.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
index 23647961fcd4e08dd731001fddd696fdaaae619a..5567b55fb3ecb22e5b70bf65468cff275cf57dd2 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated/sim"
-set IP_TBDIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_TBDIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
index 9d03c8de482d5b21f5a4fe529f2af1da913b9fd1..1388ee04dd3a148a41a25eb40a1a8bdbcc28a33b 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
[modelsim_project_file]
@@ -19,7 +19,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_mac_10g.qip
+ ip_arria10_e3sge3_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
index e3aa9bf13c5e3f1aa838ea2b857e87bb75ff0e78..9f2c5442d710666ca8ab4049d336979fdafc104c 100644
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/mult_add4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
index c58d590f77b1df91ba2e8a01b9327e92ed940db8..e27cf86d7f2e8c9c5aff9ebccdeb94f396559222 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
index d6999a29ee2f93b40c8121ec6289a4ac187eca66..8e7bc5b458b44fcbf572c6c0fbc7369b885366d6 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_phy_10gbase_r.qip
+ ip_arria10_e3sge3_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
index 7b2e6c3379e357802f2b87a4b41f3d392c612ca6..4d2d833dae507da920d09319c4b44fda9d976d05 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
index 2c483639f50437a0fc82fd8a07b646b503f2dea4..1f8b843ee0e885c212a83cedd2b062461c58a7ef 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_phy_10gbase_r_12.qip
+ ip_arria10_e3sge3_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
index 86a711170a0b1e8e856faf5bbf8a29fd46cc5c67..26ba984cb5036540586ece8045005736f2841a36 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
index 5c2b3e6e59e1cbedc0254dbc5aa9ce8e8f279ece..189f75540261952924676637fab2d899555a4eef 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_phy_10gbase_r_24.qip
+ ip_arria10_e3sge3_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
index 52f79da7b2e4a3e7e193f2e0df8d65589733279c..76743709b4c09aebff7c4cdf62d95de2aa1f831b 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
index 94e1849d1e32b336c35566ddb8f1e585797aa397..16bfd7165f750dcb58664297ccde118874795f76 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_phy_10gbase_r_4.qip
+ ip_arria10_e3sge3_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
index 82b3ff12a72276d40de0fb18f489bcc7380635a5..f80ddb5a8f5ef750d79362407a6fa7c6a1f50805 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
index 4ea8a12229e27255a30f43118748bd6ef32046d5..7c697c657220366c271679dfa03484443286dce6 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_phy_10gbase_r_48.qip
+ ip_arria10_e3sge3_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
index 71564250c52e54e7521a28286110696303257d6a..cdad30ae363b2c7919319f57edf6f9ae3c05282e 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk125/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
index 3e61b19f5b9bc8bd25a4731dd4ad711c011b1571..ed9baef7c276d80213e9ee9f83b734acdc1ef283 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_pll_clk125.qip
+ ip_arria10_e3sge3_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
index 5418dc79a17342a077163765116282c049758566..1e38e5900f4698bdf951883342899bdf381249e4 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk200/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
index 736f98fb0c7765508bb8db5d7ceec21b9fc7cd04..ca6a0c6d8bcaf01250aad3e0b1c575c7a0fb98f6 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_pll_clk200.qip
+ ip_arria10_e3sge3_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
index 07c26baa46c45c60a91f0175a612cd2d96defc68..fed8a5ff9a11c0fb8a76aa9943bfdec3ab112af2 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_clk25/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
index 7ddd6210a78df3cebc1aac249f385c683716fdba..77d805a510d55269397e2a21e0f5fcf7d54b6e2e 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_pll_clk25.qip
+ ip_arria10_e3sge3_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
index 4e80e996457cff9045c39bda82b3289463a7f2b4..10417d22caf3d49fad2250b27a92af6e1c837bd4 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
index 3241762cfd9cb8b7cf86b59add598533721719fe..bb1bcd9a4f1102d16b6c3fd34a8a43f342f89bc7 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_pll_xgmii_mac_clocks.qip
+ ip_arria10_e3sge3_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/README.txt b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
index a9fe41102a7d2cec63b7c2f3846b28447c1b4bc0..24ad4ab94e542bd2d642eaa079f4e18624d8c163 100755
--- a/libraries/technology/ip_arria10_e3sge3/ram/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
@@ -32,7 +32,7 @@ Contents:
if it need to be modified, because the ip_arria10_ram_*.vhd directly instantiates the altera_syncram component.
- The instantiation is copied manually from the generated/ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
+ The instantiation is copied manually from the ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
index a823b95804bc7f9b47109513893b3276cb5f8993..502af4187cd06b7035e21041a9d40238d667c375 100755
--- a/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ram/generate_ip.sh
@@ -33,7 +33,7 @@
#
# The IP only needs to be generated if it need to be modified, because the ip_arria10_e3sge3_ram_*.vhd directly instantiates
# the altera_syncram component.
-# The instantiation is copied manually from the generated/ip_arria10_e3sge3_ram_*/ram_2port_140/sim/ip_arria10_e3sge3_ram_*.vhd.
+# The instantiation is copied manually from the ip_arria10_e3sge3_ram_*/ram_2port_140/sim/ip_arria10_e3sge3_ram_*.vhd.
# It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
# that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
#
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
index 98c7b0550c0e17d34b477f53c20350076c3d3d9a..a0b6fedf0b8630ceba89b4bc37e59767cc0e9ace 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
@@ -99,7 +99,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e3sge3_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e3sge3_ram_cr_cw/ram_2port_140/sim/ip_arria10_e3sge3_ram_cr_cw_ram_2port_140_72tpmcy.vhd
+ -- Copied from ip_arria10_e3sge3_ram_cr_cw/ram_2port_140/sim/ip_arria10_e3sge3_ram_cr_cw_ram_2port_140_72tpmcy.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
index fc9faba96463ef13dea5ad6aab8f2b1924877bf2..e5741a8cbe69610b3d7f40442d70e2fb68e63784 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
@@ -115,7 +115,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e3sge3_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e3sge3_ram_crw_crw/ram_2port_140/sim/ip_arria10_e3sge3_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
+ -- Copied from ip_arria10_e3sge3_ram_crw_crw/ram_2port_140/sim/ip_arria10_e3sge3_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
index 810443100078b000d7b7aa2edd31e22f77da4451..1656f25328b3238286d4d390fb18eb41bbec8fde 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
@@ -95,7 +95,7 @@ ARCHITECTURE SYN OF ip_arria10_e3sge3_ram_crwk_crw IS
BEGIN
- -- Copied from generated/ip_arria10_e3sge3_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e3sge3_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
+ -- Copied from ip_arria10_e3sge3_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e3sge3_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
index 00b622447c73aedf89d070d6493799adc552ee81..033fa02fbfd9e5494f998d26708e00af6a774772 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
@@ -96,7 +96,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e3sge3_ram_r_w : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from generated/ip_arria10_e3sge3_ram_r_w/ram_2port_140/sim/ip_arria10_e3sge3_ram_r_w_ram_2port_140_hukd7xi.vhd
+ -- Copied from ip_arria10_e3sge3_ram_r_w/ram_2port_140/sim/ip_arria10_e3sge3_ram_r_w_ram_2port_140_hukd7xi.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_aclr_b => "NONE",
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
index f863a700748005ed3d0c6bd1b2e35a50c6218ea6..350a3674c84ac54768168ceb712b6ff2a8ddb292 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/temp_sense/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
index 04b2dc9836efa1f208d5371f9043ec2c30fb5b72..8f96a5f7bb69eea60f9d3a9f6ded0dede3641550 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
@@ -15,7 +15,7 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_e3sge3_temp_sense.qip
+quartus_qip_files = ip_arria10_e3sge3_temp_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
index 806454fac629ddce0a6a6e5ab1b83c5da33668f1..e16ab1bb84c6316da9dfc49018ba573bc2b95a77 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
index d1284863953e02f1f65270d4ffed68df0dd23635..afd34643a6205c784885b1f99810fa3d2ae787ed 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_pll_10g.qip
+ ip_arria10_e3sge3_transceiver_pll_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
index fd40ff872189f846f752dff7c7ea0bad54f3e731..824d03bc0cb687920db589d5f8ea78d4f8560d98 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
index df77648d5bb6d8132dee32ad2a312c87414fdb6f..f6fbacfad75630fa73b904381d4b085fed7f106e 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_reset_controller_1.qip
+ ip_arria10_e3sge3_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
index dda89b41c6ab60ab2827dbe0662ecd4b728c5840..b674c73aa85fa7158f0b197728d48ec5b4e03671 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
index 1174e7891aeed310bbf978f057b4c252d5ef2e2f..a0f8d7cfba9c5fe142cfc0b4feb676dae5a5ca14 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_reset_controller_12.qip
+ ip_arria10_e3sge3_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
index 54f87c5f3fb95085a3c3793fa26e38645984998f..d9cbccb13916af9d956f2cfd4599dffd5adb1e36 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
index 5568315590566a9718b13f2afa17e1618d654c95..a1b6720a8007e8c8a9ac5be26ee23faafcdf33bd 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_reset_controller_24.qip
+ ip_arria10_e3sge3_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
index 8ad00f7882a4a925f24b4e62e67af3df85f5f6a7..f2d0fa88e704a22ac8413b19035bcbfa706dfabd 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
index e5bb6bb856506f7660514dd1be97c0f3eca88902..79a61988aa6ba09e885b18851cf9c110f50ea3f7 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_reset_controller_4.qip
+ ip_arria10_e3sge3_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
index e77af624de326e6b61ee397fdc319ae99028ca15..84ad7eb84803cc22e84de6f2107d5db4a3761297 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
index 9185b8febc88ed705f7a89b14ab060f0aae69d0f..fddd592bd0bd0443933331ebe8b8a628abeeb125 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_transceiver_reset_controller_48.qip
+ ip_arria10_e3sge3_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
index 38368d2110f7a50c08bf0838fc9f9342b8632d91..216ad6395efaab77b402e3772713ca874f202a96 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
index a2022287b220b345ba688fd62324feb3aa31c829..9745670627b54edab6625fe19f05163fbd0e885b 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_tse_sgmii_gx.qip
+ ip_arria10_e3sge3_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
index 41c63a1ae3f64dc03c936f740bba7141d8697c11..add9457301889430396ec523be3c6a3948e1ff19 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
index 5665f5db4c74986adf0c56baf99b9339eb683702..1f2692dc301256fb90cdc53bab628aa3944f33ed 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_arria10_e3sge3_tse_sgmii_lvds.qip
+ ip_arria10_e3sge3_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
index 8b61b7eb886a3180747c704703db4924ce24cbba..090df9c5c970cda1729a1d4f14a1ad3d2b96691d 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/voltage_sense/generated/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
index 63946dd01ba8563fc43797c620922c0abe33699d..77801114c9b0760f52b341b03fcebe2ed4d91545 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
[quartus_project_file]
-quartus_qip_files = generated/ip_arria10_e3sge3_voltage_sense.qip
+quartus_qip_files = ip_arria10_e3sge3_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
index 2690e54a37ceb50230ab713b05004c8517bf0b64..59ee3539ca85a400014442074aca2f02d6ba97e3 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
@@ -23,7 +23,8 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
# Get the memory model fro the uphy_4g_* from the ip_stratixiv_ddr3_uphy_4g_800_master example design
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
+#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_example_design
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
index ab5bd65220f15f21adbe98861bc7bfa9c9fc47a4..0cba85661da782f1018dac1256b37ce01128a5e7 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
index c14c1911ff87e21ff31dac52f3cd28f6e0351b9f..c62e33e6542d97c0afd5710ed102b21c46b996fb 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
index 31f0359c75c3ec00538cfc8352f3cfd3f6ec236a..56142bcee051639f84ee9d08c8ce694570dcbb04 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
index 1ad73c93b568eac6e25f860eca978619c0ed895b..0130afea23dfba3cd3857bdb6b6ce45204bc2f89 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
index 7e5924ab3850a3721a4c8b5da9a548486d456007..aae001963a1666ede237e7d4a4f3879f8747cab9 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
index 0d39d81f1fea4fdf7b275f493514a74b2354f48f..adec7b0329c573111c3f04d2598b44c6ded23d79 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ ip_stratixiv_ddr3_uphy_4g_800_master.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
index 3cd4b206184270dfce95c54502b9766978f40d38..100507af6ac9d66860d3515cce14de9b0d6d6018 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
index 6a6e8602957e96fb85f3b0f7cdcc3493b4bdda1e..96244d1526a14cce781676867953c8e7a7a4b5e3 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
index 46a856b9a0d6eac4c536d4e611c77062cbaab7f0..8391e40fd9e4df2ec9f076a6f635ac7b4476d8f4 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ ip_stratixiv_ddr3_uphy_4g_800_slave.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
index 1d878a2a3c4154e12c4a98d5aa6a54887e084f95..84678948ceb14c7d67f200944ea17387669da202 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
index e0786cddebaef392d34fd6518e393c89acd548ba..6a06571581b76225f3950e55aad925a7bb8b8a8c 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
index c28bd93dd1b24022b08a27be593fb4c7e957d83d..e59e8b5ca01e5156790364cc7011cda38e5a909c 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
index 962b26b7f9befa28591fcbfe5f315a9541d066d9..ca5ef73e8666aba7af7ecc6b4bb7a8088ae62929 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
index 00f508ab3377462b115449814a18ad6bcab197c1..755278c8493e3aee82e075c5c9c660581ef38ef7 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
index 6f9285a23446bddeaef69b9d2bec8094a5976024..806cd417be752174015339438584299d42cf0af1 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.qip
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
index 33c1e12bf70ebeff95cdf9ea1d1b4816a377789c..8133ccc7f4a321a55c1e08d79c23843be17a72b9 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
@@ -24,7 +24,7 @@
# file msim_setup.tcl.
# tr_xaui is the first module I did this for.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_mac_10g_sim"
#vlib ./work/ ;# Assume library work already exists
#vmap work ./work/
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho
index a5b8a809ae4aafe1d9b9d1f1719a45e5bf373e71..a839c012dc1863d5528a7148ee9dd1581dc10ac3 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0001.vho
@@ -212,7 +212,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout : STD_LOGIC;
@@ -222,7 +222,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout : STD_LOGIC;
@@ -393,7 +393,7 @@
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_390q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_389q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_388q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
- altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_386q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_385q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_3_421q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout;
@@ -404,7 +404,7 @@
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_380q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_379q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_378q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
- altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_376q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_375q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_4_420q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout;
@@ -542,7 +542,7 @@
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_34_321q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_35_320q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_36_319q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
- altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_318q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_37_318q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_38_317q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_39_316q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_3_352q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_214m_dataout;
@@ -553,7 +553,7 @@
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_311q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_310q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_309q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
- altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_308q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_308q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_307q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_306q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_351q <= wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_213m_dataout;
@@ -605,7 +605,7 @@
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout <= in_data(50) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_374q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout <= in_data(49) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_375q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout <= in_data(48) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_376q;
- wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(47) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(47) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_377q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout <= in_data(46) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_378q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout <= in_data(45) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_379q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout <= in_data(44) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_380q;
@@ -615,7 +615,7 @@
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout <= in_data(40) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_40_384q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout <= in_data(39) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_39_385q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout <= in_data(38) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_38_386q;
- wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(37) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q;
+ wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(37) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_37_387q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout <= in_data(36) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_36_388q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout <= in_data(35) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_35_389q;
wire_altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout <= in_data(34) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0001_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_34_390q;
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho
index 73d05546f12ebaf394cb6f78f4c1f4711c80f8b8..0126c6d7e7aea4d6ecc09a9274d440834360a085 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0002.vho
@@ -58,7 +58,7 @@
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q : STD_LOGIC := '0';
- SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_170q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q : STD_LOGIC := '0';
@@ -69,7 +69,7 @@
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q : STD_LOGIC := '0';
- SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_180q : STD_LOGIC := '0';
+ SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_3_198q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_4_197q : STD_LOGIC := '0';
SIGNAL altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_5_196q : STD_LOGIC := '0';
@@ -225,7 +225,7 @@
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q <= '0';
- altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_170q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q <= '0';
@@ -236,7 +236,7 @@
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q <= '0';
- altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_180q <= '0';
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_3_198q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_4_197q <= '0';
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_5_196q <= '0';
@@ -260,7 +260,7 @@
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_86m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_104m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_85m_dataout;
- altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_170q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_83m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_82m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_81m_dataout;
@@ -271,7 +271,7 @@
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_76m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_103m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_75m_dataout;
- altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_180q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout;
+ altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_3_198q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_102m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_4_197q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_101m_dataout;
altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_5_196q <= wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_100m_dataout;
@@ -363,7 +363,7 @@
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_103m_dataout <= in_data(2) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_2_199q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_104m_dataout <= in_data(1) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_1_200q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_105m_dataout <= in_data(0) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_0_208q;
- wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout <= in_data(31) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_180q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_74m_dataout <= in_data(31) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_31_170q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_75m_dataout <= in_data(30) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_30_171q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_76m_dataout <= in_data(29) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_29_172q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_77m_dataout <= in_data(28) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_28_173q;
@@ -373,7 +373,7 @@
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_81m_dataout <= in_data(24) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_24_177q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_82m_dataout <= in_data(23) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_23_178q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_83m_dataout <= in_data(22) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_22_179q;
- wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout <= in_data(21) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_180q;
+ wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_84m_dataout <= in_data(21) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_21_170q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_85m_dataout <= in_data(20) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_20_181q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_86m_dataout <= in_data(19) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_19_182q;
wire_altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_87m_dataout <= in_data(18) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0002_altera_avalon_sc_fifo_tx_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_mem_1_18_183q;
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho
index d84d0eb4fc6b11950d6a0c9068c6bbb07771bac4..d630f56f5c44b516138e3764f4d826470640d062 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0003.vho
@@ -285,7 +285,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout : STD_LOGIC;
@@ -295,7 +295,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout : STD_LOGIC;
@@ -885,7 +885,7 @@
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_327q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_326q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_325q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
- altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_324q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_324q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_323q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_322q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_4_367q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_223m_dataout;
@@ -896,7 +896,7 @@
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_317q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_316q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_315q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
- altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_314q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_314q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_313q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_312q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_5_366q <= wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_222m_dataout;
@@ -933,7 +933,7 @@
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout <= in_data(60) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_60_528q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout <= in_data(59) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_529q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout <= in_data(58) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_530q;
- wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(57) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_531q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(57) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_531q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout <= in_data(56) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_532q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout <= in_data(55) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_533q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout <= in_data(54) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_534q;
@@ -943,7 +943,7 @@
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout <= in_data(50) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_50_538q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout <= in_data(49) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_539q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout <= in_data(48) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_540q;
- wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(47) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_541q;
+ wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(47) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_541q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout <= in_data(46) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_542q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout <= in_data(45) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_543q;
wire_altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout <= in_data(44) WHEN wire_nlO_w75w(0) = '1' ELSE altera_avalon_sc_fifo_0003_altera_avalon_sc_fifo_tx_eth_statistics_collector_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_544q;
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho
index 5f8525fbeb76000920f87844d1bb9217ce1f599c..324d483ebc18a11bdf4f5b0149ee9c08d7d6d874 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_avalon_sc_fifo/altera_avalon_sc_fifo_0004.vho
@@ -212,7 +212,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout : STD_LOGIC;
@@ -222,7 +222,7 @@
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout : STD_LOGIC;
- SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout : STD_LOGIC;
SIGNAL wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout : STD_LOGIC;
@@ -415,7 +415,7 @@
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_399q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_398q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_397q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
- altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_395q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_394q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_393q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout;
@@ -426,7 +426,7 @@
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_389q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_388q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_387q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
- altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_385q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_384q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_383q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout;
@@ -570,7 +570,7 @@
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_43_327q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_44_326q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_45_325q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout;
- altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_324q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_46_324q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_47_323q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_48_322q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_49_321q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout;
@@ -581,7 +581,7 @@
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_53_317q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_54_316q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_55_315q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout;
- altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_314q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout;
+ altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_56_314q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_57_313q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_58_312q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout;
altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_0_59_311q <= wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout;
@@ -620,7 +620,7 @@
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_167m_dataout <= in_data(59) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_59_383q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_168m_dataout <= in_data(58) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_58_384q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_169m_dataout <= in_data(57) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_57_385q;
- wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(56) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(56) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_56_386q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_171m_dataout <= in_data(55) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_55_387q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_172m_dataout <= in_data(54) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_54_388q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_173m_dataout <= in_data(53) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_53_389q;
@@ -630,7 +630,7 @@
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_177m_dataout <= in_data(49) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_49_393q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_178m_dataout <= in_data(48) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_48_394q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_179m_dataout <= in_data(47) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_47_395q;
- wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_180m_dataout <= in_data(46) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q;
+ wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_170m_dataout <= in_data(46) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_46_396q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_181m_dataout <= in_data(45) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_45_397q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_182m_dataout <= in_data(44) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_44_398q;
wire_altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_183m_dataout <= in_data(43) WHEN wire_nl_w1w(0) = '1' ELSE altera_avalon_sc_fifo_0004_altera_avalon_sc_fifo_tx_eth_pad_inserter_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_mem_1_43_399q;
diff --git a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho
index 91c65f7c5c3d80984b5f45333e77392639281389..feb85ddf87375305a0d83505810ec1d00c39b23a 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho
+++ b/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/altera_merlin_master_translator/altera_merlin_master_translator_0001.vho
@@ -60,7 +60,7 @@
SIGNAL wire_nO_w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout : STD_LOGIC;
SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_177m_dataout : STD_LOGIC;
- SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_180m_dataout : STD_LOGIC;
+ SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_170m_dataout : STD_LOGIC;
SIGNAL wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_181m_dataout : STD_LOGIC;
SIGNAL wire_w_lg_reset258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_uav_readdatavalid257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -93,8 +93,8 @@
wire_nO_w51w(0) <= NOT altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q;
wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout <= wire_w_lg_uav_readdatavalid257w(0) WHEN av_read = '1' ELSE uav_waitrequest;
wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_177m_dataout <= altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q AND NOT((uav_readdatavalid AND altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q));
- wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_180m_dataout <= (wire_w_lg_uav_waitrequest255w(0) AND av_read) AND wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout;
- wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_181m_dataout <= wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_177m_dataout WHEN altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q = '1' ELSE wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_180m_dataout;
+ wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_170m_dataout <= (wire_w_lg_uav_waitrequest255w(0) AND av_read) AND wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_av_waitrequest_183m_dataout;
+ wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_181m_dataout <= wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_177m_dataout WHEN altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_186q = '1' ELSE wire_altera_merlin_master_translator_0001_altera_merlin_master_translator_merlin_master_translator_read_accepted_170m_dataout;
END RTL; --altera_merlin_master_translator_0001
--synopsys translate_on
diff --git a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
index da20f4a1a876d4bc4163a9785ed2536445834e46..47e15241a44bca39c627542497dae602dfb123dc 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
@@ -25,7 +25,7 @@ quartus_vhdl_files =
quartus_sdc_files =
quartus_qip_files =
- generated/ip_stratixiv_mac_10g.qip
+ ip_stratixiv_mac_10g.qip
[generate_ip_libs]
qmegawiz_ip_files =
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
index ed22b0d05263f7d885dbbfca94f1c97c5935f6bb..3318814203f8331a9e088a57d8fec68ae9cc9284 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
@@ -27,7 +27,7 @@
# correct compile order).
# EK: The model files in phy_xaui_0_sim/ are suitable for all hard xaui IP variants.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_0_sim"
#vlib ./work/ ;# EK: Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
index 7eae3900cf0b6ecfebcb69f1b03f06c2c34d892c..7e223040ac5a77da850fcf76c456371f295e9dbd 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
@@ -27,7 +27,7 @@
# correct compile order). Bonus of this is also that there will be no errors
# when making all_mod without having run the XAUI megawizard first.
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_soft_sim"
#vlib ./work/ ;# EK: Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
index 8f8916bf66ba204b654a727c13413980d0ac0b62..ac4ee7014d1b5e7aa4680c1b529972eed67c1f09 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
@@ -33,7 +33,7 @@ quartus_vhdl_files =
quartus_sdc_files =
quartus_qip_files =
- generated/ip_stratixiv_phy_xaui_0.qip
+ ip_stratixiv_phy_xaui_0.qip
ip_stratixiv_phy_xaui_soft.qip
[generate_ip_libs]
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index 157235e48c95a9d9f3ca3f66aad5605dfaf2c733..c73c25d07ace159e1cdc134df74059710a78010e 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -8,7 +8,7 @@ hdl_lib_disclose_library_clause_names =
ip_stratixiv_mac_10g ip_stratixiv_mac_10g_lib
ip_arria10_mac_10g ip_arria10_mac_10g_alt_em10g32_150
ip_arria10_e3sge3_mac_10g ip_arria10_e3sge3_mac_10g_alt_em10g32_151
- ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g_alt_em10g32_180
+ ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g_alt_em10g32_170
synth_files =
tech_mac_10g_component_pkg.vhd
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
index 2acea7c3c25f19121043b8f93f1cab9106542cb6..c41aa2774891bb77962b62ea95583f0aadd33648 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
@@ -21,7 +21,7 @@
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_180;
+LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_170;
LIBRARY IEEE, technology_lib, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index 4f9aec44175fc9ad7bda11978a1b714ae20501d3..fccd070a5056e9397d604d567d9f6ccb20e1d5a3 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -52,7 +52,7 @@ PACKAGE tech_mac_10g_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Copied from entity $RADIOHDL_WORK/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
+ -- Copied from entity $HDL_BUILD_DIR/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
COMPONENT ip_stratixiv_mac_10g IS
PORT (
csr_clk_clk : in std_logic := '0'; -- csr_clk.clk
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 2b3f3f655d112e0fb00346756e14661765c577b1..f9ac504fb4a63e767881edd359dfd70c84209de7 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -17,7 +17,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_mult ip_arria10_mult_lib
ip_arria10_complex_mult ip_arria10_complex_mult_altmult_complex_150
ip_arria10_complex_mult_rtl ip_arria10_complex_mult_rtl_lib
- ip_arria10_e1sg_complex_mult ip_arria10_e1sg_complex_mult_altmult_complex_180
+ ip_arria10_e1sg_complex_mult ip_arria10_e1sg_complex_mult_altmult_complex_170
ip_arria10_e3sge3_mult_add4 ip_arria10_e3sge3_mult_add4_lib
ip_arria10_e1sg_mult_add4 ip_arria10_e1sg_mult_add4_lib
ip_arria10_e1sg_mult_add2 ip_arria10_e1sg_mult_add2_lib
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index 6432cf385e36cf90f7a7ee7e4911b6f6d039261f..82975e83418293f02b81b5045c8d1ccaa57fbe09 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -31,7 +31,7 @@ LIBRARY ip_stratixiv_mult_lib;
--LIBRARY ip_arria10_mult_lib;
--LIBRARY ip_arria10_mult_rtl_lib;
LIBRARY ip_arria10_complex_mult_altmult_complex_150;
-LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_180;
+LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_170;
LIBRARY ip_arria10_complex_mult_rtl_lib;
LIBRARY ip_arria10_complex_mult_rtl_canonical_lib;
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index c7b3d55035279053a4c7be362f7ce4798e9d66c2..4b047fa7c0eb0237004172d7426940ffe6f5ba8d 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -18,10 +18,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_pll_clk25 ip_arria10_e3sge3_pll_clk25_altera_iopll_151
ip_arria10_e3sge3_pll_clk125 ip_arria10_e3sge3_pll_clk125_altera_iopll_151
ip_arria10_e3sge3_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
- ip_arria10_e1sg_pll_clk200 ip_arria10_e1sg_pll_clk200_altera_iopll_180
- ip_arria10_e1sg_pll_clk25 ip_arria10_e1sg_pll_clk25_altera_iopll_180
- ip_arria10_e1sg_pll_clk125 ip_arria10_e1sg_pll_clk125_altera_iopll_180
- ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180
+ ip_arria10_e1sg_pll_clk200 ip_arria10_e1sg_pll_clk200_altera_iopll_170
+ ip_arria10_e1sg_pll_clk25 ip_arria10_e1sg_pll_clk25_altera_iopll_170
+ ip_arria10_e1sg_pll_clk125 ip_arria10_e1sg_pll_clk125_altera_iopll_170
+ ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170
synth_files =
tech_pll_component_pkg.vhd
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index df94261a8337360e01c8283d7079d38e92ef7c3d..5cdbbb6be1a4d276d0f2d45e3f701d4ca56c5bb4 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_clk125_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk125_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_180;
+LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_170;
ENTITY tech_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index adf88609a918af520b4d93bea13a62c40d831313..4eefc35b6de5375616b1f9bc585a4cc750ba1771 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_pll_lib;
LIBRARY ip_arria10_pll_clk200_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk200_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_180;
+LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_170;
ENTITY tech_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index bfb242b469fe81c81b35920dc91ad24acb4aab02..2521432735ce688387a6fa211a847973d1ef7845 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
LIBRARY ip_stratixiv_pll_clk25_lib;
LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_180;
+LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_170;
ENTITY tech_pll_clk25 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index ca3990942354cdc18be4a0cd19a240d9ea4239e8..28f1fa3a1ed8ac9a886605359bd397afc11640ca 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -43,7 +43,7 @@ USE common_lib.common_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180;
+LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170;
ENTITY tech_pll_xgmii_mac_clocks IS
GENERIC (
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index 56d098e9b3533ac82bf3ca1f5a8e95647d16d07a..0a5b17d1d19b99f85c4b0eaf890090056363083c 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -14,8 +14,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_tse_sgmii_gx ip_arria10_tse_sgmii_gx_altera_eth_tse_150
ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
ip_arria10_e3sge3_tse_sgmii_gx ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
- ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180
- ip_arria10_e1sg_tse_sgmii_gx ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180
+ ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170
+ ip_arria10_e1sg_tse_sgmii_gx ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170
synth_files =
tech_tse_component_pkg.vhd
diff --git a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
index 664f3f85ecbc4e6a2d853b9a02bfb9ae635dfc07..4512fe7d9e9a08487caa41b6376ce774ee07ef82 100644
--- a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
@@ -28,8 +28,8 @@ USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180;
-LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180;
+LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170;
+LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170;
ENTITY tech_tse_arria10_e1sg IS
GENERIC (
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index 6671ba6f7ee79bd419eb6221408a84224df5fe18..456d59f72b2b42d0e402caedd7bb3a4fc091f0fe 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -147,7 +147,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim/ip_arria10_tse_sgmii_lvds.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_tse_sgmii_lvds IS
PORT (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
@@ -198,7 +198,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim/ip_arria10_tse_sgmii_gx.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_gx.vhd
COMPONENT ip_arria10_tse_sgmii_gx IS
PORT (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
@@ -265,7 +265,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_e3sge3_tse_sgmii_lvds IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -316,7 +316,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
COMPONENT ip_arria10_e3sge3_tse_sgmii_gx IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -383,7 +383,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_e1sg_tse_sgmii_lvds IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -434,7 +434,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
COMPONENT ip_arria10_e1sg_tse_sgmii_gx IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata