From 80ba2261a31267cfb82ab90086c44e6bab62f792 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 25 Mar 2015 15:31:32 +0000
Subject: [PATCH] Renamed g_sim into g_use_ddr_memory_model.
---
libraries/technology/ddr/tech_ddr.vhd | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/libraries/technology/ddr/tech_ddr.vhd b/libraries/technology/ddr/tech_ddr.vhd
index 578924ddf5..3c2b611720 100644
--- a/libraries/technology/ddr/tech_ddr.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -24,9 +24,11 @@
-- Description:
-- The component also supports different types of DDR, so DDR3 and DDR4.
-- Remark:
--- In simulation use g_sim=TRUE to also include the DDR memory model that is
--- internally available within tech_ddr. This avoids having to connect a DDR
--- memory model at top level in the test bench.
+-- In simulation use g_use_ddr_memory_model=TRUE to also include the DDR
+-- memory model that is internally available within tech_ddr. This avoids
+-- having to connect a DDR memory model at top level in the test bench.
+-- Default g_use_ddr_memory_model must be FALSE to avoid further analysis
+-- of the DDR memory model component by synthesis.
LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -37,9 +39,9 @@ USE work.tech_ddr_pkg.ALL;
ENTITY tech_ddr IS
GENERIC (
- g_technology : NATURAL := c_tech_select_default;
- g_tech_ddr : t_c_tech_ddr;
- g_sim : BOOLEAN := FALSE
+ g_technology : NATURAL := c_tech_select_default;
+ g_tech_ddr : t_c_tech_ddr;
+ g_use_ddr_memory_model : BOOLEAN := FALSE
);
PORT (
-- PLL reference clock
@@ -90,15 +92,15 @@ BEGIN
phy_in, phy_io, i_phy_ou);
END GENERATE;
- -- Include DDR memory model for simulation
- no_sim : IF g_sim=FALSE GENERATE
+ -- Include DDR memory model only for simulation
+ no_ddr_memory_model : IF g_use_ddr_memory_model=FALSE GENERATE
phy_ou <= i_phy_ou;
END GENERATE;
- gen_sim: IF g_sim=TRUE GENERATE
+ gen_ddr_memory_model: IF g_use_ddr_memory_model=TRUE GENERATE
u_tech_ddr_memory_model : ENTITY work.tech_ddr_memory_model
GENERIC MAP (
- g_sim => g_sim,
+ g_sim => g_use_ddr_memory_model,
g_tech_ddr => g_tech_ddr
)
PORT MAP (
--
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