diff --git a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
index 47e66fdee3b9e906ab4377e4fb2ac37079bfec40..57aa161139d32e5619e833888315d1bdc2120951 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
@@ -121,52 +121,52 @@ BEGIN
     miso_arr => ram_bg_data_miso_arr
   );
   
-  gen_wg_streams : FOR I IN 0 TO g_nof_output_streams-1 GENERATE
+  gen_bg_streams : FOR I IN 0 TO g_nof_output_streams-1 GENERATE
     u_buffer_ram : ENTITY common_lib.common_ram_crw_crw
-      GENERIC MAP (
-        g_ram        => c_buf,
-        -- Sequence number and ".hex" extensie are added to the relative path in case a ram file is provided. 
-        g_init_file  => sel_a_b(g_file_name_prefix = "UNUSED", g_file_name_prefix, g_file_name_prefix & "_" & NATURAL'IMAGE(g_file_index_arr(I)) & c_post_buf_file)    
-      )
-      PORT MAP (
-        -- MM side
-        rst_a     => mm_rst,
-        clk_a     => mm_clk,
-        wr_en_a   => ram_bg_data_mosi_arr(I).wr,
-        wr_dat_a  => ram_bg_data_mosi_arr(I).wrdata(c_buf.dat_w -1 DOWNTO 0),
-        adr_a     => ram_bg_data_mosi_arr(I).address(c_buf.adr_w-1 DOWNTO 0),
-        rd_en_a   => ram_bg_data_mosi_arr(I).rd,
-        rd_dat_a  => ram_bg_data_miso_arr(I).rddata(c_buf.dat_w -1 DOWNTO 0),
-        rd_val_a  => ram_bg_data_miso_arr(I).rdval,
-        -- Waveform side
-        rst_b     => dp_rst,
-        clk_b     => dp_clk,
-        wr_en_b   => '0',
-        wr_dat_b  => (OTHERS =>'0'),
-        adr_b     => st_addr_arr(I), 
-        rd_en_b   => st_rd(I),
-        rd_dat_b  => st_rddata_arr(I),
-        rd_val_b  => st_rdval(I) 
-      );   
+    GENERIC MAP (
+      g_ram        => c_buf,
+      -- Sequence number and ".hex" extensie are added to the relative path in case a ram file is provided. 
+      g_init_file  => sel_a_b(g_file_name_prefix = "UNUSED", g_file_name_prefix, g_file_name_prefix & "_" & NATURAL'IMAGE(g_file_index_arr(I)) & c_post_buf_file)    
+    )
+    PORT MAP (
+      -- MM side
+      rst_a     => mm_rst,
+      clk_a     => mm_clk,
+      wr_en_a   => ram_bg_data_mosi_arr(I).wr,
+      wr_dat_a  => ram_bg_data_mosi_arr(I).wrdata(c_buf.dat_w -1 DOWNTO 0),
+      adr_a     => ram_bg_data_mosi_arr(I).address(c_buf.adr_w-1 DOWNTO 0),
+      rd_en_a   => ram_bg_data_mosi_arr(I).rd,
+      rd_dat_a  => ram_bg_data_miso_arr(I).rddata(c_buf.dat_w -1 DOWNTO 0),
+      rd_val_a  => ram_bg_data_miso_arr(I).rdval,
+      -- Waveform side
+      rst_b     => dp_rst,
+      clk_b     => dp_clk,
+      wr_en_b   => '0',
+      wr_dat_b  => (OTHERS =>'0'),
+      adr_b     => st_addr_arr(I), 
+      rd_en_b   => st_rd(I),
+      rd_dat_b  => st_rddata_arr(I),
+      rd_val_b  => st_rdval(I) 
+    );   
     
-    u_waveform_generator : ENTITY work.diag_block_gen
-      GENERIC MAP (
-        g_blk_sync   => g_blk_sync,
-        g_buf_dat_w  => g_buf_dat_w, 
-        g_buf_addr_w => g_buf_addr_w
-      )
-      PORT MAP (
-        rst        => dp_rst, 
-        clk        => dp_clk, 
-        buf_addr   => st_addr_arr(I),       
-        buf_rden   => st_rd(I),          
-        buf_rddat  => st_rddata_arr(I),       
-        buf_rdval  => st_rdval(I),          
-        ctrl       => bg_ctrl,
-        en_sync    => en_sync,
-        out_siso   => out_siso_arr(I),
-        out_sosi   => out_sosi_arr(I)
-      ); 
+    u_diag_block_gen : ENTITY work.diag_block_gen
+    GENERIC MAP (
+      g_blk_sync   => g_blk_sync,
+      g_buf_dat_w  => g_buf_dat_w, 
+      g_buf_addr_w => g_buf_addr_w
+    )
+    PORT MAP (
+      rst        => dp_rst, 
+      clk        => dp_clk, 
+      buf_addr   => st_addr_arr(I),       
+      buf_rden   => st_rd(I),          
+      buf_rddat  => st_rddata_arr(I),       
+      buf_rdval  => st_rdval(I),          
+      ctrl       => bg_ctrl,
+      en_sync    => en_sync,
+      out_siso   => out_siso_arr(I),
+      out_sosi   => out_sosi_arr(I)
+    );
   END GENERATE;
   
 END rtl;