From 7fb08f74b42fc6067c6eecd08aa428f8524ae417 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Mon, 31 Oct 2016 13:19:42 +0000
Subject: [PATCH] Added extra register for rd_fifo_full bit and wr_fifo_full
bit.
---
libraries/io/ddr/src/vhdl/io_ddr.vhd | 41 ++++++++++++++++++++++++----
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 38dbd9ac2d..7de57238ca 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -243,7 +243,7 @@ ARCHITECTURE str OF io_ddr IS
CONSTANT c_mem_reg_adr_w : NATURAL := 2;
CONSTANT c_mem_reg_dat_w : NATURAL := 32;
- CONSTANT c_mem_reg_nof_data : NATURAL := 3;
+ CONSTANT c_mem_reg_nof_data : NATURAL := 4;
CONSTANT c_mem_reg_io_ddr : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_adr_w , c_mem_reg_dat_w , c_mem_reg_nof_data, 'X');
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
@@ -270,6 +270,11 @@ ARCHITECTURE str OF io_ddr IS
-- Monitor only
SIGNAL ctlr_wr_fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(g_wr_fifo_depth)-1 DOWNTO 0); -- read side depth of the write FIFO
SIGNAL ctlr_rd_fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth)-1 DOWNTO 0); -- write side depth of the read FIFO
+ SIGNAL reg_rd_arr : STD_LOGIC_VECTOR(c_mem_reg_io_ddr.nof_dat-1 DOWNTO 0);
+ SIGNAL wr_fifo_full : STD_LOGIC;
+ SIGNAL wr_fifo_full_reg : STD_LOGIC;
+ SIGNAL rd_fifo_full : STD_LOGIC;
+ SIGNAL rd_fifo_full_reg : STD_LOGIC;
SIGNAL dp_flush_snk_in : t_dp_sosi := c_dp_sosi_rst;
@@ -336,6 +341,7 @@ BEGIN
snk_out => wr_siso,
snk_in => wr_fifo_snk_in,
+ wr_ful => wr_fifo_full,
wr_usedw => wr_fifo_usedw,
rd_usedw => ctlr_wr_fifo_usedw,
rd_emp => OPEN,
@@ -415,7 +421,8 @@ BEGIN
snk_out => ctlr_rd_src_in,
snk_in => ctlr_rd_src_out,
-
+
+ wr_ful => rd_fifo_full,
wr_usedw => ctlr_rd_fifo_usedw,
rd_usedw => rd_fifo_usedw,
rd_emp => OPEN,
@@ -480,9 +487,33 @@ BEGIN
);
ctlr_rst_out <= ctlr_rst_out_i;
+
+ u_wr_fifo_full : ENTITY common_lib.common_switch
+ GENERIC MAP(
+ g_priority_lo => TRUE
+ )
+ PORT MAP(
+ rst => ctlr_rst_in,
+ clk => ctlr_clk_in,
+ switch_high => wr_fifo_full,
+ switch_low => reg_rd_arr(3),
+ out_level => wr_fifo_full_reg
+ );
+
+ u_rd_fifo_full : ENTITY common_lib.common_switch
+ GENERIC MAP(
+ g_priority_lo => TRUE
+ )
+ PORT MAP(
+ rst => ctlr_rst_in,
+ clk => ctlr_clk_in,
+ switch_high => rd_fifo_full,
+ switch_low => reg_rd_arr(3),
+ out_level => rd_fifo_full_reg
+ );
-
- mm_reg_io_ddr <= RESIZE_UVEC(ctlr_wr_fifo_usedw, c_mem_reg_dat_w) &
+ mm_reg_io_ddr <= RESIZE_UVEC(rd_fifo_full_reg & wr_fifo_full_reg, c_mem_reg_dat_w) &
+ RESIZE_UVEC(ctlr_wr_fifo_usedw, c_mem_reg_dat_w) &
RESIZE_UVEC(ctlr_rd_fifo_usedw, c_mem_reg_dat_w) &
RESIZE_UVEC(ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail & ctlr_tech_miso.cal_ok &
ctlr_rst_out_i & ctlr_wr_flush_en & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done, c_mem_reg_dat_w);
@@ -508,7 +539,7 @@ BEGIN
-- MM registers in st_clk domain
reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
+ reg_rd_arr => reg_rd_arr,
in_new => '1',
in_reg => mm_reg_io_ddr,
out_reg => OPEN
--
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