diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
index 14218e8d3d3e96e1716b2418c849465390c4b3ff..3c6ba74af6f99fb0380ed4b2f20af2faf5a6c63e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
@@ -84,6 +84,14 @@ peripherals:
mm_port_names:
- REG_REMU
+ #############################################################################
+ # SDP Info
+ #############################################################################
+
+ - peripheral_name: sdp/sdp_info
+ mm_port_names:
+ - REG_SDP_INFO
+
#############################################################################
# AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
#############################################################################
@@ -207,10 +215,6 @@ peripherals:
# BF = Beamformer (from node_sdp_beamformer.vhd)
#############################################################################
- - peripheral_name: sdp/sdp_info
- mm_port_names:
- - REG_SDP_INFO
-
- peripheral_name: reorder/reorder_col_wide
number_of_peripherals: c_N_beamsets # lofar2_unb2b_beamformer.vhd
parameter_overrides:
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
index 34304c094d92a153e323ae637317ddb8878a237d..80806efb43bcce15c07ffad7edb9687ba4f0cc64 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
@@ -15,8 +15,8 @@ number_of_columns = 13
# col 9: field radix, if - then it is part of previous field_name.
# col 10: field mm_mask
# col 11: field user_mask, if - then it is same as mm_mask
-# col 12: number of peripherals span, if - then not used
-# col 13: number of mm_ports span, if - then not used
+# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
+# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
#
# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
@@ -67,60 +67,73 @@ number_of_columns = 13
- - - - data_out 0x0001a004 1 RO uint32 b[23:0] - - -
- - - - data_in 0x0001a005 1 WO uint32 b[23:0] - - -
- - - - busy 0x0001a006 1 RO uint32 b[0:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x0001c000 1 RW uint32 b[30:0] - - -
- - - - - reset 0x0001c000 1 RW uint32 b[31:31] - - -
- JESD204B 1 1 REG rx_dll_ctrl 0x0001e014 1 RW uint32 b[16:0] - - -
- - - - - rx_syncn_sysref_ctrl 0x0001e015 1 RW uint32 b[24:0] - - -
- - - - - rx_csr_sysref_always_on 0x0001e015 1 RW uint32 b[1:1] - - -
- - - - - rx_csr_rbd_offset 0x0001e015 1 RW uint32 b[10:3] - - -
- - - - - rx_csr_lmfc_offset 0x0001e015 1 RW uint32 b[19:12] - - -
- - - - - rx_err0 0x0001e018 1 RW uint32 b[8:0] - - -
- - - - - rx_err1 0x0001e019 1 RW uint32 b[9:0] - - -
- - - - - csr_dev_syncn 0x0001e020 1 RO uint32 b[0:0] - - -
- - - - - csr_rbd_count 0x0001e020 1 RO uint32 b[10:3] - - -
- - - - - rx_status1 0x0001e021 1 RW uint32 b[23:0] - - -
- - - - - rx_status2 0x0001e022 1 RW uint32 b[23:0] - - -
- - - - - rx_status3 0x0001e023 1 RW uint32 b[7:0] - - -
- - - - - rx_ilas_csr_l 0x0001e025 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_f 0x0001e025 1 RW uint32 b[15:8] - - -
- - - - - rx_ilas_csr_k 0x0001e025 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_m 0x0001e025 1 RW uint32 b[31:24] - - -
- - - - - rx_ilas_csr_n 0x0001e026 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_cs 0x0001e026 1 RW uint32 b[7:6] - - -
- - - - - rx_ilas_csr_np 0x0001e026 1 RW uint32 b[12:8] - - -
- - - - - rx_ilas_csr_subclassv 0x0001e026 1 RW uint32 b[15:13] - - -
- - - - - rx_ilas_csr_s 0x0001e026 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_jesdv 0x0001e026 1 RW uint32 b[23:21] - - -
- - - - - rx_ilas_csr_cf 0x0001e026 1 RW uint32 b[28:24] - - -
- - - - - rx_ilas_csr_hd 0x0001e026 1 RW uint32 b[31:31] - - -
- - - - - rx_status4 0x0001e03c 1 RW uint32 b[15:0] - - -
- - - - - rx_status5 0x0001e03d 1 RW uint32 b[15:0] - - -
- - - - - rx_status6 0x0001e03e 1 RW uint32 b[23:0] - - -
- - - - - rx_status7 0x0001e03f 1 RO uint32 b[31:0] - - -
- REG_DP_SHIFTRAM 1 12 REG shift 0x00020000 1 RW uint32 b[11:0] - 12 1
- REG_BSN_SOURCE 1 1 REG dp_on 0x00022000 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x00022000 1 RW uint32 b[1:1] - - -
- - - - - nof_block_per_sync 0x00022001 1 RW uint32 b[31:0] - - -
- - - - - bsn 0x00022002 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00022003 - - - b[31:0] b[63:32] - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00024000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00024001 - - - b[31:0] b[63:32] - -
- REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00026000 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00026000 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00026000 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00026001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00026002 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00026003 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00026004 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00026005 1 RO uint32 b[31:0] - - -
- - - - - bsn_first 0x00026006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00026007 - - - b[31:0] b[63:32] - -
- - - - - bsn_first_cycle_cnt 0x00026008 1 RO uint32 b[31:0] - - -
- REG_DIAG_WG 1 12 REG mode 0x00028000 1 RW uint32 b[7:0] - 48 4
- - - - - nof_samples 0x00028000 1 RW uint32 b[31:16] - - -
- - - - - phase 0x00028001 1 RW uint32 b[15:0] - - -
- - - - - freq 0x00028002 1 RW uint32 b[30:0] - - -
- - - - - ampl 0x00028003 1 RW uint32 b[16:0] - - -
+ REG_SDP_INFO 1 1 REG beamlet_scale 0x0001c000 1 RW uint32 b[15:0] - - -
+ - - - - block_period 0x0001c001 1 RO uint32 b[15:0] - - -
+ - - - - n_rn 0x0001c002 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x0001c003 1 RW uint32 b[7:0] - - -
+ - - - - n_si 0x0001c004 1 RW uint32 b[7:0] - - -
+ - - - - o_si 0x0001c005 1 RW uint32 b[7:0] - - -
+ - - - - beam_repositioning_flag 0x0001c006 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x0001c007 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x0001c008 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x0001c009 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x0001c00a 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x0001c00b 1 RO uint32 b[0:0] - - -
+ - - - - station_id 0x0001c00c 1 RW uint32 b[15:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x0001e000 1 RW uint32 b[31:31] - - -
+ JESD204B 1 1 REG rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - -
+ - - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x00020015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x00020018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x00020019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x00020020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x00020020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x00020021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x00020022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x00020023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x00020025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x00020025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x00020025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x00020025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x00020026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x00020026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x00020026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x00020026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x00020026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x00020026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x00020026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x00020026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0002003c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0002003d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0002003e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0002003f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - 12 1
+ REG_BSN_SOURCE 1 1 REG dp_on 0x00024000 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00024000 1 RW uint32 b[1:1] - - -
+ - - - - nof_block_per_sync 0x00024001 1 RW uint32 b[31:0] - - -
+ - - - - bsn 0x00024002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00024003 - - - b[31:0] b[63:32] - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00026000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00026001 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00028000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00028000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00028000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00028001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00028003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00028004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00028005 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00028006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028007 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00028008 1 RO uint32 b[31:0] - - -
+ REG_DIAG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - 48 4
+ - - - - nof_samples 0x0002a000 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x0002a001 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x0002a002 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x0002a003 1 RW uint32 b[16:0] - - -
RAM_DIAG_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - 16384 1024
REG_ADUH_MON 1 12 REG mean_sum 0x00030000 1 RO int64 b[31:0] b[31:0] 48 4
- - - - - 0x00030001 - - - b[31:0] b[63:32] - -
@@ -182,291 +195,278 @@ number_of_columns = 13
- - - - eth_destination_mac 0x0004a029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0004a02a - - - b[15:0] b[47:32] - -
- - - - word_align 0x0004a02b 1 RW uint32 b[15:0] - - -
- REG_SDP_INFO 1 1 REG beamlet_scale 0x0004c000 1 RW uint32 b[15:0] - - -
- - - - - block_period 0x0004c001 1 RO uint32 b[15:0] - - -
- - - - - n_rn 0x0004c002 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x0004c003 1 RW uint32 b[7:0] - - -
- - - - - n_si 0x0004c004 1 RW uint32 b[7:0] - - -
- - - - - o_si 0x0004c005 1 RW uint32 b[7:0] - - -
- - - - - beam_repositioning_flag 0x0004c006 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x0004c007 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x0004c008 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x0004c009 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x0004c00a 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x0004c00b 1 RO uint32 b[0:0] - - -
- - - - - station_id 0x0004c00c 1 RW uint32 b[15:0] - - -
- RAM_SS_SS_WIDE 2 6 RAM data 0x0004e000 976 RW uint32 b[9:0] - 8192 1024
- RAM_BF_WEIGHTS 2 12 RAM data 0x00054000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BF_SCALE 2 1 REG scale 0x0005c000 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x0005c001 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x0005e000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x0005e001 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x0005e002 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x0005e003 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x0005e004 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x0005e005 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x0005e006 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x0005e007 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0005e008 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x0005e009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x0005e00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x0005e00b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0005e00c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0005e00d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0005e00e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0005e00f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x0005e010 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x0005e011 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x0005e012 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x0005e013 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x0005e014 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x0005e015 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x0005e016 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x0005e017 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x0005e018 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0005e019 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0005e01a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0005e01b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0005e01c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0005e01d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0005e01e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0005e01f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x0005e020 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x0005e021 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x0005e022 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x0005e023 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x0005e024 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x0005e025 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x0005e026 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0005e027 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x0005e028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0005e029 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x00060000 1 RW uint32 b[0:0] - 1 1
- RAM_ST_BST 1 1 RAM data 0x00062000 1952 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00060001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 1 1 REG enable 0x00064000 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_INFO_BST 1 1 REG bsn 0x00066000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00066001 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x00066002 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x00066003 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x00066004 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x00066005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00066006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x00066006 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x00066006 1 RW uint32 b[31:16] - - -
- - - - - sdp_integration_interval 0x00066007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00066008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00066009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0006600a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0006600b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0006600c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0006600d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0006600e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0006600f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00066010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00066011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00066012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00066013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00066014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00066015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00066016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00066017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00066018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00066019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0006601a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0006601b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0006601c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0006601d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0006601e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0006601f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00066020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00066021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00066022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00066023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00066024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00066025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00066026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00066027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00066028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00066029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0006602a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0006602b 1 RW uint32 b[15:0] - - -
- REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00068000 1 RW uint32 b[0:0] - - -
- - - - - rx_transfer_status 0x00068001 1 RO uint32 b[0:0] - - -
- - - - - tx_transfer_control 0x00068002 1 RW uint32 b[0:0] - - -
- - - - - rx_padcrc_control 0x00068040 1 RW uint32 b[1:0] - - -
- - - - - rx_crccheck_control 0x00068080 1 RW uint32 b[1:0] - - -
- - - - - rx_pktovrflow_error 0x000680c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000680c1 - - - b[31:0] b[31:0] - -
- - - - - rx_pktovrflow_etherstatsdropevents 0x000680c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000680c3 - - - b[31:0] b[31:0] - -
- - - - - rx_lane_decoder_preamble_control 0x00068100 1 RW uint32 b[0:0] - - -
- - - - - rx_preamble_inserter_control 0x00068140 1 RW uint32 b[0:0] - - -
- - - - - rx_frame_control 0x00068800 1 RW uint32 b[19:0] - - -
- - - - - rx_frame_maxlength 0x00068801 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr0 0x00068802 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr1 0x00068803 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_0 0x00068804 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_1 0x00068805 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_0 0x00068806 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_1 0x00068807 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_0 0x00068808 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_1 0x00068809 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_0 0x0006880a 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_1 0x0006880b 1 RW uint32 b[15:0] - - -
- - - - - rx_pfc_control 0x00068818 1 RW uint32 b[16:0] - - -
- - - - - rx_stats_clr 0x00068c00 1 RW uint32 b[0:0] - - -
- - - - - rx_stats_framesok 0x00068c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c03 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_frameserr 0x00068c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c05 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_framescrcerr 0x00068c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c07 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_octetsok 0x00068c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c09 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pausemacctrl_frames 0x00068c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c0b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_iferrors 0x00068c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c0d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_framesok 0x00068c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c0f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_frameserr 0x00068c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c11 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastframesok 0x00068c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c13 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicast_frameserr 0x00068c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c15 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastframesok 0x00068c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c17 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcast_frameserr 0x00068c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c19 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatsoctets 0x00068c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c1b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatspkts 0x00068c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c1d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_undersizepkts 0x00068c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c1f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_oversizepkts 0x00068c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c21 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts64octets 0x00068c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c23 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts65to127octets 0x00068c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c25 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts128to255octets 0x00068c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c27 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts256to511octets 0x00068c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c29 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts512to1023octets 0x00068c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c2b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstat_pkts1024to1518octets 0x00068c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c2d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts1519toxoctets 0x00068c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c2f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_fragments 0x00068c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c31 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_jabbers 0x00068c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c33 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatscrcerr 0x00068c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c35 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicastmacctrlframes 0x00068c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c37 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastmac_ctrlframes 0x00068c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c39 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastmac_ctrlframes 0x00068c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c3b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pfcmacctrlframes 0x00068c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00068c3d - - - b[31:0] b[31:0] - -
- - - - - tx_transfer_status 0x00069001 1 RO uint32 b[0:0] - - -
- - - - - tx_padins_control 0x00069040 1 RW uint32 b[0:0] - - -
- - - - - tx_crcins_control 0x00069080 1 RW uint32 b[1:0] - - -
- - - - - tx_pktunderflow_error 0x000690c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000690c1 - - - b[31:0] b[31:0] - -
- - - - - tx_preamble_control 0x00069100 1 RW uint32 b[0:0] - - -
- - - - - tx_pauseframe_control 0x00069140 1 RW uint32 b[1:0] - - -
- - - - - tx_pauseframe_quanta 0x00069141 1 RW uint32 b[15:0] - - -
- - - - - tx_pauseframe_enable 0x00069142 1 RW uint32 b[0:0] - - -
- - - - - pfc_pause_quanta_0 0x00069180 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_1 0x00069181 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_2 0x00069182 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_3 0x00069183 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_4 0x00069184 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_5 0x00069185 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_6 0x00069186 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_7 0x00069187 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_0 0x00069190 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_1 0x00069191 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_2 0x00069192 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_3 0x00069193 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_4 0x00069194 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_5 0x00069195 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_6 0x00069196 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_7 0x00069197 1 RW uint32 b[31:0] - - -
- - - - - tx_pfc_priority_enable 0x000691a0 1 RW uint32 b[7:0] - - -
- - - - - tx_addrins_control 0x00069200 1 RW uint32 b[0:0] - - -
- - - - - tx_addrins_macaddr0 0x00069201 1 RW uint32 b[31:0] - - -
- - - - - tx_addrins_macaddr1 0x00069202 1 RW uint32 b[15:0] - - -
- - - - - tx_frame_maxlength 0x00069801 1 RW uint32 b[15:0] - - -
- - - - - tx_stats_clr 0x00069c00 1 RW uint32 b[0:0] - - -
- - - - - tx_stats_framesok 0x00069c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c03 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_frameserr 0x00069c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c05 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_framescrcerr 0x00069c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c07 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_octetsok 0x00069c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c09 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pausemacctrl_frames 0x00069c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c0b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_iferrors 0x00069c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c0d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_framesok 0x00069c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c0f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_frameserr 0x00069c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c11 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastframesok 0x00069c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c13 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicast_frameserr 0x00069c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c15 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastframesok 0x00069c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c17 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcast_frameserr 0x00069c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c19 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatsoctets 0x00069c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c1b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatspkts 0x00069c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c1d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_undersizepkts 0x00069c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c1f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_oversizepkts 0x00069c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c21 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts64octets 0x00069c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c23 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts65to127octets 0x00069c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c25 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts128to255octets 0x00069c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c27 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts256to511octets 0x00069c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c29 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts512to1023octets 0x00069c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c2b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstat_pkts1024to1518octets 0x00069c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c2d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts1519toxoctets 0x00069c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c2f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_fragments 0x00069c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c31 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_jabbers 0x00069c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c33 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatscrcerr 0x00069c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c35 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicastmacctrlframes 0x00069c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c37 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastmac_ctrlframes 0x00069c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c39 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastmac_ctrlframes 0x00069c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c3b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pfcmacctrlframes 0x00069c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00069c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0006a000 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x0006a000 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x0006a000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ RAM_SS_SS_WIDE 2 6 RAM data 0x0004c000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00050000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x00058000 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x00058001 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x0005a000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x0005a001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x0005a002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x0005a003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x0005a004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x0005a005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x0005a006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x0005a007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005a008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x0005a009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0005a00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0005a00b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0005a00c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0005a00d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0005a00e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0005a00f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0005a010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0005a011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0005a012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0005a013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0005a014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0005a015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0005a016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0005a017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0005a018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0005a019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0005a01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0005a01b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0005a01c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0005a01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0005a01e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0005a01f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0005a020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0005a021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0005a022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0005a023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0005a024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0005a025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0005a026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005a027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0005a028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005a029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x0005c000 1 RW uint32 b[0:0] - 1 1
+ RAM_ST_BST 1 1 RAM data 0x0005e000 1952 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005c001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 1 1 REG enable 0x00060000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_INFO_BST 1 1 REG bsn 0x00062000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00062001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00062002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00062003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00062004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00062005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00062006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00062006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00062006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00062007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00062008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00062009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0006200a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0006200b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0006200c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0006200d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0006200e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0006200f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00062010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00062011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00062012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00062013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00062014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00062015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00062016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00062017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00062018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00062019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0006201a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0006201b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0006201c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0006201d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0006201e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0006201f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00062020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00062021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00062022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00062023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00062024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00062025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00062026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00062027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00062028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00062029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0006202a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0006202b 1 RW uint32 b[15:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00064000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00064001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00064002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00064040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00064080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000640c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000640c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000640c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000640c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00064100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00064140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00064800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00064801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00064802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00064803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00064804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00064805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00064806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00064807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00064808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00064809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0006480a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0006480b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00064818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00064c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00064c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00064c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00064c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00064c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00064c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00064c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00064c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00064c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00064c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00064c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00064c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00064c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00064c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00064c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00064c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00064c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00064c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00064c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00064c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00064c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00064c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00064c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00064c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00064c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00064c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00064c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00064c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00064c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00064c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00064c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00065001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00065040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00065080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000650c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000650c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00065100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00065140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00065141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00065142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00065180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00065181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00065182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00065183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00065184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00065185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00065186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00065187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00065190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00065191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00065192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00065193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00065194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00065195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00065196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00065197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000651a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00065200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00065201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00065202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00065801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00065c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00065c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00065c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00065c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00065c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00065c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00065c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00065c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00065c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00065c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00065c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00065c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00065c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00065c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00065c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00065c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00065c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00065c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00065c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00065c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00065c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00065c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00065c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00065c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00065c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00065c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00065c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00065c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00065c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00065c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00065c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00066000 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x00066000 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00066000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 0462ee07fc37fb600588d5e788539ca51040162a..629006f70e379209faff73fc323875805973f7e9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -28,20 +28,19 @@ parameters:
- { name: c_W_sub_weight, value: 16 }
- { name: c_W_bf_weight, value: 16 }
- { name: c_W_beamlet_scale, value: 16 }
- - { name: c_W_beamlet_resolution, value: 0 - 15 } # EK: FIXME support passing on negative values, workaround use 0 - positive
+ - { name: c_W_beamlet_resolution, value: 0 - 15 } # EK: FIXME: support passing on negative values, workaround use 0 - positive
- { name: c_W_beamlet, value: 8 }
- { name: c_nof_clk_per_pps, value: c_f_adc_MHz * 10**6 } # = 200000000
- - { name: c_nof_block_per_sync, value: 195313 } # TBD temporarily use 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval, TODO: remove when REG_BSN_SOURCE_V2 is used
peripherals:
#############################################################################
# Factory / minimal (see ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
+ lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
mm_port_names:
@@ -84,6 +83,14 @@ peripherals:
mm_port_names:
- REG_REMU
+ #############################################################################
+ # SDP Info
+ #############################################################################
+
+ - peripheral_name: sdp/sdp_info
+ mm_port_names:
+ - REG_SDP_INFO
+
#############################################################################
# AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
#############################################################################
@@ -165,9 +172,12 @@ peripherals:
- peripheral_name: filter/fil_ppf_w
parameter_overrides:
- - { name: g_nof_taps, value: c_N_taps }
- - { name: g_nof_bands, value: c_N_fft }
- - { name: g_coef_dat_w, value: c_W_fir_coef }
+ - { name: g_fil_ppf.wb_factor, value: 1 } # process at sample rate (so no parallel wideband factor)
+ - { name: g_fil_ppf.nof_chan, value: 0 } # process at sample rate (so no serial time multiplexing)
+ - { name: g_fil_ppf.nof_bands, value: c_N_fft }
+ - { name: g_fil_ppf.nof_taps, value: c_N_taps }
+ - { name: g_fil_ppf.nof_streams, value: 1 }
+ - { name: g_fil_ppf.coef_dat_w, value: c_W_fir_coef }
mm_port_names:
- RAM_FIL_COEFS
@@ -218,12 +228,8 @@ peripherals:
# BF = Beamformer (from node_sdp_beamformer.vhd)
#############################################################################
- - peripheral_name: sdp/sdp_info
- mm_port_names:
- - REG_SDP_INFO
-
- peripheral_name: reorder/reorder_col_wide
- number_of_peripherals: c_N_beamsets # lofar2_unb2b_sdp_station.vhd
+ number_of_peripherals: c_N_beamsets
parameter_overrides:
- { name: g_wb_factor, value: c_P_pfb }
- { name: g_nof_ch_in, value: c_N_sub * c_Q_fft }
@@ -232,7 +238,7 @@ peripherals:
- RAM_SS_SS_WIDE
- peripheral_name: sdp/sdp_bf_weights
- number_of_peripherals: c_N_beamsets # lofar2_unb2b_sdp_station.vhd
+ number_of_peripherals: c_N_beamsets
parameter_overrides:
- { name: g_nof_instances, value: c_N_pol_bf * c_A_pn } # A_pn = P_pfb = 6
- { name: g_nof_gains, value: c_N_pol * c_S_sub_bf } # N_pol = Q_fft = 2
@@ -240,7 +246,7 @@ peripherals:
- RAM_BF_WEIGHTS
- peripheral_name: sdp/sdp_bf_scale
- number_of_peripherals: c_N_beamsets # lofar2_unb2b_sdp_station.vhd
+ number_of_peripherals: c_N_beamsets
parameter_overrides:
- { name: g_gain_w, value: c_W_beamlet_scale }
- { name: g_lsb_w, value: 0 - c_W_beamlet_resolution}
@@ -248,12 +254,12 @@ peripherals:
- REG_BF_SCALE
- peripheral_name: sdp/sdp_beamformer_output_hdr_dat
- number_of_peripherals: c_N_beamsets # lofar2_unb2b_sdp_station.vhd
+ number_of_peripherals: c_N_beamsets
mm_port_names:
- REG_HDR_DAT
- peripheral_name: dp/dp_xonoff
- number_of_peripherals: c_N_beamsets # lofar2_unb2b_sdp_station.vhd
+ number_of_peripherals: c_N_beamsets
parameter_overrides:
- { name: g_nof_streams, value: 1 }
- { name: g_combine_streams, value: False }
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
new file mode 100644
index 0000000000000000000000000000000000000000..715d30a6bca49381125b2bdd2a82e063122cab4e
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
@@ -0,0 +1,520 @@
+fpga_name = lofar2_unb2b_sdp_station
+number_of_columns = 13
+# There can be multiple lines with a single key. The host should ignore unknown keys.
+# The lines with columns follow after the number_of_columns keys. The host should ignore
+# the extra columns in case the mmap contains more columns than the host expects.
+#
+# col 1: mm_port_name, if - then it is part of previous MM port.
+# col 2: number of peripherals, if - then it is part of previous peripheral.
+# col 3: number of mm_ports, if - then it is part of previous MM port.
+# col 4: mm_port_type, if - then it is part of previous MM port.
+# col 5: field_name
+# col 6: field start address (in MM words)
+# col 7: number of fields, if - then it is part of previous field_name.
+# col 8: field access_mode, if - then it is part of previous field_name.
+# col 9: field radix, if - then it is part of previous field_name.
+# col 10: field mm_mask
+# col 11: field user_mask, if - then it is same as mm_mask
+# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
+# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
+#
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
+# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
+ PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
+ - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
+ - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
+ - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
+ - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
+ - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
+ - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
+ - - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
+ - - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
+ - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
+ - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
+ - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
+ - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
+ - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
+ REG_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x00012000 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x00012000 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x00012001 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x00012001 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x00012002 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x00014000 1 WO uint32 b[23:0] - - -
+ - - - - rden 0x00014001 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x00014002 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x00014003 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x00014004 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x00014005 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x00014006 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] - - -
+ - - - - param 0x0001a001 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0001a002 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0001a003 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0001a004 1 RO uint32 b[23:0] - - -
+ - - - - data_in 0x0001a005 1 WO uint32 b[23:0] - - -
+ - - - - busy 0x0001a006 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG beamlet_scale 0x0001c000 1 RW uint32 b[15:0] - - -
+ - - - - block_period 0x0001c001 1 RO uint32 b[15:0] - - -
+ - - - - n_rn 0x0001c002 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x0001c003 1 RW uint32 b[7:0] - - -
+ - - - - n_si 0x0001c004 1 RW uint32 b[7:0] - - -
+ - - - - o_si 0x0001c005 1 RW uint32 b[7:0] - - -
+ - - - - beam_repositioning_flag 0x0001c006 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x0001c007 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x0001c008 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x0001c009 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x0001c00a 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x0001c00b 1 RO uint32 b[0:0] - - -
+ - - - - station_id 0x0001c00c 1 RW uint32 b[15:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x0001e000 1 RW uint32 b[31:31] - - -
+ JESD204B 1 1 REG rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - -
+ - - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x00020015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x00020018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x00020019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x00020020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x00020020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x00020021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x00020022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x00020023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x00020025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x00020025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x00020025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x00020025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x00020026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x00020026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x00020026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x00020026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x00020026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x00020026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x00020026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x00020026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0002003c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0002003d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0002003e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0002003f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - 12 1
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00024000 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00024000 1 RW uint32 b[1:1] - - -
+ - - - - nof_block_per_sync 0x00024001 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x00024002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00024003 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x00024004 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00026000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00026001 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00028000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00028000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00028000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00028001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00028003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00028004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00028005 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00028006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028007 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00028008 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - 48 4
+ - - - - nof_samples 0x0002a000 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x0002a001 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x0002a002 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x0002a003 1 RW uint32 b[16:0] - - -
+ RAM_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - 16384 1024
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x00030000 1 RO int64 b[31:0] b[31:0] 48 4
+ - - - - - 0x00030001 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x00030002 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x00030003 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00032000 1 RO uint32 b[31:0] - 24 2
+ - - - - word_cnt 0x00032001 1 RO uint32 b[31:0] - - -
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00034000 1024 RW uint32 b[15:0] - 16384 1024
+ REG_SI 1 1 REG enable 0x00038000 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW uint32 b[15:0] - 16384 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - 8192 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x00042000 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x00044000 2048 RW uint64 b[31:0] b[31:0] 16384 2048
+ - - - - - 0x00042001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x00048000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x0004a000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004a001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x0004a002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_statistics_per_packet 0x0004a003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_bytes_per_statistic 0x0004a004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_nof_signal_inputs 0x0004a005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x0004a006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_sst_signal_input_index 0x0004a006 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_sst_reserved 0x0004a006 1 RW uint32 b[31:8] - - -
+ - - - - sdp_integration_interval 0x0004a007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x0004a008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x0004a009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0004a00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0004a00b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0004a00c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004a00d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004a00e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004a00f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0004a010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0004a011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0004a012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0004a013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0004a014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0004a015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0004a016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0004a017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0004a018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0004a019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0004a01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004a01b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004a01c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004a01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004a01e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004a01f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0004a020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0004a021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0004a022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0004a023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0004a024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0004a025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0004a026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0004a027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004a028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0004a029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004a02a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0004a02b 1 RW uint32 b[15:0] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x0004c000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00050000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x00058000 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x00058001 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x0005a000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x0005a001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x0005a002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x0005a003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x0005a004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x0005a005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x0005a006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x0005a007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005a008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x0005a009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0005a00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0005a00b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0005a00c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0005a00d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0005a00e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0005a00f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0005a010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0005a011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0005a012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0005a013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0005a014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0005a015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0005a016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0005a017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0005a018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0005a019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0005a01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0005a01b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0005a01c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0005a01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0005a01e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0005a01f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0005a020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0005a021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0005a022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0005a023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0005a024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0005a025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0005a026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005a027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0005a028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005a029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x0005c000 1 RW uint32 b[0:0] - 1 1
+ RAM_ST_BST 1 1 RAM data 0x0005e000 1952 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005c001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST_0 1 1 REG enable 0x00060000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_BST_0 1 1 REG bsn 0x00062000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00062001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00062002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00062003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00062004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00062005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00062006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00062006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00062006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00062007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00062008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00062009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0006200a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0006200b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0006200c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0006200d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0006200e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0006200f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00062010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00062011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00062012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00062013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00062014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00062015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00062016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00062017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00062018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00062019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0006201a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0006201b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0006201c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0006201d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0006201e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0006201f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00062020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00062021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00062022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00062023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00062024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00062025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00062026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00062027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00062028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00062029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0006202a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0006202b 1 RW uint32 b[15:0] - - -
+ REG_STAT_ENABLE_BST_1 1 1 REG enable 0x00064000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_BST_1 1 1 REG bsn 0x00066000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00066001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00066002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00066003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00066004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00066005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00066006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00066006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00066006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00066007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00066008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00066009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0006600a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0006600b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0006600c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0006600d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0006600e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0006600f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00066010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00066011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00066012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00066013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00066014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00066015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00066016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00066017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00066018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00066019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0006601a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0006601b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0006601c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0006601d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0006601e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0006601f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00066020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00066021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00066022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00066023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00066024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00066025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00066026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00066027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00066028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00066029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0006602a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0006602b 1 RW uint32 b[15:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00068000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00068001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00068002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00068040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00068080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000680c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000680c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000680c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000680c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00068100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00068140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00068800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00068801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00068802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00068803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00068804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00068805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00068806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00068807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00068808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00068809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0006880a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0006880b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00068818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00068c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00068c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00068c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00068c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00068c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00068c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00068c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00068c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00068c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00068c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00068c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00068c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00068c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00068c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00068c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00068c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00068c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00068c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00068c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00068c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00068c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00068c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00068c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00068c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00068c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00068c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00068c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00068c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00068c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00068c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00068c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00068c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00069001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00069040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00069080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000690c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000690c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00069100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00069140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00069141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00069142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00069180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00069181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00069182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00069183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00069184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00069185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00069186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00069187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00069190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00069191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00069192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00069193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00069194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00069195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00069196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00069197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000691a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00069200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00069201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00069202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00069801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00069c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00069c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00069c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00069c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00069c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00069c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00069c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00069c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00069c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00069c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00069c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00069c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00069c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00069c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00069c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00069c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00069c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00069c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00069c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00069c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00069c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00069c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00069c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00069c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00069c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00069c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00069c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00069c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00069c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00069c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00069c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00069c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0006a000 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x0006a000 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x0006a000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
new file mode 100644
index 0000000000000000000000000000000000000000..5c516153907c7299071b9c4d8de7baa954e7a5c6
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
@@ -0,0 +1,520 @@
+fpga_name = lofar2_unb2b_sdp_station
+number_of_columns = 13
+# There can be multiple lines with a single key. The host should ignore unknown keys.
+# The lines with columns follow after the number_of_columns keys. The host should ignore
+# the extra columns in case the mmap contains more columns than the host expects.
+#
+# col 1: mm_port_name, if - then it is part of previous MM port.
+# col 2: number of peripherals, if - then it is part of previous peripheral.
+# col 3: number of mm_ports, if - then it is part of previous MM port.
+# col 4: mm_port_type, if - then it is part of previous MM port.
+# col 5: field_name
+# col 6: field start address (in MM words)
+# col 7: number of fields, if - then it is part of previous field_name.
+# col 8: field access_mode, if - then it is part of previous field_name.
+# col 9: field radix, if - then it is part of previous field_name.
+# col 10: field mm_mask
+# col 11: field user_mask, if - then it is same as mm_mask
+# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
+# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
+#
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
+# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00004000 32768 RO char8 b[31:0] b[7:0] - -
+ PIO_SYSTEM_INFO 1 1 REG info 0x00000000 1 RO uint32 b[31:0] - - -
+ - - - - info_gn_index 0x00000000 1 RO uint32 b[7:0] - - -
+ - - - - info_hw_version 0x00000000 1 RO uint32 b[9:8] - - -
+ - - - - info_cs_sim 0x00000000 1 RO uint32 b[10:10] - - -
+ - - - - info_fw_version_major 0x00000000 1 RO uint32 b[19:16] - - -
+ - - - - info_fw_version_minor 0x00000000 1 RO uint32 b[23:20] - - -
+ - - - - info_rom_version 0x00000000 1 RO uint32 b[26:24] - - -
+ - - - - info_technology 0x00000000 1 RO uint32 b[31:27] - - -
+ - - - - use_phy 0x00000001 1 RO uint32 b[7:0] - - -
+ - - - - design_name 0x00000002 52 RO char8 b[31:0] b[7:0] - -
+ - - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
+ - - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
+ - - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
+ - - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
+ REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x00000df8 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00000de0 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x0002d032 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x0002d032 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x0002d032 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x0002d033 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x0002d033 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x0002d034 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x0002d000 1 WO uint32 b[23:0] - - -
+ - - - - rden 0x0002d001 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x0002d002 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x0002d003 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x0002d004 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x0002d005 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x0002d006 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x0002d030 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x0002d02e 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x0002d02c 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x0002d02d 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x0002d02a 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x0002d008 1 WO uint32 b[31:0] - - -
+ - - - - param 0x0002d009 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0002d00a 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0002d00b 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0002d00c 1 RO uint32 b[23:0] - - -
+ - - - - data_in 0x0002d00d 1 WO uint32 b[23:0] - - -
+ - - - - busy 0x0002d00e 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG beamlet_scale 0x00000dd0 1 RW uint32 b[15:0] - - -
+ - - - - block_period 0x00000dd1 1 RO uint32 b[15:0] - - -
+ - - - - n_rn 0x00000dd2 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x00000dd3 1 RW uint32 b[7:0] - - -
+ - - - - n_si 0x00000dd4 1 RW uint32 b[7:0] - - -
+ - - - - o_si 0x00000dd5 1 RW uint32 b[7:0] - - -
+ - - - - beam_repositioning_flag 0x00000dd6 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x00000dd7 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x00000dd8 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x00000dd9 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x00000dda 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x00000ddb 1 RO uint32 b[0:0] - - -
+ - - - - station_id 0x00000ddc 1 RW uint32 b[15:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x0002d020 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x0002d020 1 RW uint32 b[31:31] - - -
+ JESD204B 1 1 REG rx_dll_ctrl 0x0002c014 1 RW uint32 b[16:0] - - -
+ - - - - rx_syncn_sysref_ctrl 0x0002c015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x0002c015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x0002c015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x0002c015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x0002c018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x0002c019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x0002c020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x0002c020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x0002c021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x0002c022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x0002c023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x0002c025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x0002c025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x0002c025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x0002c025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x0002c026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x0002c026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x0002c026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x0002c026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x0002c026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x0002c026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x0002c026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x0002c026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0002c03c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0002c03d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0002c03e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0002c03f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00000c20 1 RW uint32 b[11:0] - 16 1
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00000df0 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00000df0 1 RW uint32 b[1:1] - - -
+ - - - - nof_block_per_sync 0x00000df1 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x00000df2 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000df3 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x00000df4 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x0002d026 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0002d027 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x00000cc0 1 RW uint32 b[7:0] - 64 4
+ - - - - nof_samples 0x00000cc0 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x00000cc1 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x00000cc2 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x00000cc3 1 RW uint32 b[16:0] - - -
+ RAM_WG 1 12 RAM data 0x00020000 1024 RW uint32 b[17:0] - 16384 1024
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x00000d00 1 RO int64 b[31:0] b[31:0] 64 4
+ - - - - - 0x00000d01 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x00000d02 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x00000d03 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - 32 2
+ - - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - -
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[15:0] - 16384 1024
+ REG_SI 1 1 REG enable 0x0002d028 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - 16384 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00006000 1024 RW cint16_ir b[31:0] - 8192 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x0002d024 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x00028000 2048 RW uint64 b[31:0] b[31:0] 16384 2048
+ - - - - - 0x0002d025 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x0002d01e 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c80 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c81 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00000c82 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_statistics_per_packet 0x00000c83 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_bytes_per_statistic 0x00000c84 1 RW uint32 b[7:0] - - -
+ - - - - sdp_nof_signal_inputs 0x00000c85 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000c86 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_sst_signal_input_index 0x00000c86 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_sst_reserved 0x00000c86 1 RW uint32 b[31:8] - - -
+ - - - - sdp_integration_interval 0x00000c87 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000c88 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000c89 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x00000c8a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x00000c8b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x00000c8c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x00000c8d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x00000c8e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x00000c8f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000c90 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000c91 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000c92 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000c93 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000c94 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000c95 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000c96 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000c97 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000c98 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000c99 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000c9a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x00000c9b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x00000c9c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x00000c9d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x00000c9e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x00000c9f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000ca0 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000ca1 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000ca2 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000ca3 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000ca4 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000ca5 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000ca6 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000ca7 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000ca8 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000ca9 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000caa - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x00000cab 1 RW uint32 b[15:0] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x0001c000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00010000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x0002d014 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x0002d015 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x00000080 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00000081 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00000082 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x00000083 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x00000084 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x00000085 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x00000086 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x00000087 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000088 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x00000089 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0000008a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0000008b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0000008c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0000008d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0000008e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0000008f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000090 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000091 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000092 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000093 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000094 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000095 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000096 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000097 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000098 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000099 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0000009a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0000009b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0000009c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0000009d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0000009e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0000009f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x000000a0 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x000000a1 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x000000a2 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x000000a3 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x000000a4 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x000000a5 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x000000a6 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000000a7 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x000000a8 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000000a9 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x0002d010 1 RW uint32 b[0:0] - 1 1
+ RAM_ST_BST 1 1 RAM data 0x00001000 1952 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0002d011 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST_0 1 1 REG enable 0x0002d01c 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_BST_0 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000041 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00000043 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00000044 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00000045 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000046 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00000046 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00000046 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00000047 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000048 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000049 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0000004a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0000004b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0000004c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0000004d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0000004e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0000004f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000050 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000051 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000052 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000053 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000054 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000055 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000056 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000057 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000058 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000059 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0000005a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0000005b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0000005c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0000005d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0000005e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0000005f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000060 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000061 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000062 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000063 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000064 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000065 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000066 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000067 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000068 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0000006a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
+ REG_STAT_ENABLE_BST_1 1 1 REG enable 0x0002d01a 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_BST_1 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00000c42 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00000c43 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00000c44 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00000c45 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000c46 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00000c46 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00000c46 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00000c47 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000c48 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000c49 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x00000c4a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x00000c4c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x00000c4d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x00000c4e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x00000c4f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000c50 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000c51 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000c52 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000c53 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000c54 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000c55 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000c56 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000c57 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000c58 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000c59 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000c5a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x00000c5b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x00000c5c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x00000c5d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x00000c5e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x00000c5f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000c60 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000c61 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000c62 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000c63 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000c64 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000c65 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000c66 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000c67 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c68 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00002000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00002001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00002002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00002040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00002080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000020c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000020c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000020c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000020c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00002100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00002140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00002800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00002801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00002802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00002803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00002804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00002805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00002806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00002807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00002808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00002809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0000280a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0000280b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00002818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00002c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00002c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00002c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00002c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00002c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00002c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00002c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00002c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00002c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00002c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00002c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00002c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00002c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00002c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00002c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00002c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00002c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00002c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00002c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00002c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00002c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00002c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00002c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00002c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00002c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00002c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00002c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00002c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00002c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00002c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00002c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00003001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00003040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00003080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000030c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000030c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00003100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00003140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00003141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00003142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00003180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00003181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00003182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00003183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00003184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00003185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00003186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00003187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00003190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00003191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00003192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00003193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00003194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00003195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00003196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00003197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000031a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00003200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00003201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00003202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00003801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00003c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00003c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00003c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00003c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00003c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00003c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00003c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00003c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00003c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00003c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00003c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00003c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00003c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00003c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00003c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00003c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00003c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00003c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00003c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00003c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00003c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00003c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00003c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00003c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00003c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00003c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00003c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00003c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00003c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00003c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00003c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0002d022 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x0002d022 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x0002d022 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/images/images.txt b/applications/lofar2/images/images.txt
index 8868ddf4a320adb12733de746f580b7c9642fda1..29135b8ae552db29d9b56d622121a6c8b0bbe813 100644
--- a/applications/lofar2/images/images.txt
+++ b/applications/lofar2/images/images.txt
@@ -4,7 +4,7 @@ unb2b_minimal-r03350b9b9 | 2021-03-19 |
lofar2_unb2b_filterbank_full-r8a75c955b | 2021-03-01 | R vd Walle | Deprecated, better use lofar2_unb2b_sdp_station_fsub-rc125dfd6d
lofar2_unb2b_sdp_station_adc-rc125dfd6d | 2021-04-21 | J. Hargreaves | -
lofar2_unb2b_sdp_station_adc-r087d98be6 | 2021-06-14 | J. Hargreaves | -
-lofar2_unb2b_sdp_station_fsub-ra84011947 | 2021-06-11 | R vd Walle | See $UPE_GEAR/peripherals/tc_lofar2_unb2b_filterbank.py
+lofar2_unb2b_sdp_station_fsub-rbc8dc7f66 | 2021-06-23 | R vd Walle | See $UPE_GEAR/peripherals/tc_lofar2_unb2b_filterbank.py
lofar2_unb2b_sdp_station_bf-rc125dfd6d | 2021-04-21 | R vd Walle | See $UPE_GEAR/peripherals/tc_lofar2_unb2b_beamformer.py
lofar2_unb2b_sdp_station_bf-r087d98be6 | 2021-06-14 | R vd Walle | See $UPE_GEAR/peripherals/tc_lofar2_unb2b_beamformer.py
lofar2_unb2b_sdp_station_xsub_one-r087d98be6 | 2021-06-14 | R vd Walle |
diff --git a/applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-ra84011947.tar.gz b/applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-rbc8dc7f66.tar.gz
similarity index 54%
rename from applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-ra84011947.tar.gz
rename to applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-rbc8dc7f66.tar.gz
index e623c101226360cf17400d070541a1fd71c5acce..e8682233268a6a5f5b9e1a848437319f942ba078 100644
Binary files a/applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-ra84011947.tar.gz and b/applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-rbc8dc7f66.tar.gz differ
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index 58bd7d22dccf0090f87864f2266bd4a486847293..b74bbd3a32ca0092cb3dbdf5e7165cf2cc0fe0a2 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -701,6 +701,8 @@ Start --> Administration --> Synaptic package manager
> sudo pip install numpy # to run Python2 library installer as root
> sudo pip3 install numpy # to run Python3 library installer as root
+> sudo apt-get install python3-tk # worked, now I can do: python3 test_plot.py
+
> sudo apt-get install pip # to install Python2 library installer
> sudo apt-get install python-matplotlib
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 79591b0b305fbab6107ee2acb05afe6e709a73ef..ba09970a6f98b5f6896ef7036894ca27fa5b024f 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -325,36 +325,42 @@ PACKAGE common_pkg IS
-- . Note that using func_slv_concat() without the BOOLEAN use_* is equivalent to using the
-- slv concatenation operator & directly. However this overloaded func_slv_concat() is
-- still nice to have, because it shows the relation with the inverse func_slv_extract().
- FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e : BOOLEAN; a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( use_a, use_b, use_c, use_d : BOOLEAN; a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( use_a, use_b, use_c : BOOLEAN; a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( use_a, use_b : BOOLEAN; a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_concat_w(use_a, use_b : BOOLEAN; a_w, b_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( use_a, use_b : BOOLEAN; a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+
+ FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a, b, c, d, e, f, g, h : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e : BOOLEAN; a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b, use_c, use_d : BOOLEAN; a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b, use_c : BOOLEAN; a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b : BOOLEAN; a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d, e, f, g, h : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b : BOOLEAN; a_w, b_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b : BOOLEAN; a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
FUNCTION TO_UINT(vec : STD_LOGIC_VECTOR) RETURN NATURAL; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
FUNCTION TO_SINT(vec : STD_LOGIC_VECTOR) RETURN INTEGER;
@@ -1508,10 +1514,9 @@ PACKAGE BODY common_pkg IS
RETURN v_mat;
END;
-
- -- Support concatenation of up to 7 slv into 1 slv
- FUNCTION func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
- CONSTANT c_max_w : NATURAL := a'LENGTH + b'LENGTH + c'LENGTH + d'LENGTH + e'LENGTH + f'LENGTH + g'LENGTH;
+ -- Support concatenation of up to 8 slv into 1 slv
+ FUNCTION func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a, b, c, d, e, f, g, h : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ CONSTANT c_max_w : NATURAL := a'LENGTH + b'LENGTH + c'LENGTH + d'LENGTH + e'LENGTH + f'LENGTH + g'LENGTH + h'LENGTH;
VARIABLE v_res : STD_LOGIC_VECTOR(c_max_w-1 DOWNTO 0) := (OTHERS=>'0');
VARIABLE v_len : NATURAL := 0;
BEGIN
@@ -1522,34 +1527,45 @@ PACKAGE BODY common_pkg IS
IF use_e = TRUE THEN v_res(e'LENGTH-1 + v_len DOWNTO v_len) := e; v_len := v_len + e'LENGTH; END IF;
IF use_f = TRUE THEN v_res(f'LENGTH-1 + v_len DOWNTO v_len) := f; v_len := v_len + f'LENGTH; END IF;
IF use_g = TRUE THEN v_res(g'LENGTH-1 + v_len DOWNTO v_len) := g; v_len := v_len + g'LENGTH; END IF;
+ IF use_h = TRUE THEN v_res(h'LENGTH-1 + v_len DOWNTO v_len) := h; v_len := v_len + h'LENGTH; END IF;
RETURN v_res(v_len-1 DOWNTO 0);
END func_slv_concat;
-
+
+ FUNCTION func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g, FALSE, a, b, c, d, e, f, g, "0");
+ END func_slv_concat;
+
FUNCTION func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, a, b, c, d, e, f, "0");
+ RETURN func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, FALSE, a, b, c, d, e, f, "0", "0");
END func_slv_concat;
FUNCTION func_slv_concat(use_a, use_b, use_c, use_d, use_e : BOOLEAN; a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_concat(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, a, b, c, d, e, "0", "0");
+ RETURN func_slv_concat(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, FALSE, a, b, c, d, e, "0", "0", "0");
END func_slv_concat;
FUNCTION func_slv_concat(use_a, use_b, use_c, use_d : BOOLEAN; a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_concat(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, a, b, c, d, "0", "0", "0");
+ RETURN func_slv_concat(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, FALSE, a, b, c, d, "0", "0", "0", "0");
END func_slv_concat;
FUNCTION func_slv_concat(use_a, use_b, use_c : BOOLEAN; a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_concat(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, a, b, c, "0", "0", "0", "0");
+ RETURN func_slv_concat(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, FALSE, a, b, c, "0", "0", "0", "0", "0");
END func_slv_concat;
FUNCTION func_slv_concat(use_a, use_b : BOOLEAN; a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_concat(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, a, b, "0", "0", "0", "0", "0");
+ RETURN func_slv_concat(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, a, b, "0", "0", "0", "0", "0", "0");
END func_slv_concat;
-
+
+ FUNCTION func_slv_concat(a, b, c, d, e, f, g, h : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_concat(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a, b, c, d, e, f, g, h);
+ END func_slv_concat;
+
FUNCTION func_slv_concat(a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN func_slv_concat(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a, b, c, d, e, f, g);
@@ -1580,7 +1596,7 @@ PACKAGE BODY common_pkg IS
RETURN func_slv_concat(TRUE, TRUE, a, b);
END func_slv_concat;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL) RETURN NATURAL IS
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL) RETURN NATURAL IS
VARIABLE v_len : NATURAL := 0;
BEGIN
IF use_a = TRUE THEN v_len := v_len + a_w; END IF;
@@ -1590,36 +1606,42 @@ PACKAGE BODY common_pkg IS
IF use_e = TRUE THEN v_len := v_len + e_w; END IF;
IF use_f = TRUE THEN v_len := v_len + f_w; END IF;
IF use_g = TRUE THEN v_len := v_len + g_w; END IF;
+ IF use_h = TRUE THEN v_len := v_len + h_w; END IF;
RETURN v_len;
END func_slv_concat_w;
-
+
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL) RETURN NATURAL IS
+ BEGIN
+ RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, g_w, 0);
+ END func_slv_concat_w;
+
FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL) RETURN NATURAL IS
BEGIN
- RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, 0);
+ RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, 0, 0);
END func_slv_concat_w;
FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL) RETURN NATURAL IS
BEGIN
- RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, 0, 0);
+ RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, 0, 0, 0);
END func_slv_concat_w;
FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL) RETURN NATURAL IS
BEGIN
- RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, 0, 0, 0);
+ RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, 0, 0, 0, 0);
END func_slv_concat_w;
FUNCTION func_slv_concat_w(use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL) RETURN NATURAL IS
BEGIN
- RETURN func_slv_concat_w(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, 0, 0, 0, 0);
+ RETURN func_slv_concat_w(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, 0, 0, 0, 0, 0);
END func_slv_concat_w;
FUNCTION func_slv_concat_w(use_a, use_b : BOOLEAN; a_w, b_w : NATURAL) RETURN NATURAL IS
BEGIN
- RETURN func_slv_concat_w(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, 0, 0, 0, 0, 0);
+ RETURN func_slv_concat_w(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, 0, 0, 0, 0, 0, 0);
END func_slv_concat_w;
-
+
-- extract slv
- FUNCTION func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ FUNCTION func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
VARIABLE v_w : NATURAL := 0;
VARIABLE v_lo : NATURAL := 0;
BEGIN
@@ -1660,36 +1682,55 @@ PACKAGE BODY common_pkg IS
IF use_d = TRUE THEN v_lo := v_lo + d_w; END IF;
IF use_e = TRUE THEN v_lo := v_lo + e_w; END IF;
IF use_f = TRUE THEN v_lo := v_lo + f_w; END IF;
+ WHEN 7 =>
+ IF use_h = TRUE THEN v_w := h_w; ELSE RETURN c_slv0(h_w-1 DOWNTO 0); END IF;
+ IF use_a = TRUE THEN v_lo := v_lo + a_w; END IF;
+ IF use_b = TRUE THEN v_lo := v_lo + b_w; END IF;
+ IF use_c = TRUE THEN v_lo := v_lo + c_w; END IF;
+ IF use_d = TRUE THEN v_lo := v_lo + d_w; END IF;
+ IF use_e = TRUE THEN v_lo := v_lo + e_w; END IF;
+ IF use_f = TRUE THEN v_lo := v_lo + f_w; END IF;
+ IF use_g = TRUE THEN v_lo := v_lo + g_w; END IF;
WHEN OTHERS => REPORT "Unknown common_pkg func_slv_extract argument" SEVERITY FAILURE;
END CASE;
RETURN vec(v_w-1 + v_lo DOWNTO v_lo); -- extracted slv
END func_slv_extract;
-
+
+ FUNCTION func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, g_w, 0, vec, sel);
+ END func_slv_extract;
+
FUNCTION func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, 0, vec, sel);
+ RETURN func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, 0, 0, vec, sel);
END func_slv_extract;
FUNCTION func_slv_extract(use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_extract(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, 0, 0, vec, sel);
+ RETURN func_slv_extract(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, 0, 0, 0, vec, sel);
END func_slv_extract;
FUNCTION func_slv_extract(use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_extract(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, 0, 0, 0, vec, sel);
+ RETURN func_slv_extract(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, 0, 0, 0, 0, vec, sel);
END func_slv_extract;
FUNCTION func_slv_extract(use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_extract(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, 0, 0, 0, 0, vec, sel);
+ RETURN func_slv_extract(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, 0, 0, 0, 0, 0, vec, sel);
END func_slv_extract;
FUNCTION func_slv_extract(use_a, use_b : BOOLEAN; a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_extract(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, 0, 0, 0, 0, 0, vec, sel);
+ RETURN func_slv_extract(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, 0, 0, 0, 0, 0, 0, vec, sel);
END func_slv_extract;
-
+
+ FUNCTION func_slv_extract(a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_extract(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w, vec, sel);
+ END func_slv_extract;
+
FUNCTION func_slv_extract(a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN func_slv_extract(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a_w, b_w, c_w, d_w, e_w, f_w, g_w, vec, sel);
diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 35eb45f99ba31ed7867ddb948437b64012e445f1..39ca669c8f184bc1e880bf341840641e720fd402 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -43,8 +43,10 @@ synth_files =
src/vhdl/dp_shiftreg.vhd
src/vhdl/dp_fifo_info.vhd
src/vhdl/dp_fifo_core.vhd
+ src/vhdl/dp_fifo_core_arr.vhd
src/vhdl/dp_fifo_sc.vhd
src/vhdl/dp_fifo_dc.vhd
+ src/vhdl/dp_fifo_dc_arr.vhd
src/vhdl/dp_fifo_dc_mixed_widths.vhd
src/vhdl/dp_fifo_fill_core.vhd
src/vhdl/dp_fifo_fill_sc.vhd
@@ -219,6 +221,7 @@ test_bench_files =
tb/vhdl/tb_dp_fifo_fill_sc.vhd
tb/vhdl/tb_dp_fifo_info.vhd
tb/vhdl/tb_dp_fifo_dc.vhd
+ tb/vhdl/tb_dp_fifo_dc_arr.vhd
tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
tb/vhdl/tb_dp_fifo_sc.vhd
tb/vhdl/tb_dp_fifo_to_mm.vhd
@@ -291,6 +294,7 @@ test_bench_files =
tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
tb/vhdl/tb_tb_dp_fifo_dc.vhd
+ tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
tb/vhdl/tb_tb_dp_frame_scheduler.vhd
tb/vhdl/tb_tb_dp_latency_fifo.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bf5fcd921ed889ca348433387b814f265bb68786
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
@@ -0,0 +1,311 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose:
+-- Provide input ready control and use output ready control to the FIFO.
+-- Pass sop and eop along with the data through the FIFO if g_use_ctrl=TRUE.
+-- Default the RL=1, use g_fifo_rl=0 for a the show ahead FIFO.
+-- Description:
+-- Provide the sink ready for FIFO write control and use source ready for
+-- FIFO read access. The sink ready output is derived from FIFO almost full.
+-- Data without framing can use g_use_ctrl=FALSE to avoid implementing two
+-- data bits for sop and eop in the FIFO word width. Idem for g_use_sync,
+-- g_use_empty, g_use_channel, g_use_error and g_use_aux.
+-- Remark:
+-- . The bsn, empty, channel and error fields are valid at the sop and or eop.
+-- Therefore alternatively these fields can be passed on through a separate
+-- FIFO, with only one entry per frame, to save FIFO memory in case
+-- concatenating them makes the FIFO word width larger than a standard
+-- memory data word width.
+-- . The FIFO makes that the src_in.ready and snk_out.ready are not
+-- combinatorially connected, so this can ease the timing closure for the
+-- ready signal.
+-- . It is assumed all inputs are synchronous (identical control signals).
+-- If the inputs are asynchronous, better use multiple instances of
+-- dp_fifo_core.
+-- . It is possible to use additonal signals to the fifo using in_aux/out_aux.
+
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY dp_fifo_core_arr IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ g_nof_streams : NATURAL := 1;
+ g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_use_dual_clock : BOOLEAN := FALSE;
+ g_use_lut_sc : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
+ g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_bsn_w : NATURAL := 1;
+ g_empty_w : NATURAL := 1;
+ g_channel_w : NATURAL := 1;
+ g_error_w : NATURAL := 1;
+ g_aux_w : NATURAL := 1;
+ g_use_bsn : BOOLEAN := FALSE;
+ g_use_empty : BOOLEAN := FALSE;
+ g_use_channel : BOOLEAN := FALSE;
+ g_use_error : BOOLEAN := FALSE;
+ g_use_sync : BOOLEAN := FALSE;
+ g_use_aux : BOOLEAN := FALSE; -- extra signal in_aux/out_aux
+ g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
+ g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_rl : NATURAL := 1
+ );
+ PORT (
+ wr_rst : IN STD_LOGIC;
+ wr_clk : IN STD_LOGIC;
+ rd_rst : IN STD_LOGIC;
+ rd_clk : IN STD_LOGIC;
+ -- Monitor FIFO filling
+ wr_ful : OUT STD_LOGIC; -- corresponds to the carry bit of wr_usedw when FIFO is full
+ wr_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_emp : OUT STD_LOGIC;
+ -- ST sink
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ in_aux : IN STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0) := (OTHERS => '0');
+ -- ST source
+ src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_aux : OUT STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0)
+ );
+END dp_fifo_core_arr;
+
+
+ARCHITECTURE str OF dp_fifo_core_arr IS
+
+ CONSTANT c_use_data : BOOLEAN := TRUE;
+ CONSTANT c_total_data_w : NATURAL := g_nof_streams * g_data_w;
+ CONSTANT c_ctrl_w : NATURAL := 2; -- sop and eop
+
+ CONSTANT c_complex_w : NATURAL := smallest(c_dp_stream_dsp_data_w, g_data_w/2); -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
+
+ CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size-g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
+ CONSTANT c_fifo_dat_w : NATURAL := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
+ c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w); -- concat via FIFO
+
+ SIGNAL nxt_snk_out : t_dp_siso := c_dp_siso_rst;
+
+ SIGNAL arst : STD_LOGIC;
+
+ TYPE t_wr_data_complex_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(2*c_complex_w-1 DOWNTO 0);
+ TYPE t_rd_data_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
+
+ SIGNAL wr_data_complex_arr : t_wr_data_complex_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL wr_data : STD_LOGIC_VECTOR(c_total_data_w-1 DOWNTO 0);
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_total_data_w-1 DOWNTO 0);
+ SIGNAL rd_data_arr : t_rd_data_arr(g_nof_streams-1 DOWNTO 0);
+
+ SIGNAL fifo_wr_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0);
+ SIGNAL fifo_wr_req : STD_LOGIC;
+ SIGNAL fifo_wr_ful : STD_LOGIC;
+ SIGNAL fifo_wr_usedw : STD_LOGIC_VECTOR(wr_usedw'RANGE);
+
+ SIGNAL fifo_rd_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL fifo_rd_val : STD_LOGIC;
+ SIGNAL fifo_rd_req : STD_LOGIC;
+ SIGNAL fifo_rd_emp : STD_LOGIC;
+ SIGNAL fifo_rd_usedw : STD_LOGIC_VECTOR(rd_usedw'RANGE);
+
+ SIGNAL wr_sync : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL rd_sync : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL wr_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL rd_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL wr_aux : STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0);
+
+ SIGNAL rd_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rd_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- initialize default values for unused sosi fields
+
+ SIGNAL in_aux_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL out_aux_sosi : t_dp_sosi := c_dp_sosi_rst;
+
+BEGIN
+
+ -- Output monitor FIFO filling
+ wr_ful <= fifo_wr_ful;
+ wr_usedw <= fifo_wr_usedw;
+ rd_usedw <= fifo_rd_usedw;
+ rd_emp <= fifo_rd_emp;
+
+ p_wr_clk: PROCESS(wr_clk, wr_rst)
+ BEGIN
+ IF wr_rst='1' THEN
+ snk_out_arr <= (OTHERS => c_dp_siso_rst);
+ ELSIF rising_edge(wr_clk) THEN
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ snk_out_arr(I) <= nxt_snk_out;
+ END LOOP;
+ END IF;
+ END PROCESS;
+
+ wr_sync(0) <= snk_in_arr(0).sync;
+ wr_ctrl <= snk_in_arr(0).sop & snk_in_arr(0).eop;
+ wr_aux <= in_aux;
+
+ -- Assign the snk_in_arr data field or concatenated complex fields to the FIFO wr_data depending on g_use_complex
+ gen_streams : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ wr_data_complex_arr(I) <= snk_in_arr(I).im(c_complex_w-1 DOWNTO 0) & snk_in_arr(I).re(c_complex_w-1 DOWNTO 0);
+ wr_data((I+1) * g_data_w -1 DOWNTO I * g_data_w) <= snk_in_arr(I).data(g_data_w-1 DOWNTO 0) WHEN g_use_complex = FALSE ELSE RESIZE_UVEC(wr_data_complex_arr(I), g_data_w);
+ END GENERATE;
+ -- fifo wr wires
+ fifo_wr_req <= snk_in_arr(0).valid;
+ fifo_wr_dat <= func_slv_concat(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
+ wr_data,
+ snk_in_arr(0).bsn( g_bsn_w-1 DOWNTO 0),
+ snk_in_arr(0).empty( g_empty_w-1 DOWNTO 0),
+ snk_in_arr(0).channel(g_channel_w-1 DOWNTO 0),
+ snk_in_arr(0).err( g_error_w-1 DOWNTO 0),
+ wr_sync,
+ wr_ctrl,
+ wr_aux);
+
+ -- pass on frame level flow control
+ nxt_snk_out.xon <= src_in_arr(0).xon;
+
+ -- up stream use fifo almost full to control snk_out.ready
+ nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
+
+ gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
+ u_common_fifo_sc : ENTITY common_lib.common_fifo_sc
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_lut => g_use_lut_sc,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ PORT MAP (
+ rst => rd_rst,
+ clk => rd_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rd_val => fifo_rd_val,
+ usedw => fifo_rd_usedw
+ );
+
+ fifo_wr_usedw <= fifo_rd_usedw;
+ END GENERATE;
+
+ gen_common_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
+ u_common_fifo_dc : ENTITY common_lib.common_fifo_dc
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ PORT MAP (
+ rst => arst,
+ wr_clk => wr_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ wrusedw => fifo_wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rdusedw => fifo_rd_usedw,
+ rd_val => fifo_rd_val
+ );
+
+ arst <= wr_rst OR rd_rst;
+ END GENERATE;
+
+ -- Extract the data from the wide FIFO output SLV. rd_data will be assigned to rd_sosi.data or rd_sosi.im & rd_sosi.re depending on g_use_complex.
+ rd_data <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
+ c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w,
+ fifo_rd_dat, 0);
+
+ -- fifo rd wires
+ -- SISO
+ fifo_rd_req <= rd_siso_arr(0).ready;
+ rd_sync <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 5);
+ rd_ctrl <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 6);
+
+ -- AUX
+ in_aux_sosi.data <= RESIZE_DP_DATA(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 7));
+ in_aux_sosi.valid <= fifo_rd_val;
+ out_aux <= out_aux_sosi.data(g_aux_w-1 DOWNTO 0);
+
+ -- SOSI
+ gen_rd_streams : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ rd_data_arr(I) <= rd_data( (I+1) * g_data_w -1 DOWNTO I * g_data_w);
+ rd_sosi_arr(I).data <= RESIZE_DP_SDATA(rd_data_arr(I)) WHEN g_data_signed=TRUE ELSE RESIZE_DP_DATA(rd_data_arr(I));
+ rd_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(rd_data_arr(I)( c_complex_w-1 DOWNTO 0));
+ rd_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(rd_data_arr(I)(2*c_complex_w-1 DOWNTO c_complex_w));
+ rd_sosi_arr(I).bsn <= RESIZE_DP_BSN(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 1));
+ rd_sosi_arr(I).empty <= RESIZE_DP_EMPTY(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 2));
+ rd_sosi_arr(I).channel <= RESIZE_DP_CHANNEL(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 3));
+ rd_sosi_arr(I).err <= RESIZE_DP_ERROR(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 4));
+ rd_sosi_arr(I).sync <= fifo_rd_val AND rd_sync(0);
+ rd_sosi_arr(I).valid <= fifo_rd_val;
+ rd_sosi_arr(I).sop <= fifo_rd_val AND rd_ctrl(1);
+ rd_sosi_arr(I).eop <= fifo_rd_val AND rd_ctrl(0);
+
+ u_ready_latency : ENTITY work.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => g_fifo_rl
+ )
+ PORT MAP (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso_arr(I),
+ snk_in => rd_sosi_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
+ END GENERATE;
+
+ -- Using extra dp_latency_adapter for aux signal
+ u_ready_latency_aux : ENTITY work.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => g_fifo_rl
+ )
+ PORT MAP (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_in => in_aux_sosi,
+ -- ST source
+ src_in => src_in_arr(0),
+ src_out => out_aux_sosi
+ );
+
+
+END str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e788c2b57913f8cef7638e3288e83aa7ef55da3c
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
@@ -0,0 +1,124 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: DP FIFO array for dual clock (= dc) domain wr and rd.
+-- Description: See dp_fifo_core_arr.vhd.
+
+LIBRARY IEEE,common_lib, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY dp_fifo_dc_arr IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ g_nof_streams : NATURAL := 1;
+ g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_bsn_w : NATURAL := 1;
+ g_empty_w : NATURAL := 1;
+ g_channel_w : NATURAL := 1;
+ g_error_w : NATURAL := 1;
+ g_aux_w : NATURAL := 1;
+ g_use_bsn : BOOLEAN := FALSE;
+ g_use_empty : BOOLEAN := FALSE;
+ g_use_channel : BOOLEAN := FALSE;
+ g_use_error : BOOLEAN := FALSE;
+ g_use_sync : BOOLEAN := FALSE;
+ g_use_aux : BOOLEAN := FALSE;
+ g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
+ g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_rl : NATURAL := 1
+ );
+ PORT (
+ wr_rst : IN STD_LOGIC;
+ wr_clk : IN STD_LOGIC;
+ rd_rst : IN STD_LOGIC;
+ rd_clk : IN STD_LOGIC;
+ -- Monitor FIFO filling
+ wr_ful : OUT STD_LOGIC;
+ wr_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_emp : OUT STD_LOGIC;
+ -- ST sink
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ in_aux : IN STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0);
+ -- ST source
+ src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_aux : OUT STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0)
+ );
+END dp_fifo_dc_arr;
+
+
+ARCHITECTURE str OF dp_fifo_dc_arr IS
+BEGIN
+
+ u_dp_fifo_core_arr : ENTITY work.dp_fifo_core_arr
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_use_dual_clock => TRUE,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_aux_w => g_aux_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_aux => g_use_aux,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => g_fifo_rl
+ )
+ PORT MAP (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ in_aux => in_aux,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr,
+ out_aux => out_aux
+ );
+
+END str;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..514ebe5def34235e3eab48d0502a83b7c860190d
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
@@ -0,0 +1,251 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Test dp_fifo_dc_arr.
+-- Description:
+-- Verifies output data and ctrl signals of DUT. This is configurable using generics.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE work.tb_dp_pkg.ALL;
+
+ENTITY tb_dp_fifo_dc_arr IS
+ GENERIC (
+ -- Try FIFO settings
+ g_dut_nof_streams : NATURAL := 3;
+ g_dut_wr_clk_freq : POSITIVE := 2; -- normalized write clock frequency
+ g_dut_rd_clk_freq : POSITIVE := 3; -- normalized read clock frequency
+ g_dut_use_bsn : BOOLEAN := TRUE;
+ g_dut_use_empty : BOOLEAN := TRUE;
+ g_dut_use_channel : BOOLEAN := TRUE;
+ g_dut_use_sync : BOOLEAN := TRUE;
+ g_dut_use_ctrl : BOOLEAN := TRUE;
+ g_dut_use_aux : BOOLEAN := TRUE;
+ g_dut_out_latency : NATURAL := 1 -- selectable for dp_fifo_dc_arr: default 1 or 0 for look ahead FIFO
+ );
+END tb_dp_fifo_dc_arr;
+
+
+ARCHITECTURE tb OF tb_dp_fifo_dc_arr IS
+
+ -- See tb_dp_pkg.vhd for explanation and run time, increase the run time by g_dut_rd_clk_freq/g_dut_wr_clk_freq if g_dut_rd_clk_freq>g_dut_wr_clk_freq
+
+ -- DUT
+ CONSTANT c_dut_fifo_size : NATURAL := 64;
+ CONSTANT c_dut_in_latency : NATURAL := 1; -- fixed for dp_fifo_dc_arr
+
+ -- Stimuli
+ CONSTANT c_tx_latency : NATURAL := c_dut_in_latency; -- TX ready latency of TB
+ CONSTANT c_tx_void : NATURAL := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ CONSTANT c_tx_offset_sop : NATURAL := 3;
+ CONSTANT c_tx_period_sop : NATURAL := 7; -- sop in data valid cycle 3, 10, 17, ...
+ CONSTANT c_tx_offset_eop : NATURAL := 5; -- eop in data valid cycle 5, 12, 19, ...
+ CONSTANT c_tx_period_eop : NATURAL := c_tx_period_sop;
+ CONSTANT c_tx_offset_sync : NATURAL := 3; -- sync in data valid cycle 3, 20, 37, ...
+ CONSTANT c_tx_period_sync : NATURAL := 17;
+ CONSTANT c_rx_latency : NATURAL := g_dut_out_latency; -- RX ready latency from DUT
+ CONSTANT c_verify_en_wait : NATURAL := 20; -- wait some cycles before asserting verify enable
+
+ CONSTANT c_bsn_offset : NATURAL := 1;
+ CONSTANT c_empty_offset : NATURAL := 2;
+ CONSTANT c_channel_offset : NATURAL := 3;
+
+ CONSTANT c_random_w : NATURAL := 19;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL wr_clk : STD_LOGIC := '0';
+ SIGNAL rd_clk : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC;
+ SIGNAL sync : STD_LOGIC;
+ SIGNAL lfsr1 : STD_LOGIC_VECTOR(c_random_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL lfsr2 : STD_LOGIC_VECTOR(c_random_w DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL cnt_dat : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
+ SIGNAL cnt_val : STD_LOGIC;
+ SIGNAL cnt_en : STD_LOGIC;
+
+ SIGNAL tx_data : t_dp_data_arr(0 TO c_tx_latency + c_tx_void) := (OTHERS=>(OTHERS=>'0'));
+ SIGNAL tx_val : STD_LOGIC_VECTOR(0 TO c_tx_latency + c_tx_void) := (OTHERS=>'0');
+
+ SIGNAL in_ready : STD_LOGIC;
+ SIGNAL in_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_bsn : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_empty : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_channel : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_sync : STD_LOGIC;
+ SIGNAL in_val : STD_LOGIC;
+ SIGNAL in_sop : STD_LOGIC;
+ SIGNAL in_eop : STD_LOGIC;
+ SIGNAL in_aux : STD_LOGIC;
+
+ SIGNAL in_siso_arr : t_dp_siso_arr(g_dut_nof_streams-1 DOWNTO 0);
+ SIGNAL in_sosi_arr : t_dp_sosi_arr(g_dut_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL out_siso_arr : t_dp_siso_arr(g_dut_nof_streams-1 DOWNTO 0);
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(g_dut_nof_streams-1 DOWNTO 0);
+
+ SIGNAL out_ready : STD_LOGIC;
+ SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO c_rx_latency);
+ SIGNAL out_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
+ SIGNAL out_bsn : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_empty : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_channel : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_sync : STD_LOGIC;
+ SIGNAL out_val : STD_LOGIC;
+ SIGNAL out_sop : STD_LOGIC;
+ SIGNAL out_eop : STD_LOGIC;
+ SIGNAL out_aux : STD_LOGIC;
+ SIGNAL prev_out_data : STD_LOGIC_VECTOR(out_data'RANGE);
+
+ SIGNAL state : t_dp_state_enum;
+
+ SIGNAL verify_en : STD_LOGIC;
+ SIGNAL verify_done : STD_LOGIC;
+
+ SIGNAL exp_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := TO_UVEC(19000/g_dut_wr_clk_freq, c_dp_data_w);
+
+ SIGNAL usedw : STD_LOGIC_VECTOR(ceil_log2(c_dut_fifo_size)-1 DOWNTO 0);
+
+BEGIN
+
+ wr_clk <= NOT wr_clk OR tb_end AFTER g_dut_rd_clk_freq*clk_period/2;
+ rd_clk <= NOT rd_clk OR tb_end AFTER g_dut_wr_clk_freq*clk_period/2;
+ rst <= '1', '0' AFTER clk_period*7;
+
+ -- Sync interval
+ proc_dp_sync_interval(wr_clk, sync);
+
+ -- Input data
+ cnt_val <= in_ready AND cnt_en;
+
+ proc_dp_cnt_dat(rst, wr_clk, cnt_val, cnt_dat);
+ proc_dp_tx_data(c_tx_latency, rst, wr_clk, cnt_val, cnt_dat, tx_data, tx_val, in_data, in_val);
+ proc_dp_tx_ctrl(c_tx_offset_sync, c_tx_period_sync, in_data, in_val, in_sync);
+ proc_dp_tx_ctrl(c_tx_offset_sop, c_tx_period_sop, in_data, in_val, in_sop);
+ proc_dp_tx_ctrl(c_tx_offset_eop, c_tx_period_eop, in_data, in_val, in_eop);
+
+ in_bsn <= INCR_UVEC(in_data, c_bsn_offset);
+ in_empty <= INCR_UVEC(in_data, c_empty_offset);
+ in_channel <= INCR_UVEC(in_data, c_channel_offset);
+
+ -- Stimuli control
+ proc_dp_count_en(rst, wr_clk, sync, lfsr1, state, verify_done, tb_end, cnt_en);
+ proc_dp_out_ready(rst, wr_clk, sync, lfsr2, out_ready);
+
+ -- Output verify
+ proc_dp_verify_en(c_verify_en_wait, rst, rd_clk, sync, verify_en);
+ proc_dp_verify_data("out_sosi.data", c_rx_latency, rd_clk, verify_en, out_ready, out_val, out_data, prev_out_data);
+ proc_dp_verify_valid(c_rx_latency, rd_clk, verify_en, out_ready, prev_out_ready, out_val);
+
+ gen_verify_sync : IF g_dut_use_sync=TRUE GENERATE
+ proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "sync", rd_clk, verify_en, out_data, out_val, out_sync);
+ END GENERATE;
+
+ gen_verify_aux : IF g_dut_use_aux=TRUE GENERATE
+ proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "aux", rd_clk, verify_en, out_data, out_val, out_aux);
+ END GENERATE;
+
+ gen_verify_ctrl : IF g_dut_use_ctrl=TRUE GENERATE
+ proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", rd_clk, verify_en, out_data, out_val, out_sop);
+ proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", rd_clk, verify_en, out_data, out_val, out_eop);
+ END GENERATE;
+
+ gen_verify_bsn : IF g_dut_use_bsn=TRUE GENERATE
+ proc_dp_verify_other_sosi("bsn", INCR_UVEC(out_data, c_bsn_offset), rd_clk, verify_en, out_bsn);
+ END GENERATE;
+
+ gen_verify_empty : IF g_dut_use_empty=TRUE GENERATE
+ proc_dp_verify_other_sosi("empty", INCR_UVEC(out_data, c_empty_offset), rd_clk, verify_en, out_empty);
+ END GENERATE;
+
+ gen_verify_channel : IF g_dut_use_channel=TRUE GENERATE
+ proc_dp_verify_other_sosi("channel", INCR_UVEC(out_data, c_channel_offset), rd_clk, verify_en, out_channel);
+ END GENERATE;
+
+ -- Check that the test has ran at all
+ proc_dp_verify_value(e_at_least, rd_clk, verify_done, exp_data, out_data);
+
+ ------------------------------------------------------------------------------
+ -- DUT dp_fifo_dc_arr
+ ------------------------------------------------------------------------------
+
+ -- map sl, slv to record
+ in_ready <= in_siso_arr(0).ready; -- SISO
+ in_aux <= in_sync; -- use sync to test aux data
+ gen_streams : FOR I IN 0 TO g_dut_nof_streams -1 GENERATE
+ in_sosi_arr(I).data(c_dp_data_w-1 DOWNTO 0) <= in_data; -- SOSI
+ in_sosi_arr(I).bsn(c_dp_bsn_w-1 DOWNTO 0) <= in_bsn(c_dp_bsn_w-1 DOWNTO 0);
+ in_sosi_arr(I).empty <= in_empty(c_dp_empty_w-1 DOWNTO 0);
+ in_sosi_arr(I).channel <= in_channel(c_dp_channel_w-1 DOWNTO 0);
+ in_sosi_arr(I).sync <= in_sync;
+ in_sosi_arr(I).valid <= in_val;
+ in_sosi_arr(I).sop <= in_sop;
+ in_sosi_arr(I).eop <= in_eop;
+ out_siso_arr(I).ready <= out_ready; -- SISO
+ END GENERATE;
+ out_data <= out_sosi_arr(0).data(c_dp_data_w-1 DOWNTO 0); -- SOSI
+ out_bsn(c_dp_bsn_w-1 DOWNTO 0) <= out_sosi_arr(0).bsn(c_dp_bsn_w-1 DOWNTO 0);
+ out_empty(c_dp_empty_w-1 DOWNTO 0) <= out_sosi_arr(0).empty;
+ out_channel(c_dp_channel_w-1 DOWNTO 0) <= out_sosi_arr(0).channel;
+ out_sync <= out_sosi_arr(0).sync;
+ out_val <= out_sosi_arr(0).valid;
+ out_sop <= out_sosi_arr(0).sop;
+ out_eop <= out_sosi_arr(0).eop;
+
+ dut : ENTITY work.dp_fifo_dc_arr
+ GENERIC MAP (
+ g_nof_streams => g_dut_nof_streams,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_aux_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => FALSE,
+ g_use_sync => g_dut_use_sync,
+ g_use_aux => g_dut_use_aux,
+ g_use_ctrl => g_dut_use_ctrl,
+ g_fifo_size => c_dut_fifo_size,
+ g_fifo_rl => g_dut_out_latency
+ )
+ PORT MAP (
+ wr_rst => rst,
+ wr_clk => wr_clk,
+ rd_rst => rst,
+ rd_clk => rd_clk,
+ snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi_arr,
+ in_aux(0) => in_aux,
+ wr_usedw => usedw,
+ rd_usedw => OPEN,
+ src_in_arr => out_siso_arr, -- IN = request from downstream ST sink
+ src_out_arr => out_sosi_arr,
+ out_aux(0) => out_aux
+ );
+
+END tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a5a8429a8e0cefa5eae73755b8df3b083df2b55b
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
@@ -0,0 +1,67 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Test multiple instances of tb_dp_fifo_dc_arr.
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_tb_dp_fifo_dc_arr IS
+END tb_tb_dp_fifo_dc_arr;
+
+
+ARCHITECTURE tb OF tb_tb_dp_fifo_dc_arr IS
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+
+ -- > as 10
+ -- > run g_dut_rd_clk_freq * 330 us --> OK
+
+ -- Try FIFO settings : GENERIC MAP (g_dut_wr_clk_freq, g_dut_rd_clk_freq, g_dut_use_bsn, g_dut_use_empty, g_dut_use_channel, g_dut_use_sync, g_dut_use_ctrl, g_dut_out_latency)
+
+ u_use_all_rl_0 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_2_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 2, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_1_2 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 2, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_3_2 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 3, 2, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_2_3 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 2, 3, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+
+ u_use_all : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (1, 1, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_use_all_clk_3_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 3, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_use_all_clk_1_3 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 3, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+
+ u_use_ctrl_rl_0 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (1, 1, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 0);
+ u_use_ctrl_rl_0_clk_1_3 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 3, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 0);
+ u_use_ctrl_rl_0_clk_3_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 3, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 0);
+ u_use_ctrl : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 1);
+ u_use_ctrl_clk_1_2 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 2, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 1);
+ u_use_ctrl_clk_2_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 2, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 1);
+
+ u_no_bsn : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_no_empty : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, FALSE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_no_channel : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, FALSE, TRUE, TRUE, TRUE, 1);
+ u_no_sync : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, FALSE, TRUE, TRUE, 1);
+ u_no_ctrl : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, TRUE, FALSE, TRUE, 1);
+ u_no_aux : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, 1);
+
+END tb;