From 7f986b37891cb805232d9eca70c2eb960f47cfa6 Mon Sep 17 00:00:00 2001
From: Jan Oudman <oudman@astron.nl>
Date: Tue, 8 Sep 2020 10:51:39 +0200
Subject: [PATCH] fixed timing ram_pointer & p_ram_to_fifo, added out-port
dbg_ram_miso
---
libraries/dsp/st/src/vhdl/st_histogram.vhd | 241 +++++++++----------
libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd | 35 ++-
2 files changed, 145 insertions(+), 131 deletions(-)
diff --git a/libraries/dsp/st/src/vhdl/st_histogram.vhd b/libraries/dsp/st/src/vhdl/st_histogram.vhd
index 01ae2e640d..13b57e0ee1 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram.vhd
@@ -46,6 +46,14 @@
-- RAM is swapped after every sync both RAM blocks need to use the dp_clk.
-- If the MM bus needs to acces the data in a RAM block it has to acces it
-- through st_histogram_reg as the mm_clk can't be used.
+--
+-- The design is basically devided in the following blocks of code:
+-- . Assign inputs of RAM
+-- . Bin reader
+-- . Bin Writer
+-- . Bin Arbiter
+-- . RAM selector & Dual swapped RAM instances
+-- . Connect interface to DUAL swapped RAM, read out histogram statistics
--
-- Remarks:
-- . Because the values of the generics g_nof_bins depends on g_in_data_w
@@ -65,9 +73,11 @@
-- further consecutive samples and have the read/write limitation)
-- . If adresses are toggling at every cycle (e.g. adress 0; 1; 0; 1) you
-- have to remember the data to be written and increment it as you have the
--- read/write limitation and writing takes priority in this case
--- . When a sync signal appears the RAM has to be swapped 3 cycles later so
--- the first 3 cycles may not be read from the old RAM block
+-- read/write limitation (missing samples) and writing takes priority
+-- in this case
+-- . When a sync signal appears the RAM has to be swapped 4 cycles later so
+-- the first 3 cycles may/can not ask a read from the old RAM block (the
+-- read_enable takes one cycle hence the difference of 3 against 4 cycles)
--
-------------------------------------------------------------------------------
@@ -84,7 +94,7 @@ ENTITY st_histogram IS
g_nof_bins : NATURAL := 512; -- is a power of 2 and g_nof_bins <= c_data_span; max. 512
g_nof_data : NATURAL; --
g_str : STRING := "freq.density"; -- to select output to MM bus ("frequency" or "freq.density")
- g_ram_miso_dbg_mode : BOOLEAN := FALSE -- when TRUE the ram_miso bus will get a copy of the data written into the RAM.
+ g_ram_miso_sim_mode : BOOLEAN := FALSE -- when TRUE the ram_miso bus will get a copy of the data written into the RAM.
);
PORT (
dp_rst : IN STD_LOGIC;
@@ -95,15 +105,19 @@ ENTITY st_histogram IS
-- DP clocked memory bus
sla_in_ram_mosi : IN t_mem_mosi; -- Beware, works in dp clock domain !
- sla_out_ram_miso : OUT t_mem_miso -- '' !
+ sla_out_ram_miso : OUT t_mem_miso; -- '' !
-- ram_mosi : IN t_mem_mosi; -- Beware, works in dp clock domain !
-- ram_miso : OUT t_mem_miso -- '' !
+ -- Debug bus
+ dbg_ram_miso : OUT t_mem_miso
);
END st_histogram;
ARCHITECTURE rtl OF st_histogram IS
+-- CONSTANT c_data_span : NATURAL := pow2(g_in_data_w); -- any use?
+-- CONSTANT c_bin_w : NATURAL := ceil_log2(g_nof_data); -- any use?
CONSTANT c_clear : NATURAL := g_nof_data - g_nof_bins;
CONSTANT c_adr_w : NATURAL := ceil_log2(g_nof_bins);
CONSTANT c_adr_low_calc : INTEGER := g_in_data_w-c_adr_w; -- Calculation might yield a negative number
@@ -120,78 +134,53 @@ ARCHITECTURE rtl OF st_histogram IS
-- SIGNAL mem_miso_init : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL bin_reader_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL snk_in_p : t_dp_sosi;
+ SIGNAL snk_in_pp : t_dp_sosi;
+ SIGNAL snk_in_pppp : t_dp_sosi;
+
+ SIGNAL bin_reader_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL prev_bin_reader_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL bin_reader_mosi_pp : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL bin_reader_mosi_ppp : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL nxt_bin_writer_mosi : t_mem_mosi;
- SIGNAL bin_writer_mosi : t_mem_mosi;
+ SIGNAL nxt_bin_writer_mosi : t_mem_mosi;
+ SIGNAL bin_writer_mosi : t_mem_mosi;
- SIGNAL nxt_bin_arbiter_wr_mosi : t_mem_mosi;
- SIGNAL bin_arbiter_wr_mosi : t_mem_mosi;
+ SIGNAL nxt_bin_arbiter_wr_mosi : t_mem_mosi;
+ SIGNAL bin_arbiter_wr_mosi : t_mem_mosi;
- SIGNAL nxt_bin_arbiter_rd_mosi : t_mem_mosi;
- SIGNAL bin_arbiter_rd_mosi : t_mem_mosi;
+ SIGNAL nxt_bin_arbiter_rd_mosi : t_mem_mosi;
+ SIGNAL bin_arbiter_rd_mosi : t_mem_mosi;
- SIGNAL bin_arbiter_rd_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL bin_reader_rd_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL common_ram_r_w_0_miso : t_mem_miso := c_mem_miso_rst;
-
- SIGNAL init_phase : STD_LOGIC := '1';
- SIGNAL nxt_init_phase : STD_LOGIC;
- SIGNAL rd_cnt_allowed : STD_LOGIC := '0';
- SIGNAL rd_cnt_allowed_pp : STD_LOGIC := '0';
- SIGNAL toggle_detect : STD_LOGIC := '0';
- SIGNAL toggle_detect_pp : STD_LOGIC;
- SIGNAL toggle_detect_false : STD_LOGIC := '1';
+ SIGNAL bin_arbiter_rd_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL bin_reader_rd_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL common_ram_r_w_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL init_phase : STD_LOGIC := '1';
+ SIGNAL nxt_init_phase : STD_LOGIC;
+
+ SIGNAL rd_cnt_allowed : STD_LOGIC := '0';
+ SIGNAL rd_cnt_allowed_pp : STD_LOGIC := '0';
+
+ SIGNAL toggle_detect : STD_LOGIC := '0';
+ SIGNAL toggle_detect_pp : STD_LOGIC;
+ SIGNAL toggle_detect_false : STD_LOGIC := '1';
SIGNAL nxt_toggle_detect_false : STD_LOGIC;
- SIGNAL nxt_prev_wrdata : NATURAL;
- SIGNAL prev_wrdata : NATURAL;
- SIGNAL prev_prev_wrdata : NATURAL;
- SIGNAL prev_prev_prev_wrdata: NATURAL;
- SIGNAL sync_detect : STD_LOGIC := '0';
- SIGNAL sync_detect_pp : STD_LOGIC;
- SIGNAL same_r_w_address : STD_LOGIC;
- SIGNAL same_r_w_address_pp : STD_LOGIC;
-
- --pipelined signals
- SIGNAL snk_in_p : t_dp_sosi;
- SIGNAL snk_in_pp : t_dp_sosi;
- SIGNAL snk_in_ppp : t_dp_sosi;
- SIGNAL prev_bin_reader_mosi : t_mem_mosi := c_mem_mosi_rst ;
- SIGNAL bin_reader_mosi_pp : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL bin_reader_mosi_ppp : t_mem_mosi := c_mem_mosi_rst;
+
+ SIGNAL nxt_prev_wrdata : NATURAL;
+ SIGNAL prev_wrdata : NATURAL;
+ SIGNAL prev_prev_wrdata : NATURAL;
+ SIGNAL prev_prev_prev_wrdata : NATURAL;
+
+ SIGNAL sync_detect : STD_LOGIC := '0';
+ SIGNAL sync_detect_pp : STD_LOGIC;
+
+ SIGNAL same_r_w_address : STD_LOGIC;
+ SIGNAL same_r_w_address_pp : STD_LOGIC;
--debug signals
--- SIGNAL nxt_dbg_sync_detect : STD_LOGIC;
--- SIGNAL dbg_sync_detect : STD_LOGIC;
- SIGNAL dbg_state_string : STRING(1 TO 3) := " ";
- SIGNAL dbg_snk_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
-
------
-
--- CONSTANT c_data_span : NATURAL := pow2(g_in_data_w); -- any use?
--- CONSTANT c_bin_w : NATURAL := ceil_log2(g_nof_data); -- any use?
--- CONSTANT c_clear : NATURAL := g_nof_data - g_nof_bins;
--- CONSTANT c_adr_w : NATURAL := ceil_log2(g_nof_bins);
--- CONSTANT c_adr_low_calc : INTEGER := g_in_data_w-c_adr_w; -- Calculation might yield a negative number
--- CONSTANT c_adr_low : NATURAL := largest(0, c_adr_low_calc); -- Override any negative value of c_adr_low_calc
---
--- CONSTANT c_ram : t_c_mem := (latency => 1,
--- adr_w => c_adr_w, -- 9 bits needed to adress/select 512 adresses
--- dat_w => c_word_w, -- 32bit, def. in common_pkg; >= c_bin_w
--- nof_dat => g_nof_bins, -- 512 adresses with 32 bit words, so 512
--- init_sl => '0'); -- MM side : sla_in, sla_out
-
--- SIGNAL dp_pipeline_src_out_p : t_dp_sosi;
--- SIGNAL dp_pipeline_src_out_pp : t_dp_sosi;
---
--- SIGNAL rd_adr_cnt : NATURAL := 1;
--- SIGNAL nxt_rd_adr_cnt : NATURAL;
--- SIGNAL prev_rd_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
---
--- -- Toggle implementation signals
--- SIGNAL prev_same_r_w_adr : STD_LOGIC := '0';
--- SIGNAL same_r_w_adr : STD_LOGIC := '0';
--- SIGNAL nxt_same_r_w_adr : STD_LOGIC := '0';
+ SIGNAL dbg_state_string : STRING(1 TO 3) := " ";
+ SIGNAL dbg_snk_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
SIGNAL ram_pointer : STD_LOGIC := '0';
@@ -212,31 +201,29 @@ ARCHITECTURE rtl OF st_histogram IS
SIGNAL mm_adr_illegal_pp : STD_LOGIC := '0';
- SIGNAL ram_0_wr_en : STD_LOGIC;
--- SIGNAL ram_0_wr_en_b : STD_LOGIC := '0'; -- pointer=1, temp'0'
- SIGNAL ram_0_wr_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
--- SIGNAL ram_0_wr_dat_b : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0) := (OTHERS =>'0'); -- pointer=1, temp'0'
+ SIGNAL ram_0_wr_en : STD_LOGIC;
+ SIGNAL ram_0_wr_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
SIGNAL ram_0_wr_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
SIGNAL ram_0_rd_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
- SIGNAL ram_0_rd_en : STD_LOGIC;
- SIGNAL ram_0_rd_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
- SIGNAL ram_0_rd_val : STD_LOGIC;
-
- SIGNAL ram_1_wr_en : STD_LOGIC;
- SIGNAL ram_1_wr_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+ SIGNAL ram_0_rd_en : STD_LOGIC;
+ SIGNAL ram_0_rd_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+ SIGNAL ram_0_rd_val : STD_LOGIC;
+
+ SIGNAL ram_1_wr_en : STD_LOGIC;
+ SIGNAL ram_1_wr_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
SIGNAL ram_1_wr_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
SIGNAL ram_1_rd_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
- SIGNAL ram_1_rd_en : STD_LOGIC;
- SIGNAL ram_1_rd_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
- SIGNAL ram_1_rd_val : STD_LOGIC;
-
- SIGNAL ram_out_wr_en : STD_LOGIC;
- SIGNAL ram_out_wr_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
- SIGNAL ram_out_wr_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
- SIGNAL ram_out_rd_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
- SIGNAL ram_out_rd_en : STD_LOGIC;
- SIGNAL ram_out_rd_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
- SIGNAL ram_out_rd_val : STD_LOGIC;
+ SIGNAL ram_1_rd_en : STD_LOGIC;
+ SIGNAL ram_1_rd_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+ SIGNAL ram_1_rd_val : STD_LOGIC;
+
+ SIGNAL ram_out_wr_en : STD_LOGIC;
+ SIGNAL ram_out_wr_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+ SIGNAL ram_out_wr_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
+ SIGNAL ram_out_rd_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
+ SIGNAL ram_out_rd_en : STD_LOGIC;
+ SIGNAL ram_out_rd_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
+ SIGNAL ram_out_rd_val : STD_LOGIC;
SIGNAL prev_ram_out_wr_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
SIGNAL ram_out_same_w_r_adr : STD_LOGIC;
@@ -249,15 +236,15 @@ BEGIN
ASSERT c_adr_low_calc>0 REPORT "ceil_log2(g_nof_bins) is as large as g_in_data_w, don't increase g_nof_bins" SEVERITY WARNING;
-----------------------------------------------------------------------------
- -- Assign inputs of RAM:
+ -- Assign inputs of RAM: <-- use parts of description for bin_writer
-- . Determine address based on input data
-- . Compare adress with the two previous adresses and if:
-- . it is the same as the last adress increase a counter
- -- . it is the same as 2 cycles back but not the last copy the data to be
- -- written directly into the counter instead of trying to read (ask) it
- -- back from RAM at the same clock cycle (which is impossible)
- -- . it is not the same enable the nxt_wr_dat data to be written
- -- at the next cycle by making nxt_wr_en high
+ -- . it is the same as 2 cycles back but not the last copy the data to be
+ -- written directly into a local counter instead of trying to read (ask)
+ -- it back from RAM at the same clock cycle (which is impossible)
+ -- . it is not the same enable the nxt_wr_dat data to be written .
+ -- at the next cycle by making nxt_wr_en high .
-- . Write the wr_dat data to the RAM
-- . At the snk_in.sync pulse:
-- . let first 3 cycles start counting from 0 again
@@ -267,9 +254,14 @@ BEGIN
-- . pause when adress is the same as the previous adress
-- . restart from 0 when adress is not the same as previous adress
-- . restart from 0 when also a sync appears
+ --
+ --
+ -- . in : snk_in (latency: 0)
+ -- : common_ram_r_w_miso (latency: 2)
+ -- . out : snk_in_pppp.sync (latency: 4)
+ -- : bin_arbiter_wr_mosi (latency: 4)
+ -- : bin_arbiter_rd_mosi (latency: 1)
--
- -- input: snk_in; rd_dat; rd_val
- -- output: wr_adr; rd_adr; wr_en; rd_en; wr_dat;
----------------------------------------------------------------------------
-----------------------------------------------------------------------------
@@ -333,15 +325,15 @@ BEGIN
);
-- Enable switching the ram_pointer
- u_dp_pipeline_snk_in_3_cycle : ENTITY dp_lib.dp_pipeline
+ u_dp_pipeline_snk_in_4_cycle : ENTITY dp_lib.dp_pipeline
GENERIC MAP (
- g_pipeline => 3 -- 0 for wires, > 0 for registers,
+ g_pipeline => 4 -- 0 for wires, > 0 for registers,
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_in => snk_in,
- src_out => snk_in_ppp
+ src_out => snk_in_pppp
);
dbg_snk_data <= snk_in_pp.data(g_in_data_w-1 DOWNTO 0);
@@ -458,21 +450,21 @@ BEGIN
-- . in : toggle_detect_pp (latency: 2)
-- . in : same_r_w_address_pp (latency: 2)
-- . in : bin_reader_mosi_pp (latency: 2)
- -- . in : bin_reader_rd_miso (latency: 2) aka bin_arbiter_rd_miso or common_ram_r_w_0_miso
+ -- . in : bin_reader_rd_miso (latency: 2) aka bin_arbiter_rd_miso or common_ram_r_w_miso
-- . in : rd_cnt_allowed_pp (latency: 2)
-- . in : sync_detect_pp
-- . out : bin_writer_mosi (latency: 3)
-----------------------------------------------------------------------------
p_nxt_bin_writer_mosi : PROCESS(bin_reader_rd_miso,
- bin_reader_mosi_pp.address, toggle_detect_pp, rd_cnt_allowed_pp, init_phase, prev_wrdata, prev_prev_wrdata, prev_prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp) IS -- init_phase unnecesary? ; removed: common_ram_r_w_0_miso.rdval, common_ram_r_w_0_miso.rddata,
+ bin_reader_mosi_pp.address, toggle_detect_pp, rd_cnt_allowed_pp, prev_wrdata, prev_prev_wrdata, prev_prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp) IS
BEGIN
nxt_bin_writer_mosi <= c_mem_mosi_rst;
dbg_state_string <= "unv";
- IF bin_reader_rd_miso.rdval='1' THEN -- common_ram_r_w_0_miso
+ IF bin_reader_rd_miso.rdval='1' THEN
nxt_bin_writer_mosi.wr <= '1';
- nxt_bin_writer_mosi.wrdata <= INCR_UVEC(bin_reader_rd_miso.rddata, 1); -- common_ram_r_w_0_miso
+ nxt_bin_writer_mosi.wrdata <= INCR_UVEC(bin_reader_rd_miso.rddata, 1);
nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
- nxt_prev_wrdata <= TO_UINT(bin_reader_rd_miso.rddata) + 1; -- common_ram_r_w_0_miso
+ nxt_prev_wrdata <= TO_UINT(bin_reader_rd_miso.rddata) + 1;
dbg_state_string <= "val";
ELSIF toggle_detect_pp = '1' THEN
@@ -529,7 +521,7 @@ BEGIN
bin_writer_mosi <= nxt_bin_writer_mosi;
-- IF nxt_bin_writer_mosi.wr = '1' THEN
-- prev_wrdata <= nxt_prev_wrdata;
--- prev_prev_wrdata<= prev_wrdata; -- wrong when unvalid before toggle_detect_pp; may not shift wrdata when unvalid
+-- prev_prev_wrdata<= prev_wrdata;
-- prev_prev_prev_wrdata <= prev_prev_wrdata;
-- END IF;
END IF;
@@ -545,7 +537,7 @@ BEGIN
-- : bin_reader_mosi_ppp (latency: 3)
-- : bin_writer_mosi (latency: 3)
-- : sync_detect (latency: 0? or 3?
- -- : common_ram_r_w_0_miso (latency: 2)
+ -- : common_ram_r_w_miso (latency: 2)
-- . out : bin_arbiter_rd_mosi (latency: 1)
-- . : bin_arbiter_rd_miso (latency: 2)
-- . : bin_arbiter_wr_mosi (latency: 4)
@@ -572,12 +564,12 @@ BEGIN
-- sla_out_ram_miso.rddata <= bin_arbiter_wr_mosi.wrdata;
-- Make RAM data available for the bin_reader (or bin_writer)
- bin_arbiter_rd_miso <= common_ram_r_w_0_miso;
+ bin_arbiter_rd_miso <= common_ram_r_w_miso;
-----------------------------------------------------------------------------
-- RAM selector & Dual swapped RAM instances:
- -- 3 cycles after a sync the RAM block is swapped for an empty one to allow
+ -- 4 cycles after a sync the RAM block is swapped for an empty one to allow
-- the block to be read out till the next sync+3 cycles
-- The input is the st side, the output is the dp clocked mm side.
--
@@ -585,18 +577,18 @@ BEGIN
-- ram_pointer = '0': input RAM_0, output RAM_1
-- ram_pointer = '1': input RAM_1, output RAM_0
--
- -- input in: snk_in_pp.sync (latency: 2)
+ -- input in: snk_in_pppp.sync (latency: 4)
-- bin_arbiter_wr_mosi (latency: 4)
-- bin_arbiter_rd_mosi (latency: 1)
- -- out: common_ram_r_w_0_miso (latency: 2)
+ -- out: common_ram_r_w_miso (latency: 2)
--
-- output in: ram_out_wr_en; ram_out_wr_dat; ram_out_wr_adr; ram_out_rd_adr;
-- ram_out_rd_en
-- out: ram_out_rd_dat; ram_out_rd_val
-----------------------------------------------------------------------------
- p_ram_pointer_at_sync : PROCESS(snk_in_ppp) IS -- needs nxt_ram_pointer ?? -- snk_in_ppp
+ p_ram_pointer_at_sync : PROCESS(snk_in_pppp) IS -- needs nxt_ram_pointer ??
BEGIN
- IF snk_in_ppp.sync = '1' THEN --restructured takes xtra cycles, dp_pipeline_src_out_pp becomes snk_in_ppp
+ IF snk_in_pppp.sync = '1' THEN --needs snk_in_pppp <--
ram_pointer <= NOT(ram_pointer);
END IF;
END PROCESS;
@@ -612,8 +604,8 @@ BEGIN
ram_0_wr_adr <= bin_arbiter_wr_mosi.address(c_adr_w-1 DOWNTO 0); -- bin_arbiter_wr_mosi.address wr_adr
ram_0_rd_adr <= bin_arbiter_rd_mosi.address(c_adr_w-1 DOWNTO 0); -- bin_arbiter_rd_mosi.address rd_adr
ram_0_rd_en <= bin_arbiter_rd_mosi.rd; -- bin_arbiter_rd_mosi.rd rd_en
- common_ram_r_w_0_miso.rddata(c_word_w-1 DOWNTO 0) <= ram_0_rd_dat; -- common_ram_r_w_0_miso.rddata rd_dat
- common_ram_r_w_0_miso.rdval <= ram_0_rd_val; -- common_ram_r_w_0_miso.rdval rd_val
+ common_ram_r_w_miso.rddata(c_word_w-1 DOWNTO 0) <= ram_0_rd_dat; -- common_ram_r_w_miso.rddata rd_dat
+ common_ram_r_w_miso.rdval <= ram_0_rd_val; -- common_ram_r_w_miso.rdval rd_val
-- dp_clk'd MM side (RAM 1)
@@ -634,8 +626,8 @@ BEGIN
ram_1_wr_adr <= bin_arbiter_wr_mosi.address(c_adr_w-1 DOWNTO 0);
ram_1_rd_adr <= bin_arbiter_rd_mosi.address(c_adr_w-1 DOWNTO 0);
ram_1_rd_en <= bin_arbiter_rd_mosi.rd;
- common_ram_r_w_0_miso.rddata(c_word_w-1 DOWNTO 0) <= ram_1_rd_dat;
- common_ram_r_w_0_miso.rdval <= ram_1_rd_val;
+ common_ram_r_w_miso.rddata(c_word_w-1 DOWNTO 0) <= ram_1_rd_dat;
+ common_ram_r_w_miso.rdval <= ram_1_rd_val;
--dp_clk'd MM side (RAM 0)
ram_0_wr_en <= ram_out_wr_en;
@@ -730,10 +722,10 @@ BEGIN
mm_adr_cnt <= TO_UINT(sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0)) WHEN sla_in_ram_mosi.rd = '1';
ram_out_same_w_r_adr <= '1' WHEN ram_out_wr_adr = sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0) ELSE '0';
- p_ram_to_fifo : PROCESS(snk_in_pp.sync, cycle_cnt, sla_in_ram_mosi.address, sla_in_ram_mosi.rd, ram_out_rd_dat, ram_out_rd_val, prev_ram_out_wr_adr, mm_adr_illegal, ram_out_same_w_r_adr, bin_arbiter_wr_mosi.wrdata) IS
+ p_ram_to_fifo : PROCESS(snk_in_pp.sync, cycle_cnt, sla_in_ram_mosi.address, sla_in_ram_mosi.rd, ram_out_rd_dat, ram_out_rd_val, prev_ram_out_wr_adr, mm_adr_illegal_pp, ram_out_same_w_r_adr, bin_arbiter_wr_mosi.wrdata) IS
BEGIN
- IF g_ram_miso_dbg_mode = FALSE THEN
- IF snk_in_pp.sync = '1' THEN
+ IF g_ram_miso_sim_mode = FALSE THEN
+ IF snk_in_pppp.sync = '1' THEN
ram_out_wr_en <= '0';
nxt_cycle_cnt <= 0;
ELSIF cycle_cnt = c_clear THEN
@@ -753,6 +745,7 @@ BEGIN
nxt_cycle_cnt <= cycle_cnt +1;
ELSIF cycle_cnt > c_clear THEN
ram_out_wr_adr <= INCR_UVEC(prev_ram_out_wr_adr, 1);
+ ram_out_wr_dat <= (OTHERS => '0');
nxt_cycle_cnt <= cycle_cnt +1;
IF ram_out_same_w_r_adr = '1' OR snk_in.sync = '1' THEN
sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= (OTHERS => '0');
@@ -763,19 +756,23 @@ BEGIN
sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= ram_out_rd_dat;
sla_out_ram_miso.rdval <= ram_out_rd_val;
END IF;
+ ram_out_wr_en <= '1';
ELSIF mm_adr_illegal_pp = '1' THEN
ram_out_rd_adr <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
ram_out_rd_en <= sla_in_ram_mosi.rd;
sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= (OTHERS => '0');
sla_out_ram_miso.rdval <= ram_out_rd_val;
nxt_cycle_cnt <= cycle_cnt +1;
+ ram_out_wr_en <= '0';
ELSE
ram_out_rd_adr <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
ram_out_rd_en <= sla_in_ram_mosi.rd;
sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= ram_out_rd_dat;
sla_out_ram_miso.rdval <= ram_out_rd_val;
nxt_cycle_cnt <= cycle_cnt +1;
+ ram_out_wr_en <= '0';
END IF;
+ dbg_ram_miso.rddata <= bin_arbiter_wr_mosi.wrdata;
ELSE
sla_out_ram_miso.rddata <= bin_arbiter_wr_mosi.wrdata;
END IF;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
index 42e3e4a5ea..faad666ee4 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
@@ -138,7 +138,8 @@ ARCHITECTURE tb OF tb_st_histogram IS
-- Streaming Output
----------------------------------------------------------------------------
- SIGNAL st_histogram_ram_miso : t_mem_miso;
+ SIGNAL st_histogram_ram_miso : t_mem_miso;
+ SIGNAL st_histogram_dbg_ram_miso : t_mem_miso;
----------------------------------------------------------------------------
@@ -365,6 +366,21 @@ BEGIN
+-- p_mm_stimuli : PROCESS --(st_histogram_snk_in.sync)
+-- BEGIN
+-- st_histogram_ram_mosi <= c_mem_mosi_rst; --.address(c_adr_w-1 DOWNTO 0) <= (OTHERS=>'0');
+-- WAIT UNTIL st_histogram_snk_in.sync = '1';
+-- -- wait till one RAM block is written
+-- FOR I IN 0 TO (g_sync_length) LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+-- -- wait for some more cycles
+-- FOR I IN 0 TO 2 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+-- -- read all bins
+-- FOR I IN 0 TO g_nof_bins-1 LOOP
+-- proc_mem_mm_bus_rd(I, dp_clk, st_histogram_ram_mosi);
+-- proc_common_wait_some_cycles(dp_clk, 1);
+-- END LOOP;
+-- END PROCESS;
+
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
@@ -374,7 +390,7 @@ BEGIN
g_in_data_w => g_data_w,
g_nof_bins => g_nof_bins,
g_nof_data => g_nof_data,
- g_ram_miso_dbg_mode => TRUE
+ g_ram_miso_sim_mode => FALSE -- TRUE
)
PORT MAP (
dp_rst => dp_rst,
@@ -385,7 +401,8 @@ BEGIN
-- Memory Mapped
sla_in_ram_mosi => c_mem_mosi_rst,-- sla_in_
- sla_out_ram_miso => st_histogram_ram_miso --OPEN -- sla_out_
+ sla_out_ram_miso => st_histogram_ram_miso, --OPEN -- sla_out_
+ dbg_ram_miso => st_histogram_dbg_ram_miso
);
@@ -465,23 +482,23 @@ BEGIN
---------------------
-- extra dbg signals
- dbg_int_data_miso <= TO_UINT(st_histogram_ram_miso.rddata);
+ dbg_int_data_miso <= TO_UINT(st_histogram_dbg_ram_miso.rddata);
dbg_int_data_arr <= data_check_arr(prev_check_adr);
---------------------
-- selftest
--- p_selfcheck : PROCESS (dp_rst, dp_clk, data_check_arr, prev_check_adr, st_histogram_ram_miso.rddata)
+-- p_selfcheck : PROCESS (dp_rst, dp_clk, data_check_arr, prev_check_adr, st_histogram_dbg_ram_miso.rddata)
-- BEGIN
-- --PROCESS
-- -- compare cumulated testdata with ram_mosi
--
--- --dbg_int_data_miso <= TO_UINT(st_histogram_ram_miso.rddata);
+-- --dbg_int_data_miso <= TO_UINT(st_histogram_dbg_ram_miso.rddata);
-- --dbg_int_data_arr <= data_check_arr(check_adr);
-- IF rising_edge(dp_clk) THEN
-- --dbg_error_location <= '0';
--- --dbg_int_data_miso <= TO_UINT(st_histogram_ram_miso.rddata);
+-- --dbg_int_data_miso <= TO_UINT(st_histogram_dbg_ram_miso.rddata);
-- --dbg_int_data_arr <= data_check_arr(check_adr);
--- IF data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_ram_miso.rddata) AND st_histogram_snk_in_pppp.valid='1' THEN
+-- IF data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_dbg_ram_miso.rddata) AND st_histogram_snk_in_pppp.valid='1' THEN
-- dbg_error_location <= '1';
-- REPORT "The value written to the RAM is not what it should be. See signal 'dbg_int_data_arr'. The failure concerns the bin (and array) address: " &integer'image(prev_check_adr) SEVERITY ERROR;
-- error_cnt <= error_cnt + 1;
@@ -499,7 +516,7 @@ BEGIN
-- show the location of an error after a small delay (to prevent spikes) when the data written is not the same as the reference and only when the data was initially valid. Do not allow to be triggered at the testbench end.
- dbg_error_location <= '1' AFTER c_dp_clk_period/5 WHEN ( (data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_ram_miso.rddata) ) AND st_histogram_snk_in_pppp.valid='1' AND tb_end='0' ) ELSE '0';
+ dbg_error_location <= '1' AFTER c_dp_clk_period/5 WHEN ( (data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_dbg_ram_miso.rddata) ) AND st_histogram_snk_in_pppp.valid='1' AND tb_end='0' ) ELSE '0';
ASSERT dbg_error_location='0' REPORT "The value written to the RAM is not what it should be. Comparison failed on (bin and array) address: " &integer'image(prev_check_adr) SEVERITY ERROR;
--
GitLab