From 7f6fcdc1e6e08ceaa582fe358e08dfbdaedf9dd0 Mon Sep 17 00:00:00 2001
From: Zanting <zanting>
Date: Mon, 8 Jun 2015 12:43:48 +0000
Subject: [PATCH] Added verbosity check and repeat loops
---
.../unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py | 97 +++++++++----------
1 file changed, 48 insertions(+), 49 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py b/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py
index 01279e2739..9db3346255 100644
--- a/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py
+++ b/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py
@@ -75,61 +75,60 @@ ddr = pi_io_ddr.PiIoDdr(tc, io, nof_inst = 1)
# Wait for power up (reset release)
io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
-# Initialization
-tx_seq.write_disable()
-rx_seq.write_disable()
-
-# Read RX Sequencer result before run
-rx_seq.read_result()
-
-# Wait for the DDR memory to become available
-#ddr.read_io_ddr()
-do_until_eq(ddr.read_init_done, ms_retry=3000, val=1, s_timeout=3600)
-
-# Flush Tx FIFO
-ddr.write_flush_pulse()
-io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
-
-# Set DDR controller in write mode and start writing
+# Control defaults
+nof_mon = 2
start_address = 0
nof_words = 100
-ddr.set_address(data=start_address)
-ddr.set_burstsize(data=nof_words)
-ddr.set_write()
-ddr.burstbegin()
-
-# Tx sequence start
-tx_seq.write_enable_cntr()
-# Tx sequence monitor
for rep in range(tc.repeat):
- io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
- tx_seq.read_cnt()
-
-# Wait until controller write access is done
-do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)
+ tc.append_log(5, '')
+ tc.append_log(3, '>>> Rep-%d' % rep)
-# Rx sequence start
-rx_seq.write_enable_cntr()
-
-# Set DDR3 controller in read mode and start reading
-ddr.set_read()
-ddr.burstbegin()
-
-# Rx sequence monitor
-for rep in range(tc.repeat):
+ # Initialization
+ tx_seq.write_disable(vLevel=5)
+ rx_seq.write_disable(vLevel=5)
+
+ # Wait for the DDR memory to become available
+ do_until_eq(ddr.read_init_done, ms_retry=3000, val=1, s_timeout=3600)
+
+ # Flush Tx FIFO
+ ddr.write_flush_pulse(vLevel=5)
io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
- rx_seq.read_cnt()
-
-# Wait until controller read access is done
-do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)
-
-rx_seq.read_result()
-
-io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
-
-rx_seq.read_result()
-
+
+ # Set DDR controller in write mode and start writing
+ ddr.set_address(data=start_address, vLevel=5)
+ ddr.set_burstsize(data=nof_words, vLevel=5)
+ ddr.set_write(vLevel=5)
+ ddr.burstbegin(vLevel=5)
+
+ # Tx sequence start
+ tx_seq.write_enable_cntr(vLevel=5)
+
+ # Tx sequence monitor
+ for mon in range(nof_mon):
+ io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
+ tx_seq.read_cnt(vLevel=5)
+
+ # Wait until controller write access is done
+ do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)
+
+ # Rx sequence start
+ rx_seq.write_enable_cntr(vLevel=5)
+
+ # Set DDR3 controller in read mode and start reading
+ ddr.set_read(vLevel=5)
+ ddr.burstbegin(vLevel=5)
+
+ # Rx sequence monitor
+ for mon in range(nof_mon):
+ io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
+ rx_seq.read_cnt(vLevel=5)
+
+ # Wait until controller read access is done
+ do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)
+
+ rx_seq.read_result(vLevel=5)
+
# End
tc.set_section_id('')
--
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