diff --git a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
index e907b32e0517de019d06abf0c369f9dacdc6132a..f4cec63c6bf137390fbe6e2d70a06749a641936b 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
+++ b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
@@ -37,7 +37,7 @@
{
datum baseAddress
{
- value = "960";
+ value = "1984";
type = "String";
}
}
@@ -69,7 +69,7 @@
{
datum baseAddress
{
- value = "896";
+ value = "1920";
type = "String";
}
}
@@ -117,7 +117,7 @@
{
datum baseAddress
{
- value = "1480";
+ value = "12752";
type = "String";
}
}
@@ -162,7 +162,7 @@
{
datum baseAddress
{
- value = "1472";
+ value = "12744";
type = "String";
}
}
@@ -194,7 +194,7 @@
{
datum baseAddress
{
- value = "1376";
+ value = "12304";
type = "String";
}
}
@@ -210,7 +210,7 @@
{
datum _sortIndex
{
- value = "31";
+ value = "34";
type = "int";
}
}
@@ -226,7 +226,7 @@
{
datum _sortIndex
{
- value = "30";
+ value = "33";
type = "int";
}
}
@@ -242,7 +242,7 @@
{
datum _sortIndex
{
- value = "27";
+ value = "30";
type = "int";
}
}
@@ -258,7 +258,7 @@
{
datum _sortIndex
{
- value = "26";
+ value = "29";
type = "int";
}
}
@@ -274,7 +274,7 @@
{
datum _sortIndex
{
- value = "44";
+ value = "47";
type = "int";
}
}
@@ -290,7 +290,7 @@
{
datum _sortIndex
{
- value = "45";
+ value = "48";
type = "int";
}
}
@@ -306,7 +306,7 @@
{
datum _sortIndex
{
- value = "23";
+ value = "26";
type = "int";
}
}
@@ -322,7 +322,7 @@
{
datum _sortIndex
{
- value = "22";
+ value = "25";
type = "int";
}
}
@@ -330,7 +330,7 @@
{
datum baseAddress
{
- value = "768";
+ value = "1792";
type = "String";
}
}
@@ -338,7 +338,7 @@
{
datum _sortIndex
{
- value = "29";
+ value = "32";
type = "int";
}
}
@@ -346,7 +346,7 @@
{
datum baseAddress
{
- value = "1216";
+ value = "12512";
type = "String";
}
}
@@ -354,7 +354,7 @@
{
datum _sortIndex
{
- value = "28";
+ value = "31";
type = "int";
}
}
@@ -362,7 +362,7 @@
{
datum baseAddress
{
- value = "1248";
+ value = "12544";
type = "String";
}
}
@@ -370,7 +370,7 @@
{
datum _sortIndex
{
- value = "25";
+ value = "28";
type = "int";
}
}
@@ -378,7 +378,7 @@
{
datum baseAddress
{
- value = "384";
+ value = "1408";
type = "String";
}
}
@@ -386,7 +386,7 @@
{
datum _sortIndex
{
- value = "24";
+ value = "27";
type = "int";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "640";
+ value = "1664";
type = "String";
}
}
@@ -402,7 +402,7 @@
{
datum _sortIndex
{
- value = "42";
+ value = "45";
type = "int";
}
}
@@ -410,7 +410,7 @@
{
datum baseAddress
{
- value = "512";
+ value = "1536";
type = "String";
}
}
@@ -418,7 +418,7 @@
{
datum _sortIndex
{
- value = "43";
+ value = "46";
type = "int";
}
}
@@ -434,7 +434,7 @@
{
datum _sortIndex
{
- value = "35";
+ value = "38";
type = "int";
}
}
@@ -442,7 +442,7 @@
{
datum baseAddress
{
- value = "256";
+ value = "1280";
type = "String";
}
}
@@ -450,7 +450,7 @@
{
datum _sortIndex
{
- value = "33";
+ value = "36";
type = "int";
}
}
@@ -458,7 +458,7 @@
{
datum baseAddress
{
- value = "1184";
+ value = "12480";
type = "String";
}
}
@@ -466,7 +466,7 @@
{
datum _sortIndex
{
- value = "40";
+ value = "43";
type = "int";
}
}
@@ -474,7 +474,7 @@
{
datum baseAddress
{
- value = "1152";
+ value = "12448";
type = "String";
}
}
@@ -482,7 +482,7 @@
{
datum _sortIndex
{
- value = "41";
+ value = "44";
type = "int";
}
}
@@ -490,7 +490,7 @@
{
datum baseAddress
{
- value = "1120";
+ value = "12416";
type = "String";
}
}
@@ -498,7 +498,7 @@
{
datum _sortIndex
{
- value = "34";
+ value = "37";
type = "int";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "1024";
+ value = "12352";
type = "String";
}
}
@@ -514,7 +514,7 @@
{
datum _sortIndex
{
- value = "32";
+ value = "35";
type = "int";
}
}
@@ -522,7 +522,7 @@
{
datum baseAddress
{
- value = "1424";
+ value = "12704";
type = "String";
}
}
@@ -530,7 +530,7 @@
{
datum _sortIndex
{
- value = "38";
+ value = "41";
type = "int";
}
}
@@ -538,7 +538,7 @@
{
datum baseAddress
{
- value = "1408";
+ value = "12688";
type = "String";
}
}
@@ -546,7 +546,7 @@
{
datum _sortIndex
{
- value = "39";
+ value = "42";
type = "int";
}
}
@@ -554,7 +554,7 @@
{
datum baseAddress
{
- value = "1392";
+ value = "12672";
type = "String";
}
}
@@ -570,7 +570,7 @@
{
datum baseAddress
{
- value = "1464";
+ value = "12736";
type = "String";
}
}
@@ -586,7 +586,7 @@
{
datum baseAddress
{
- value = "1456";
+ value = "12728";
type = "String";
}
}
@@ -602,7 +602,55 @@
{
datum baseAddress
{
- value = "1280";
+ value = "12576";
+ type = "String";
+ }
+ }
+ element reg_eth10g_back0
+ {
+ datum _sortIndex
+ {
+ value = "23";
+ type = "int";
+ }
+ }
+ element reg_eth10g_back0.mem
+ {
+ datum baseAddress
+ {
+ value = "1024";
+ type = "String";
+ }
+ }
+ element reg_eth10g_back1
+ {
+ datum _sortIndex
+ {
+ value = "24";
+ type = "int";
+ }
+ }
+ element reg_eth10g_back1.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "String";
+ }
+ }
+ element reg_eth10g_qsfp_ring
+ {
+ datum _sortIndex
+ {
+ value = "22";
+ type = "int";
+ }
+ }
+ element reg_eth10g_qsfp_ring.mem
+ {
+ datum baseAddress
+ {
+ value = "512";
type = "String";
}
}
@@ -610,7 +658,7 @@
{
datum _sortIndex
{
- value = "36";
+ value = "39";
type = "int";
}
}
@@ -626,7 +674,7 @@
{
datum _sortIndex
{
- value = "37";
+ value = "40";
type = "int";
}
}
@@ -650,7 +698,7 @@
{
datum baseAddress
{
- value = "1448";
+ value = "12720";
type = "String";
}
}
@@ -666,7 +714,7 @@
{
datum baseAddress
{
- value = "1440";
+ value = "12296";
type = "String";
}
}
@@ -682,7 +730,7 @@
{
datum baseAddress
{
- value = "1312";
+ value = "12608";
type = "String";
}
}
@@ -746,7 +794,7 @@
{
datum baseAddress
{
- value = "1344";
+ value = "12640";
type = "String";
}
}
@@ -804,7 +852,7 @@
{
datum baseAddress
{
- value = "1088";
+ value = "12320";
type = "String";
}
}
@@ -822,7 +870,7 @@
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="unb2_test_ddr.qpf" />
+ <parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
@@ -1958,6 +2006,111 @@
internal="reg_epcs.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_eth10g_back0_address"
+ internal="reg_eth10g_back0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back0_clk"
+ internal="reg_eth10g_back0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back0_read"
+ internal="reg_eth10g_back0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back0_readdata"
+ internal="reg_eth10g_back0.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back0_reset"
+ internal="reg_eth10g_back0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back0_write"
+ internal="reg_eth10g_back0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back0_writedata"
+ internal="reg_eth10g_back0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back1_address"
+ internal="reg_eth10g_back1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back1_clk"
+ internal="reg_eth10g_back1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back1_read"
+ internal="reg_eth10g_back1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back1_readdata"
+ internal="reg_eth10g_back1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back1_reset"
+ internal="reg_eth10g_back1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back1_write"
+ internal="reg_eth10g_back1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_back1_writedata"
+ internal="reg_eth10g_back1.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_qsfp_ring_address"
+ internal="reg_eth10g_qsfp_ring.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_qsfp_ring_clk"
+ internal="reg_eth10g_qsfp_ring.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_qsfp_ring_read"
+ internal="reg_eth10g_qsfp_ring.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_qsfp_ring_readdata"
+ internal="reg_eth10g_qsfp_ring.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_qsfp_ring_reset"
+ internal="reg_eth10g_qsfp_ring.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_qsfp_ring_write"
+ internal="reg_eth10g_qsfp_ring.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_eth10g_qsfp_ring_writedata"
+ internal="reg_eth10g_qsfp_ring.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_io_ddr_mb_i_address"
internal="reg_io_ddr_MB_I.address"
@@ -2375,7 +2528,7 @@
<parameter name="dataAddrWidth" value="23" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x80' end='0x100' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x100' end='0x180' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x180' end='0x200' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x200' end='0x280' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x280' end='0x300' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x300' end='0x380' /><slave name='avs_eth_1.mms_reg' start='0x380' end='0x3C0' /><slave name='avs_eth_0.mms_reg' start='0x3C0' end='0x400' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x400' end='0x440' /><slave name='timer_0.s1' start='0x440' end='0x460' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x460' end='0x480' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x480' end='0x4A0' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x4A0' end='0x4C0' /><slave name='reg_diag_bg_10gbe.mem' start='0x4C0' end='0x4E0' /><slave name='reg_diag_bg_1gbe.mem' start='0x4E0' end='0x500' /><slave name='reg_epcs.mem' start='0x500' end='0x520' /><slave name='reg_remu.mem' start='0x520' end='0x540' /><slave name='reg_unb_sens.mem' start='0x540' end='0x560' /><slave name='pio_wdi.s1' start='0x560' end='0x570' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x570' end='0x580' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x580' end='0x590' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x590' end='0x5A0' /><slave name='reg_mmdp_data.mem' start='0x5A0' end='0x5A8' /><slave name='reg_mmdp_ctrl.mem' start='0x5A8' end='0x5B0' /><slave name='reg_dpmm_data.mem' start='0x5B0' end='0x5B8' /><slave name='reg_dpmm_ctrl.mem' start='0x5B8' end='0x5C0' /><slave name='pio_pps.mem' start='0x5C0' end='0x5C8' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x5C8' end='0x5D0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0x4000' end='0x6000' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x6000' end='0x8000' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0x8000' end='0xA000' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xC000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xC000' end='0xE000' /><slave name='avs_eth_0.mms_tse' start='0xE000' end='0xF000' /><slave name='avs_eth_1.mms_ram' start='0xF000' end='0x10000' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x80' end='0x100' /><slave name='reg_eth10g_back1.mem' start='0x100' end='0x200' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' /><slave name='reg_eth10g_back0.mem' start='0x400' end='0x500' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x500' end='0x580' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x580' end='0x600' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x600' end='0x680' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x680' end='0x700' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x700' end='0x780' /><slave name='avs_eth_1.mms_reg' start='0x780' end='0x7C0' /><slave name='avs_eth_0.mms_reg' start='0x7C0' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3040' end='0x3080' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x3080' end='0x30A0' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x30A0' end='0x30C0' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x30C0' end='0x30E0' /><slave name='reg_diag_bg_10gbe.mem' start='0x30E0' end='0x3100' /><slave name='reg_diag_bg_1gbe.mem' start='0x3100' end='0x3120' /><slave name='reg_epcs.mem' start='0x3120' end='0x3140' /><slave name='reg_remu.mem' start='0x3140' end='0x3160' /><slave name='reg_unb_sens.mem' start='0x3160' end='0x3180' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x3180' end='0x3190' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x3190' end='0x31A0' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x31A0' end='0x31B0' /><slave name='reg_mmdp_ctrl.mem' start='0x31B0' end='0x31B8' /><slave name='reg_dpmm_data.mem' start='0x31B8' end='0x31C0' /><slave name='reg_dpmm_ctrl.mem' start='0x31C0' end='0x31C8' /><slave name='pio_pps.mem' start='0x31C8' end='0x31D0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x31D0' end='0x31D8' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0x4000' end='0x6000' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x6000' end='0x8000' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0x8000' end='0xA000' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xC000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xC000' end='0xE000' /><slave name='avs_eth_0.mms_tse' start='0xE000' end='0xF000' /><slave name='avs_eth_1.mms_ram' start='0xF000' end='0x10000' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@@ -2816,6 +2969,33 @@
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
</module>
+ <module
+ name="reg_eth10g_back0"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_eth10g_back1"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_eth10g_qsfp_ring"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ <parameter name="g_adr_w" value="7" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
<module name="reg_io_ddr_MB_I" kind="avs_common_mm" version="1.0" enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
<parameter name="g_adr_w" value="16" />
@@ -2905,7 +3085,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x05c8" />
+ <parameter name="baseAddress" value="0x31d0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2923,7 +3103,7 @@
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0540" />
+ <parameter name="baseAddress" value="0x3160" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2950,7 +3130,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x05c0" />
+ <parameter name="baseAddress" value="0x31c8" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2968,7 +3148,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0520" />
+ <parameter name="baseAddress" value="0x3140" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2977,7 +3157,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0500" />
+ <parameter name="baseAddress" value="0x3120" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2986,7 +3166,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x05b8" />
+ <parameter name="baseAddress" value="0x31c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2995,7 +3175,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x05b0" />
+ <parameter name="baseAddress" value="0x31b8" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3004,7 +3184,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x05a8" />
+ <parameter name="baseAddress" value="0x31b0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3013,7 +3193,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x05a0" />
+ <parameter name="baseAddress" value="0x3008" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3031,7 +3211,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0300" />
+ <parameter name="baseAddress" value="0x0700" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3040,7 +3220,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0280" />
+ <parameter name="baseAddress" value="0x0680" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3058,7 +3238,7 @@
start="cpu_0.data_master"
end="reg_diag_bg_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x04e0" />
+ <parameter name="baseAddress" value="0x3100" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3094,7 +3274,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0200" />
+ <parameter name="baseAddress" value="0x0600" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3130,7 +3310,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0180" />
+ <parameter name="baseAddress" value="0x0580" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3148,7 +3328,7 @@
start="cpu_0.data_master"
end="reg_diag_bg_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x04c0" />
+ <parameter name="baseAddress" value="0x30e0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3166,7 +3346,7 @@
start="cpu_0.data_master"
end="reg_diag_tx_seq_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0590" />
+ <parameter name="baseAddress" value="0x31a0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3175,7 +3355,7 @@
start="cpu_0.data_master"
end="reg_diag_rx_seq_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x04a0" />
+ <parameter name="baseAddress" value="0x30c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3184,7 +3364,7 @@
start="cpu_0.data_master"
end="reg_diag_tx_seq_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0400" />
+ <parameter name="baseAddress" value="0x3040" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3193,7 +3373,7 @@
start="cpu_0.data_master"
end="reg_diag_rx_seq_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0100" />
+ <parameter name="baseAddress" value="0x0500" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3202,7 +3382,7 @@
start="cpu_0.data_master"
end="reg_diag_tx_seq_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0580" />
+ <parameter name="baseAddress" value="0x3190" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3211,7 +3391,7 @@
start="cpu_0.data_master"
end="reg_diag_rx_seq_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0480" />
+ <parameter name="baseAddress" value="0x30a0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3238,7 +3418,7 @@
start="cpu_0.data_master"
end="reg_diag_tx_seq_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0570" />
+ <parameter name="baseAddress" value="0x3180" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3247,7 +3427,7 @@
start="cpu_0.data_master"
end="reg_diag_rx_seq_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0460" />
+ <parameter name="baseAddress" value="0x3080" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3259,6 +3439,33 @@
<parameter name="baseAddress" value="0x0080" />
<parameter name="defaultConnection" value="false" />
</connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_eth10g_qsfp_ring.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0200" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_eth10g_back0.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0400" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_eth10g_back1.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
kind="avalon"
version="15.0"
@@ -3283,7 +3490,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x03c0" />
+ <parameter name="baseAddress" value="0x07c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3292,7 +3499,7 @@
start="cpu_0.data_master"
end="avs_eth_1.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0380" />
+ <parameter name="baseAddress" value="0x0780" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3328,7 +3535,7 @@
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0560" />
+ <parameter name="baseAddress" value="0x3010" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3337,7 +3544,7 @@
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0440" />
+ <parameter name="baseAddress" value="0x3020" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3543,6 +3750,21 @@
version="15.0"
start="clk_0.clk"
end="reg_diag_data_buffer_ddr_MB_II.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_eth10g_qsfp_ring.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_eth10g_back0.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_eth10g_back1.system" />
<connection
kind="interrupt"
version="15.0"
@@ -3788,6 +4010,21 @@
version="15.0"
start="clk_0.clk_reset"
end="reg_diag_data_buffer_ddr_MB_II.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_eth10g_qsfp_ring.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_eth10g_back0.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_eth10g_back1.system_reset" />
<connection
kind="reset"
version="15.0"
@@ -4013,6 +4250,21 @@
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_diag_data_buffer_ddr_MB_II.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_eth10g_qsfp_ring.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_eth10g_back0.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_eth10g_back1.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
index d9a70e0a5bf9de09c6f104d2fc0219de58d04e09..fa0094d938028697737b8f0256f73a8466ea9f73 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
@@ -32,7 +32,7 @@ ENTITY unb2_test_10GbE IS
GENERIC (
g_design_name : STRING := "unb2_test_10GbE";
--g_design_note : STRING := "10GbE: 3xQSFP";
- g_design_note : STRING := "10GbE: 6xQSFP 2xRING";
+ g_design_note : STRING := "10GbE: 2xQSFP 1xRING";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
@@ -77,8 +77,8 @@ ENTITY unb2_test_10GbE IS
-- ring transceivers
RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ --RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ --RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
@@ -88,14 +88,14 @@ ENTITY unb2_test_10GbE IS
QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
@@ -156,8 +156,8 @@ BEGIN
-- ring transceivers
RING_0_RX => RING_0_RX,
RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
+ --RING_1_RX => RING_1_RX,
+ --RING_1_TX => RING_1_TX,
-- pmbus
PMBUS_SC => PMBUS_SC,
PMBUS_SD => PMBUS_SD,
@@ -167,14 +167,14 @@ BEGIN
QSFP_0_TX => QSFP_0_TX,
QSFP_1_RX => QSFP_1_RX,
QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
+ --QSFP_2_RX => QSFP_2_RX,
+ --QSFP_2_TX => QSFP_2_TX,
+ --QSFP_3_RX => QSFP_3_RX,
+ --QSFP_3_TX => QSFP_3_TX,
+ --QSFP_4_RX => QSFP_4_RX,
+ --QSFP_4_TX => QSFP_4_TX,
+ --QSFP_5_RX => QSFP_5_RX,
+ --QSFP_5_TX => QSFP_5_TX,
QSFP_SDA => QSFP_SDA,
QSFP_SCL => QSFP_SCL,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index ed88977f8e68a7a7d1ada24586f0283e7b813b86..f0d4577b1d5868fd5f5fcabb8428fb4b1c03753e 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -174,6 +174,13 @@ ENTITY mmm_unb2_test IS
reg_tr_10GbE_back1_mosi : OUT t_mem_mosi;
reg_tr_10GbE_back1_miso : IN t_mem_miso;
+ reg_eth10g_qsfp_ring_mosi : OUT t_mem_mosi;
+ reg_eth10g_qsfp_ring_miso : IN t_mem_miso;
+ reg_eth10g_back0_mosi : OUT t_mem_mosi;
+ reg_eth10g_back0_miso : IN t_mem_miso;
+ reg_eth10g_back1_mosi : OUT t_mem_mosi;
+ reg_eth10g_back1_miso : IN t_mem_miso;
+
-- DDR4 : MB I
reg_io_ddr_MB_I_mosi : OUT t_mem_mosi;
reg_io_ddr_MB_I_miso : IN t_mem_miso;
@@ -241,6 +248,12 @@ ARCHITECTURE str OF mmm_unb2_test IS
CONSTANT c_reg_tr_10GbE_back0_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_back0 * pow2(c_reg_tr_10GbE_adr_w));
CONSTANT c_reg_tr_10GbE_back1_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_back1 * pow2(c_reg_tr_10GbE_adr_w));
+ -- reg_eth10g
+ CONSTANT c_reg_eth10g_adr_w : NATURAL := 1;
+ CONSTANT c_reg_eth10g_qsfp_ring_multi_adr_w : NATURAL := ceil_log2((g_nof_streams_qsfp+g_nof_streams_ring) * pow2(c_reg_eth10g_adr_w));
+ CONSTANT c_reg_eth10g_back0_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_back0 * pow2(c_reg_eth10g_adr_w));
+ CONSTANT c_reg_eth10g_back1_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_back1 * pow2(c_reg_eth10g_adr_w));
+
-- BSN monitors
CONSTANT c_reg_rsp_bsn_monitor_1GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
CONSTANT c_reg_rsp_bsn_monitor_10GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
@@ -377,6 +390,13 @@ BEGIN
u_mm_file_reg_tr_10GbE_back1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
+ u_mm_file_reg_eth10g_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
+ PORT MAP(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+ u_mm_file_reg_eth10g_back0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
+ PORT MAP(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+ u_mm_file_reg_eth10g_back1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
+ PORT MAP(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
+
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
@@ -585,6 +605,30 @@ BEGIN
reg_tr_10gbe_back1_readdata_export => reg_tr_10GbE_back1_miso.rddata(c_word_w-1 DOWNTO 0),
reg_tr_10gbe_back1_waitrequest_export => reg_tr_10GbE_back1_miso.waitrequest,
+ reg_eth10g_qsfp_ring_reset_export => OPEN,
+ reg_eth10g_qsfp_ring_clk_export => OPEN,
+ reg_eth10g_qsfp_ring_address_export => reg_eth10g_qsfp_ring_mosi.address(c_reg_eth10g_qsfp_ring_multi_adr_w-1 DOWNTO 0),
+ reg_eth10g_qsfp_ring_write_export => reg_eth10g_qsfp_ring_mosi.wr,
+ reg_eth10g_qsfp_ring_writedata_export => reg_eth10g_qsfp_ring_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth10g_qsfp_ring_read_export => reg_eth10g_qsfp_ring_mosi.rd,
+ reg_eth10g_qsfp_ring_readdata_export => reg_eth10g_qsfp_ring_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth10g_back0_reset_export => OPEN,
+ reg_eth10g_back0_clk_export => OPEN,
+ reg_eth10g_back0_address_export => reg_eth10g_back0_mosi.address(c_reg_eth10g_back0_multi_adr_w-1 DOWNTO 0),
+ reg_eth10g_back0_write_export => reg_eth10g_back0_mosi.wr,
+ reg_eth10g_back0_writedata_export => reg_eth10g_back0_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth10g_back0_read_export => reg_eth10g_back0_mosi.rd,
+ reg_eth10g_back0_readdata_export => reg_eth10g_back0_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_eth10g_back1_reset_export => OPEN,
+ reg_eth10g_back1_clk_export => OPEN,
+ reg_eth10g_back1_address_export => reg_eth10g_back1_mosi.address(c_reg_eth10g_back1_multi_adr_w-1 DOWNTO 0),
+ reg_eth10g_back1_write_export => reg_eth10g_back1_mosi.wr,
+ reg_eth10g_back1_writedata_export => reg_eth10g_back1_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
+ reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w-1 DOWNTO 0),
+
-- -- the_reg_dp_offload_tx_1GbE
-- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
-- reg_dp_offload_tx_1GbE_clk_export => OPEN,
@@ -661,37 +705,37 @@ BEGIN
ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
ram_diag_data_buffer_10gbe_readdata_export => ram_diag_data_buf_10gbe_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_diag_bg_1GbE_reset_export => OPEN,
- reg_diag_bg_1GbE_clk_export => OPEN,
- reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
- reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
- reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
- reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
- reg_diag_bg_10GbE_reset_export => OPEN,
- reg_diag_bg_10GbE_clk_export => OPEN,
- reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
- reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
- reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
- reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
- ram_diag_bg_1GbE_reset_export => OPEN,
- ram_diag_bg_1GbE_clk_export => OPEN,
- ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w-1 DOWNTO 0),
- ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
- ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
- ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
- ram_diag_bg_10GbE_reset_export => OPEN,
- ram_diag_bg_10GbE_clk_export => OPEN,
- ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w-1 DOWNTO 0),
- ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
- ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
- ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_1GbE_reset_export => OPEN,
+ reg_diag_bg_1GbE_clk_export => OPEN,
+ reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
+ reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
+ reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
+ reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_bg_10GbE_reset_export => OPEN,
+ reg_diag_bg_10GbE_clk_export => OPEN,
+ reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
+ reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
+ reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
+ reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ ram_diag_bg_1GbE_reset_export => OPEN,
+ ram_diag_bg_1GbE_clk_export => OPEN,
+ ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w-1 DOWNTO 0),
+ ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
+ ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
+ ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ ram_diag_bg_10GbE_reset_export => OPEN,
+ ram_diag_bg_10GbE_clk_export => OPEN,
+ ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w-1 DOWNTO 0),
+ ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
+ ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
+ ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
reg_io_ddr_MB_I_clk_export => OPEN,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 2b3875d9d8738854a84caccf8c7f50a47046e71c..33573db31f269fa327902c0d3ea331dc8bc39b44 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -28,321 +28,342 @@ PACKAGE qsys_unb2_test_pkg IS
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-- $RADIOHDL/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
-----------------------------------------------------------------------------
- component qsys_unb2_test is
- port (
- avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
- avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
- avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
- avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
- avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
- avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
- avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
- avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
- avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
- avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
- avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
- avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
- avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
- avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
- avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
- avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
- avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
- avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
- avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
- avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
- clk_clk : in std_logic := '0'; -- clk.clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
- pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
- pio_pps_read_export : out std_logic; -- pio_pps_read.export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
- pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
- pio_pps_write_export : out std_logic; -- pio_pps_write.export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
- pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
- pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
- pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
- pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
- pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
- ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
- ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
- ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
- ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
- reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
- reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
- reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
- reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_10gbe_address.export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
- reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
- reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
- reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
- reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
- reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
- reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
- reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
- reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
- reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
- reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
- reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
- reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
- reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
- reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
- reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
- reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
- reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
- reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
- reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
- reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
- reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
- reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
- reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
- reg_remu_read_export : out std_logic; -- reg_remu_read.export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
- reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
- reg_remu_write_export : out std_logic; -- reg_remu_write.export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
- reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
- reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
- reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
- reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- reg_unb_sens_address.export
- reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
- reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
- reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
- reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
- reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
- reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
- reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
- reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
- reset_reset_n : in std_logic := '0'; -- reset.reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
- rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
- rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
- rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
- rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
- );
- end component qsys_unb2_test;
-
+ component qsys_unb2_test is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_irq_export : in std_logic := 'X'; -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back0_read_export : out std_logic; -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back0_write_export : out std_logic; -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back0_clk_export : out std_logic; -- export
+ reg_eth10g_back0_reset_export : out std_logic; -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back1_read_export : out std_logic; -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back1_write_export : out std_logic; -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back1_clk_export : out std_logic; -- export
+ reg_eth10g_back1_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2_test;
+
END qsys_unb2_test_pkg;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index d32c050110cecec6c56df74585d003e966dc6c34..a2b2573d3fe5c47537a708c42824a4c3f5374a5c 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -93,8 +93,8 @@ ENTITY unb2_test IS
-- ring transceivers
RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ --RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
+ --RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
@@ -104,14 +104,14 @@ ENTITY unb2_test IS
QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ --QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ --QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ --QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ --QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
@@ -150,8 +150,8 @@ ARCHITECTURE str OF unb2_test IS
CONSTANT c_use_MB_II : BOOLEAN := g_design_name="unb2_test_ddr_MB_II" OR g_design_name="unb2_test_ddr_MB_I_II" OR g_design_name="unb2_test_all";
-- transceivers
- CONSTANT c_nof_qsfp : NATURAL := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;--8
- CONSTANT c_nof_ring : NATURAL := c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
+ CONSTANT c_nof_qsfp : NATURAL := 8;--c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;--8
+ CONSTANT c_nof_ring : NATURAL := 12;--c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
CONSTANT c_nof_back0 : NATURAL := c_unb2_board_tr_back.bus_w;
CONSTANT c_nof_back1 : NATURAL := c_unb2_board_tr_back.bus_w;
@@ -309,7 +309,6 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0);
-
SIGNAL reg_tr_10GbE_qsfp_ring_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_qsfp_ring_miso : t_mem_miso;
SIGNAL reg_tr_10GbE_back0_mosi : t_mem_mosi;
@@ -317,6 +316,13 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_tr_10GbE_back1_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_back1_miso : t_mem_miso;
+ SIGNAL reg_eth10g_qsfp_ring_mosi : t_mem_mosi;
+ SIGNAL reg_eth10g_qsfp_ring_miso : t_mem_miso;
+ SIGNAL reg_eth10g_back0_mosi : t_mem_mosi;
+ SIGNAL reg_eth10g_back0_miso : t_mem_miso;
+ SIGNAL reg_eth10g_back1_mosi : t_mem_mosi;
+ SIGNAL reg_eth10g_back1_miso : t_mem_miso;
+
SIGNAL reg_diag_bg_1GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_1GbE_miso : t_mem_miso;
SIGNAL ram_diag_bg_1GbE_mosi : t_mem_mosi;
@@ -390,7 +396,7 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL ram_diag_data_buf_ddr_MB_II_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_ddr_MB_II_miso : t_mem_miso;
- -- Interface: 1GbE UDP streaming ports
+ -- Interface: 1GbE UDP streaming ports
SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
@@ -664,6 +670,16 @@ BEGIN
reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
+ reg_eth10g_back1_miso => reg_eth10g_back1_miso,
+
-- DDR4 : MB I
reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
@@ -808,16 +824,6 @@ BEGIN
);
--- u_sa_clk_buf : ENTITY tech_clkbuf_lib.tech_clkbuf
--- GENERIC MAP (
--- g_technology => g_technology,
--- g_clock_net => "GLOBAL"
--- )
--- PORT MAP (
--- inclk => SA_CLK,
--- outclk => SA_CLK_buf
--- );
-
u_tr_10GbE_qsfp_and_ring: ENTITY unb2_board_lib.unb2_board_10gbe -- QSFP and Ring lines
GENERIC MAP (
g_technology => g_technology,
@@ -833,6 +839,8 @@ BEGIN
mm_clk => mm_clk,
reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
dp_rst => dp_rst,
dp_clk => dp_clk,
@@ -853,17 +861,17 @@ BEGIN
i_QSFP_RX(0) <= QSFP_0_RX;
i_QSFP_RX(1) <= QSFP_1_RX;
- i_QSFP_RX(2) <= QSFP_2_RX;
- i_QSFP_RX(3) <= QSFP_3_RX;
- i_QSFP_RX(4) <= QSFP_4_RX;
- i_QSFP_RX(5) <= QSFP_5_RX;
+ --i_QSFP_RX(2) <= QSFP_2_RX;
+ --i_QSFP_RX(3) <= QSFP_3_RX;
+ --i_QSFP_RX(4) <= QSFP_4_RX;
+ --i_QSFP_RX(5) <= QSFP_5_RX;
QSFP_0_TX <= i_QSFP_TX(0);
QSFP_1_TX <= i_QSFP_TX(1);
- QSFP_2_TX <= i_QSFP_TX(2);
- QSFP_3_TX <= i_QSFP_TX(3);
- QSFP_4_TX <= i_QSFP_TX(4);
- QSFP_5_TX <= i_QSFP_TX(5);
+ --QSFP_2_TX <= i_QSFP_TX(2);
+ --QSFP_3_TX <= i_QSFP_TX(3);
+ --QSFP_4_TX <= i_QSFP_TX(4);
+ --QSFP_5_TX <= i_QSFP_TX(5);
@@ -895,9 +903,9 @@ BEGIN
END GENERATE;
i_RING_RX(0) <= RING_0_RX;
- i_RING_RX(1) <= RING_1_RX;
+ --i_RING_RX(1) <= RING_1_RX;
RING_0_TX <= i_RING_TX(0);
- RING_1_TX <= i_RING_TX(1);
+ --RING_1_TX <= i_RING_TX(1);
u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
GENERIC MAP (
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index 7c3260bcaf28b4a35fdb7e71372d73aafa66deba..d439accf217c984644ff98c75f6429b0cf0404a4 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -231,10 +231,10 @@ BEGIN
-- Serial I/O
QSFP_0_TX => si_lpbk_0,
QSFP_0_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_1,
- QSFP_1_RX => si_lpbk_1,
- QSFP_2_TX => si_lpbk_2,
- QSFP_2_RX => si_lpbk_2,
+-- QSFP_1_TX => si_lpbk_1,
+-- QSFP_1_RX => si_lpbk_1,
+-- QSFP_2_TX => si_lpbk_2,
+-- QSFP_2_RX => si_lpbk_2,
-- QSFP_3_TX => si_lpbk_3,
-- QSFP_3_RX => si_lpbk_3,
-- QSFP_4_TX => si_lpbk_4,