diff --git a/tools/hdltool_readme.txt b/tools/hdltool_readme.txt
index fb04a4363913c6d0c68335b4352be9d949741a16..a0d76b7ecb9d09a31958ec55a0373f03f141cf6f 100644
--- a/tools/hdltool_readme.txt
+++ b/tools/hdltool_readme.txt
@@ -133,12 +133,23 @@ d) Compiling the Altera libraries for simulation with Modelsim
 The Altera verilog and vhdl libraries for the required FPGA device families can be compile using:
 
  > tools/quartus/run_altera_simlib_comp <tool target> <compilation output directory> <FPGA device family>
-
-This run_altera_simlib_comp script must be used and not the tools/Launch simulation library compiler in the Quartus GUI, because
+ 
+For Modelsim versions newer than about version 10 this run_altera_simlib_comp script must be used and not the tools/Launch simulation library compiler in the Quartus GUI, because
 the libraries have to be compiled with the 'vlib -type directory' option to be able to use 'mk all'. 
 
 The run_altera_simlib_comp uses set_modelsim and set_quartus to make the tool settings for Modelsim and Quartus.
 
+For example:
+
+ # For toolset 'unb1' with only stratixiv the libraries can be compiled with the GUI (because 'unb1' uses Modelsim 6.6.c < 10) or one may use:
+ > run_altera_simlib_comp unb1 11.1 stratixiv
+
+ # For toolset 'unb2' with arria10 and also support for stratixiv
+ > run_altera_simlib_comp unb2 14.1 stratixiv
+ > run_altera_simlib_comp unb2 14.1 arria10
+
+Note that the second argument of the Quartus version is used as OUTPUT_DIR and must match the toolset.
+
 
 e) Quartus user_components.ipx