From 7f0170e79da677e20f383945b3f4e6f1a47b5b83 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 4 Nov 2016 10:03:46 +0000
Subject: [PATCH] Use internal SCLK in aduh_quad_scope.
---
libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd | 8 ++++----
libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd b/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd
index 3c5e420329..81a84c4626 100644
--- a/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd
@@ -39,8 +39,7 @@ ENTITY aduh_quad_scope IS
g_ai : t_c_aduh_dd_ai := c_aduh_dd_ai
);
PORT (
- -- Sample clock
- SCLK : IN STD_LOGIC := '0'; -- sample clk, use only for simulation purposes
+ DCLK : IN STD_LOGIC := '0'; -- digital processing clk
-- Streaming samples (can be from ADU or from internal WG)
sp_sosi_arr : IN t_dp_sosi_arr(0 TO g_ai.nof_sp-1) -- = [0:3] = Signal Paths [A,B,C,D]
@@ -65,14 +64,15 @@ BEGIN
u_dp_scope : ENTITY dp_lib.dp_wideband_sp_arr_scope
GENERIC MAP (
g_sim => g_sim,
+ g_use_sclk => FALSE,
g_nof_streams => g_ai.nof_sp,
g_wideband_factor => c_wideband_factor,
g_wideband_big_endian => FALSE,
g_dat_w => g_ai.port_w
)
PORT MAP (
- -- Sample clock
- SCLK => SCLK,
+ -- Digital processing clk
+ DCLK => DCLK,
-- Streaming samples
sp_sosi_arr => dp_sosi_arr -- = [3:0] = Signal Paths [D,C,B,A]
diff --git a/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd b/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
index 4458526eac..a0921a0764 100644
--- a/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
@@ -296,8 +296,8 @@ BEGIN
g_ai => c_aduh_dd_ai
)
PORT MAP (
- -- Sample clock
- SCLK => SCLK,
+ -- Digital processing clock
+ DCLK => dp_clk,
-- Streaming samples (can be from ADU or from internal WG)
sp_sosi_arr => aduh_sosi_arr
--
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