From 7ef666eb549e34bc0bcef2719d1b2d3d39e768ca Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 24 Feb 2015 14:02:03 +0000
Subject: [PATCH] Use new dp_stimuli_st.vhd component.
---
libraries/base/dp/tb/vhdl/dp_stimuli_st.vhd | 177 ++++++++++++++++++
.../base/dp/tb/vhdl/tb_dp_example_no_dut.vhd | 121 +++++-------
2 files changed, 222 insertions(+), 76 deletions(-)
create mode 100644 libraries/base/dp/tb/vhdl/dp_stimuli_st.vhd
diff --git a/libraries/base/dp/tb/vhdl/dp_stimuli_st.vhd b/libraries/base/dp/tb/vhdl/dp_stimuli_st.vhd
new file mode 100644
index 0000000000..a7f6718e37
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/dp_stimuli_st.vhd
@@ -0,0 +1,177 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- . The dp_stimuli_st generates as stream of packets with counter data.
+-- Description:
+--
+-- Usage:
+-- . See tb_dp_example_no_dut for usage example
+--
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE work.tb_dp_pkg.ALL;
+
+
+ENTITY dp_stimuli_st IS
+ GENERIC (
+ -- general
+ g_index : NATURAL := 0;
+ g_random_w : NATURAL := 15; -- use different random width for stimuli and for verify to have different random sequences
+ g_flow_control : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
+ -- specific
+ g_in_dat_w : NATURAL := 32;
+ g_in_nof_words : NATURAL := 1;
+ g_nof_repeat : NATURAL := 5;
+ g_pkt_len : NATURAL := 16; -- must be a multiple of g_in_nof_words
+ g_pkt_gap : NATURAL := 4
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+
+ -- Generate stimuli
+ stimuli_src_in : IN t_dp_siso;
+ stimuli_src_out : OUT t_dp_sosi;
+
+ -- End of stimuli
+ expected_verify_snk_in : OUT t_dp_sosi; -- expected verify_snk_in after end of stimuli
+ verify_last : OUT STD_LOGIC; -- trigger verify to verify the expected_verify_snk_in
+ tb_end : OUT STD_LOGIC -- signal end of tb as far as this dp_stimuli_st is concerned
+ );
+END dp_stimuli_st;
+
+
+ARCHITECTURE str OF dp_stimuli_st IS
+
+ CONSTANT c_pulse_active : NATURAL := g_in_nof_words;
+ CONSTANT c_pulse_period : NATURAL := g_in_nof_words;
+
+ CONSTANT c_sync_period : NATURAL := 10;
+ CONSTANT c_sync_offset : NATURAL := 7;
+
+ CONSTANT c_data_init : INTEGER := -1;
+ CONSTANT c_bsn_init : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := X"0000000000000000"; -- X"0877665544332211"
+ CONSTANT c_err_init : NATURAL := 247;
+ CONSTANT c_channel_init : INTEGER := 5; -- fixed
+
+ SIGNAL random : STD_LOGIC_VECTOR(g_random_w-1 DOWNTO 0) := TO_UVEC(g_index, g_random_w); -- use different initialization to have different random sequences per stream
+ SIGNAL pulse : STD_LOGIC;
+ SIGNAL pulse_en : STD_LOGIC := '1';
+
+ SIGNAL stimuli_en : STD_LOGIC := '1';
+ SIGNAL stimuli_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
+ SIGNAL i_stimuli_src_out : t_dp_sosi;
+
+ SIGNAL dut_snk_out : t_dp_siso;
+ SIGNAL dut_snk_in : t_dp_sosi;
+
+ SIGNAL dut_src_in : t_dp_siso;
+ SIGNAL dut_src_out : t_dp_sosi;
+
+BEGIN
+
+ stimuli_src_out <= i_stimuli_src_out;
+
+ random <= func_common_random(random) WHEN rising_edge(clk);
+
+ proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse);
+
+ ------------------------------------------------------------------------------
+ -- STREAM CONTROL
+ ------------------------------------------------------------------------------
+
+ stimuli_en <= '1' WHEN g_flow_control=e_active ELSE
+ random(random'HIGH) WHEN g_flow_control=e_random ELSE
+ pulse WHEN g_flow_control=e_pulse;
+
+ ------------------------------------------------------------------------------
+ -- DATA GENERATION
+ ------------------------------------------------------------------------------
+
+ -- Generate data path input data
+ p_stimuli_st : PROCESS
+ VARIABLE v_sosi : t_dp_sosi := c_dp_sosi_rst;
+ BEGIN
+ -- Initialisations
+ expected_verify_snk_in <= c_dp_sosi_rst;
+ verify_last <= '0';
+ tb_end <= '0';
+
+ -- Adjust initial sosi field values by -1 to compensate for auto increment
+ v_sosi.bsn := INCR_UVEC(c_bsn_init, -1);
+ v_sosi.channel := INCR_UVEC(TO_DP_CHANNEL(c_channel_init), -1);
+ v_sosi.data := INCR_UVEC(TO_DP_DATA(c_data_init), -1);
+ v_sosi.err := INCR_UVEC(TO_DP_ERROR(c_err_init), -1);
+
+ i_stimuli_src_out <= c_dp_sosi_rst;
+ proc_common_wait_until_low(clk, rst);
+ proc_common_wait_some_cycles(clk, 5);
+
+ -- Generate c_nof_repeat packets
+ FOR I IN 0 TO g_nof_repeat-1 LOOP
+ -- Auto increment v_sosi field values for this packet
+ v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
+ v_sosi.sync := sel_a_b((UNSIGNED(v_sosi.bsn) MOD c_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
+ v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w-1 DOWNTO 0)); -- wrap when >= 2**g_in_dat_w
+ v_sosi.err := INCR_UVEC(v_sosi.err, 1);
+
+ -- Send packet
+ proc_dp_gen_block_data(g_in_dat_w, TO_UINT(v_sosi.data), g_pkt_len, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn, clk, stimuli_en, stimuli_src_in, i_stimuli_src_out);
+
+ -- Insert optional gap between the packets
+ proc_common_wait_some_cycles(clk, g_pkt_gap);
+ END LOOP;
+
+ -- Determine expected sosi field values after end of stimuli
+ -- . e_qual
+ v_sosi.bsn := STD_LOGIC_VECTOR( UNSIGNED(c_bsn_init) + g_nof_repeat-1);
+ v_sosi.channel := TO_DP_CHANNEL(c_channel_init + g_nof_repeat-1);
+ v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_repeat-1);
+ -- . account for g_pkt_len
+ v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len-1);
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w-1 DOWNTO 0)); -- wrap when >= 2**g_in_dat_w
+ expected_verify_snk_in <= v_sosi;
+
+ -- Signal end of stimuli
+ proc_common_wait_some_cycles(clk, 100); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ proc_common_gen_pulse(clk, verify_last);
+ proc_common_wait_some_cycles(clk, 50);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ ------------------------------------------------------------------------------
+ -- Auxiliary
+ ------------------------------------------------------------------------------
+
+ -- Map to slv to ease monitoring in wave window
+ stimuli_data <= i_stimuli_src_out.data(g_in_dat_w-1 DOWNTO 0);
+
+END str;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
index dd4578c59c..4f1aeb880d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
@@ -157,13 +157,10 @@ ARCHITECTURE tb OF tb_dp_example_no_dut IS
SIGNAL rst : STD_LOGIC := '1';
SIGNAL sl1 : STD_LOGIC := '1';
- SIGNAL random_0 : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
SIGNAL random_1 : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
- SIGNAL pulse_0 : STD_LOGIC;
SIGNAL pulse_1 : STD_LOGIC;
SIGNAL pulse_en : STD_LOGIC := '1';
- SIGNAL stimuli_en : STD_LOGIC := '1';
SIGNAL stimuli_src_in : t_dp_siso;
SIGNAL stimuli_src_out : t_dp_sosi;
SIGNAL stimuli_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
@@ -177,7 +174,7 @@ ARCHITECTURE tb OF tb_dp_example_no_dut IS
SIGNAL prev_verify_snk_out : t_dp_siso;
SIGNAL verify_snk_out : t_dp_siso := c_dp_siso_rdy;
SIGNAL verify_snk_in : t_dp_sosi;
- SIGNAL verify_snk_in_data : STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0); -- used to hold valid data for verify at verify_done
+ SIGNAL verify_snk_in_data : STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0); -- used to hold valid data for verify at verify_last
SIGNAL verify_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL prev_verify_snk_in : t_dp_sosi;
@@ -185,7 +182,7 @@ ARCHITECTURE tb OF tb_dp_example_no_dut IS
SIGNAL verify_en_valid : STD_LOGIC := '0';
SIGNAL verify_en_sop : STD_LOGIC := '0';
SIGNAL verify_en_eop : STD_LOGIC := '0';
- SIGNAL verify_done : STD_LOGIC := '0';
+ SIGNAL verify_last : STD_LOGIC := '0';
SIGNAL expected_verify_snk_in : t_dp_sosi;
SIGNAL exp_size : NATURAL;
@@ -196,96 +193,68 @@ BEGIN
clk <= (NOT clk) OR tb_end AFTER clk_period/2;
rst <= '1', '0' AFTER clk_period*7;
- random_0 <= func_common_random(random_0) WHEN rising_edge(clk);
+ ------------------------------------------------------------------------------
+ -- DATA GENERATION
+ ------------------------------------------------------------------------------
+
+ u_dp_stimuli_st : ENTITY work.dp_stimuli_st
+ GENERIC MAP (
+ -- general
+ g_index => 0, -- only one stream so choose index 0
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- specific
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ stimuli_src_in => stimuli_src_in,
+ stimuli_src_out => stimuli_src_out,
+
+ -- End of stimuli
+ expected_verify_snk_in => expected_verify_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_last => verify_last, -- trigger verify to verify the expected_verify_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stimuli_st is concerned
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- DATA VERIFICATION
+ ------------------------------------------------------------------------------
+
random_1 <= func_common_random(random_1) WHEN rising_edge(clk);
- proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period+1, '1', rst, clk, pulse_en, pulse_1);
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
- stimuli_en <= '1' WHEN g_flow_control_stimuli=e_active ELSE
- random_0(random_0'HIGH) WHEN g_flow_control_stimuli=e_random ELSE
- pulse_0 WHEN g_flow_control_stimuli=e_pulse;
-
verify_snk_out.ready <= '1' WHEN g_flow_control_verify=e_active ELSE
random_1(random_1'HIGH) WHEN g_flow_control_verify=e_random ELSE
pulse_1 WHEN g_flow_control_verify=e_pulse;
- ------------------------------------------------------------------------------
- -- DATA GENERATION
- ------------------------------------------------------------------------------
-
- -- Generate data path input data
- p_stimuli_st : PROCESS
- VARIABLE v_sosi : t_dp_sosi := c_dp_sosi_rst;
- BEGIN
- -- Adjust initial sosi field values by -1 to compensate for auto increment
- v_sosi.bsn := INCR_UVEC(c_bsn_init, -1);
- v_sosi.channel := INCR_UVEC(TO_DP_CHANNEL(c_channel_init), -1);
- v_sosi.data := INCR_UVEC(TO_DP_DATA(c_data_init), -1);
- v_sosi.err := INCR_UVEC(TO_DP_ERROR(c_err_init), -1);
-
- stimuli_src_out <= c_dp_sosi_rst;
- proc_common_wait_until_low(clk, rst);
- proc_common_wait_some_cycles(clk, 5);
-
- -- Generate c_nof_repeat packets
- FOR I IN 0 TO g_nof_repeat-1 LOOP
- -- Auto increment v_sosi field values for this packet
- v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
- v_sosi.sync := sel_a_b((UNSIGNED(v_sosi.bsn) MOD c_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
- v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
- v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w-1 DOWNTO 0)); -- wrap when >= 2**g_in_dat_w
- v_sosi.err := INCR_UVEC(v_sosi.err, 1);
-
- -- Send packet
- proc_dp_gen_block_data(g_in_dat_w, TO_UINT(v_sosi.data), g_pkt_len, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn, clk, stimuli_en, stimuli_src_in, stimuli_src_out);
-
- -- Insert optional gap between the packets
- proc_common_wait_some_cycles(clk, g_pkt_gap);
- END LOOP;
-
- -- Determine expected sosi field values after end of stimuli
- -- . e_qual
- v_sosi.bsn := STD_LOGIC_VECTOR( UNSIGNED(c_bsn_init) + g_nof_repeat-1);
- v_sosi.channel := TO_DP_CHANNEL(c_channel_init + g_nof_repeat-1);
- v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_repeat-1);
- -- . account for g_pkt_len
- v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len-1);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w-1 DOWNTO 0)); -- wrap when >= 2**g_in_dat_w
- expected_verify_snk_in <= v_sosi;
-
- -- Signal end of stimuli
- proc_common_wait_some_cycles(clk, 100); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
- proc_common_gen_pulse(clk, verify_done);
- proc_common_wait_some_cycles(clk, 50);
- tb_end <= '1';
- WAIT;
- END PROCESS;
-
-
- ------------------------------------------------------------------------------
- -- DATA VERIFICATION
- ------------------------------------------------------------------------------
-
-- Start verify after first valid, sop or eop
verify_en_valid <= '1' WHEN verify_snk_in.valid='1' AND rising_edge(clk);
verify_en_sop <= '1' WHEN verify_snk_in.sop='1' AND rising_edge(clk);
verify_en_eop <= '1' WHEN verify_snk_in.eop='1' AND rising_edge(clk);
-- Verify that the stimuli have been applied at all
- proc_dp_verify_value("verify_snk_in.valid", clk, verify_done, sl1, verify_en_valid);
- proc_dp_verify_value("verify_snk_in.sop", clk, verify_done, sl1, verify_en_sop);
- proc_dp_verify_value("verify_snk_in.eop", clk, verify_done, sl1, verify_en_eop);
- proc_dp_verify_value("verify_snk_in.data", e_equal, clk, verify_done, expected_verify_snk_in.data, verify_snk_in_data);
- --proc_dp_verify_value("verify_snk_in.bsn", e_equal, clk, verify_done, expected_verify_snk_in.bsn, verify_snk_in.bsn);
- --proc_dp_verify_value("verify_snk_in.channel", e_equal, clk, verify_done, expected_verify_snk_in.channel, verify_snk_in.channel);
- --proc_dp_verify_value("verify_snk_in.err", e_equal, clk, verify_done, expected_verify_snk_in.err, verify_snk_in.err);
+ proc_dp_verify_value("verify_snk_in.valid", clk, verify_last, sl1, verify_en_valid);
+ proc_dp_verify_value("verify_snk_in.sop", clk, verify_last, sl1, verify_en_sop);
+ proc_dp_verify_value("verify_snk_in.eop", clk, verify_last, sl1, verify_en_eop);
+ proc_dp_verify_value("verify_snk_in.data", e_equal, clk, verify_last, expected_verify_snk_in.data, verify_snk_in_data);
+ --proc_dp_verify_value("verify_snk_in.bsn", e_equal, clk, verify_last, expected_verify_snk_in.bsn, verify_snk_in.bsn);
+ --proc_dp_verify_value("verify_snk_in.channel", e_equal, clk, verify_last, expected_verify_snk_in.channel, verify_snk_in.channel);
+ --proc_dp_verify_value("verify_snk_in.err", e_equal, clk, verify_last, expected_verify_snk_in.err, verify_snk_in.err);
-- Verify that the output is incrementing data, like the input stimuli
proc_dp_verify_data("verify_snk_in.data", c_rl, c_data_max, c_unsigned_1, clk, verify_en_valid, verify_snk_out.ready, verify_snk_in.valid, verify_snk_in.data, prev_verify_snk_in.data);
--
GitLab