diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
index 2923acb0d078a19521a54cab116c2be09ae82fea..1c170f9929b0cbbe500fadd02e92e00b26131ab3 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
@@ -30,7 +30,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
     $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
     #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
index c6cc023e92db7fe5b85814f447e3e1729face519..1adf4b585e61f9e3515874bc4b14be306fa5d85f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
@@ -30,7 +30,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
     $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
     #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
index 4ca4e1ab6c759c667437a523addfc3caa4d6fe08..77af8a99ea421b76bf937cc4761d2963d3d5c52b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
@@ -36,10 +36,7 @@ ENTITY unb1_test_all IS
     g_sim_node_nr : NATURAL := 0;  -- FN0
     g_stamp_date  : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time  : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
-    g_stamp_svn   : NATURAL := 0;  -- SVN revision    -- set by QSF
-    g_nof_MB      : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
-    g_use_MB_I    : NATURAL := 0;                     -- 1: use MB_I  0: do not use
-    g_use_MB_II   : NATURAL := 0
+    g_stamp_svn   : NATURAL := 0   -- SVN revision    -- set by QSF
   );
   PORT (
     -- GENERAL
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
index efefaed8792447c9a6883660674946321ef6e855..14419b4fa7c29176f478dd29dbdb6aa31a55133f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
@@ -30,7 +30,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
     $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
     #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
 
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
index 3388ac2b8c606b8585e901ab3757f755ade771d7..b7c9b59fdaaac315214b3236180b83830ad6750b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
@@ -36,10 +36,7 @@ ENTITY unb1_test_ddr IS
     g_sim_node_nr : NATURAL := 0;  -- FN0
     g_stamp_date  : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time  : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
-    g_stamp_svn   : NATURAL := 0;  -- SVN revision    -- set by QSF
-    g_nof_MB      : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
-    g_use_MB_I    : NATURAL := 0;                     -- 1: use MB_I  0: do not use
-    g_use_MB_II   : NATURAL := 0
+    g_stamp_svn   : NATURAL := 0   -- SVN revision    -- set by QSF
   );
   PORT (
     -- GENERAL
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 8993ec42e21a6da4f6e42f572f5487588e7fa7f2..8cc15d92f1063814de08d91b5ed43c593f6cc247 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -48,10 +48,7 @@ ENTITY unb1_test IS
     g_technology  : NATURAL := c_tech_stratixiv;
     g_stamp_date  : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time  : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
-    g_stamp_svn   : NATURAL := 0;  -- SVN revision    -- set by QSF
-    g_nof_MB      : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
-    g_use_MB_I    : NATURAL := 1;                     -- 1: use MB_I  0: do not use
-    g_use_MB_II   : NATURAL := 0
+    g_stamp_svn   : NATURAL := 0   -- SVN revision    -- set by QSF
   );
   PORT (
     -- GENERAL
@@ -76,17 +73,17 @@ ENTITY unb1_test IS
     ETH_SGOUT    : OUT   STD_LOGIC;
 
     -- Transceiver clocks
-    SA_CLK       : IN  STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+    SA_CLK       : IN  STD_LOGIC := '0'; -- SerDes Clock BN-BI / SI_FN
 
     -- Serial I/O
     SI_FN_0_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-    SI_FN_0_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    SI_FN_0_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
     SI_FN_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-    SI_FN_1_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    SI_FN_1_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
     SI_FN_2_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-    SI_FN_2_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    SI_FN_2_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
     SI_FN_3_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-    SI_FN_3_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    SI_FN_3_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
 
     SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
     SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
@@ -95,13 +92,13 @@ ENTITY unb1_test IS
     SI_FN_RSTN    : OUT   STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
 
     BN_BI_0_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-    BN_BI_0_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    BN_BI_0_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
     BN_BI_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-    BN_BI_1_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    BN_BI_1_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
     BN_BI_2_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-    BN_BI_2_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    BN_BI_2_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
     BN_BI_3_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-    BN_BI_3_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    BN_BI_3_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
 
     -- SO-DIMM Memory Bank I
     MB_I_IN       : IN    t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
@@ -122,24 +119,35 @@ ARCHITECTURE str OF unb1_test IS
   -- Firmware version x.y
   CONSTANT c_fw_version             : t_unb1_board_fw_version := (1, 2);
 
-  CONSTANT c_use_front              : BOOLEAN := TRUE;  -- connect SI_FN_[0..2]
+  CONSTANT c_use_front              : BOOLEAN := g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
   CONSTANT c_use_back               : BOOLEAN := FALSE; -- however SI_FN_[0..2] do connect to copper connectors of single board unb
 
   -- Revision controlled constants
-  CONSTANT c_use_1GbE               : BOOLEAN := g_design_name = "unb1_test_1GbE" OR g_design_name = "unb1_test_10GbE";
-  CONSTANT c_use_10GbE              : BOOLEAN := g_design_name = "unb1_test_10GbE";
+  CONSTANT c_use_1GbE               : BOOLEAN := g_design_name="unb1_test_1GbE"  OR g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
+  CONSTANT c_use_10GbE              : BOOLEAN := g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
+  CONSTANT c_use_ddr                : BOOLEAN := g_design_name="unb1_test_ddr"   OR g_design_name="unb1_test_all";
+
+
+  -- max useful peripherals (FIXME read these constants from board lib)
+ -- CONSTANT c_max_nof_
+
+
+  -- ddr
+  CONSTANT c_nof_MB                 : NATURAL := c_unb1_board_nof_ddr3;  -- Fixed control infrastructure for 2 modules per FPGA
+  CONSTANT c_use_MB_I               : NATURAL := sel_a_b(c_use_ddr,1,0); -- 1: use MB_I  0: do not use
+  CONSTANT c_use_MB_II              : NATURAL := 0;
 
   CONSTANT c_use_phy                : t_c_unb1_board_use_phy  := (sel_a_b(c_use_1GbE, 1, 0), 
-                                                                  sel_a_b(c_use_front, 1, 0), 
+                                                                  sel_a_b(c_use_front,1, 0), 
                                                                   0, 
                                                                   sel_a_b(c_use_back, 1, 0), 
-                                                                  sel_a_b(g_use_MB_I, 1, 0), 
-                                                                  sel_a_b(g_use_MB_II,1, 0), 
+                                                                  sel_a_b(c_use_MB_I, 1, 0), 
+                                                                  sel_a_b(c_use_MB_II,1, 0), 
                                                                   0, 1);
 
   CONSTANT c_nof_streams_10GbE          : NATURAL := sel_a_b(c_use_10GbE,3,0);
   CONSTANT c_nof_streams_1GbE           : NATURAL := sel_a_b(c_use_1GbE,1,0);
-  CONSTANT c_nof_streams_ddr            : NATURAL := sel_a_b(g_use_MB_I,sel_a_b(g_use_MB_II,2,1),0);
+  CONSTANT c_nof_streams_ddr            : NATURAL := sel_a_b(c_use_MB_I,sel_a_b(c_use_MB_II,2,1),0);
   CONSTANT c_nof_streams                : NATURAL := c_nof_streams_1GbE + c_nof_streams_10GbE + c_nof_streams_ddr;
   CONSTANT c_nof_streams_eth            : NATURAL := c_nof_streams_1GbE + c_nof_streams_10GbE;
   CONSTANT c_data_w_32                  : NATURAL := c_eth_data_w;   --  1GbE
@@ -468,9 +476,9 @@ BEGIN
     g_sim               => g_sim,
     g_sim_unb_nr        => g_sim_unb_nr,
     g_sim_node_nr       => g_sim_node_nr,
-    g_nof_streams_1GbE  => c_nof_streams_1GbE,
-    g_nof_streams_10GbE => c_nof_streams_10GbE,
-    g_nof_streams_ddr   => c_nof_streams_ddr,
+    g_nof_streams_1GbE  => 1,--c_nof_streams_1GbE,
+    g_nof_streams_10GbE => 3,--c_nof_streams_10GbE,
+    g_nof_streams_ddr   => 1,--c_nof_streams_ddr,
     g_bg_block_size     => c_bg_block_size
    )
   PORT MAP(  
@@ -598,110 +606,114 @@ BEGIN
   );
 
 
-  u_udp_stream_1GbE : ENTITY work.udp_stream
-  GENERIC MAP (
-    g_sim                       => g_sim,
-    g_nof_streams               => c_nof_streams_1GbE,
-    g_data_w                    => c_data_w_32,
-    g_bg_block_size             => c_bg_block_size,
-    g_bg_gapsize                => c_bg_gapsize,
-    g_bg_blocks_per_sync        => c_bg_blocks_per_sync,
-    g_def_block_size            => c_def_1GbE_block_size,
-    g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
-    g_remove_crc                => TRUE
-  )
-  PORT MAP (
-    mm_rst                         => mm_rst,
-    mm_clk                         => mm_clk,
-
-    dp_rst                         => dp_rst,
-    dp_clk                         => dp_clk,
-
-    ID                             => ID,
-
-    -- blockgen MM
-    reg_diag_bg_mosi               => reg_diag_bg_1GbE_mosi,
-    reg_diag_bg_miso               => reg_diag_bg_1GbE_miso,
-    ram_diag_bg_mosi               => ram_diag_bg_1GbE_mosi,
-    ram_diag_bg_miso               => ram_diag_bg_1GbE_miso,
-
-    -- dp_offload_tx
-    reg_dp_offload_tx_mosi         => reg_dp_offload_tx_1GbE_mosi,
-    reg_dp_offload_tx_miso         => reg_dp_offload_tx_1GbE_miso,
-    reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
-    reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
-    dp_offload_tx_src_out_arr      => dp_offload_tx_1GbE_src_out_arr,
-    dp_offload_tx_src_in_arr       => dp_offload_tx_1GbE_src_in_arr,
-
-    -- dp_offload_rx
-    reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
-    reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-    dp_offload_rx_snk_in_arr       => dp_offload_rx_1GbE_snk_in_arr,
-    dp_offload_rx_snk_out_arr      => dp_offload_rx_1GbE_snk_out_arr,
-
-    -- bsn
-    reg_bsn_monitor_mosi           => reg_bsn_monitor_1GbE_mosi,
-    reg_bsn_monitor_miso           => reg_bsn_monitor_1GbE_miso,
-
-    -- databuffer
-    reg_diag_data_buf_mosi         => reg_diag_data_buf_1GbE_mosi,
-    reg_diag_data_buf_miso         => reg_diag_data_buf_1GbE_miso,
-    ram_diag_data_buf_mosi         => ram_diag_data_buf_1GbE_mosi,
-    ram_diag_data_buf_miso         => ram_diag_data_buf_1GbE_miso
-  );
-
-
-  u_udp_stream_10GbE : ENTITY work.udp_stream
-  GENERIC MAP (
-    g_sim                       => g_sim,
-    g_nof_streams               => c_nof_streams_10GbE,
-    g_data_w                    => c_data_w_64,
-    g_bg_block_size             => c_bg_block_size,
-    g_bg_gapsize                => c_bg_gapsize,
-    g_bg_blocks_per_sync        => c_bg_blocks_per_sync,
-    g_def_block_size            => c_def_10GbE_block_size,
-    g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
-    g_remove_crc                => FALSE
-  )
-  PORT MAP (
-    mm_rst                         => mm_rst,
-    mm_clk                         => mm_clk,
-
-    dp_rst                         => dp_rst,
-    dp_clk                         => dp_clk,
-
-    ID                             => ID,
-
-    -- blockgen mm
-    reg_diag_bg_mosi               => reg_diag_bg_10GbE_mosi,
-    reg_diag_bg_miso               => reg_diag_bg_10GbE_miso,
-    ram_diag_bg_mosi               => ram_diag_bg_10GbE_mosi,
-    ram_diag_bg_miso               => ram_diag_bg_10GbE_miso,
-
-    -- dp_offload_tx
-    reg_dp_offload_tx_mosi         => reg_dp_offload_tx_10GbE_mosi,
-    reg_dp_offload_tx_miso         => reg_dp_offload_tx_10GbE_miso,
-    reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
-    reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
-    dp_offload_tx_src_out_arr      => dp_offload_tx_10GbE_src_out_arr,
-    dp_offload_tx_src_in_arr       => dp_offload_tx_10GbE_src_in_arr,
-
-    -- dp_offload_rx
-    reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
-    reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
-    dp_offload_rx_snk_in_arr       => dp_offload_rx_10GbE_snk_in_arr,
-    dp_offload_rx_snk_out_arr      => dp_offload_rx_10GbE_snk_out_arr,
+  gen_udp_stream_1GbE : IF c_use_1GbE = TRUE GENERATE
+    u_udp_stream_1GbE : ENTITY work.udp_stream
+    GENERIC MAP (
+      g_sim                       => g_sim,
+      g_nof_streams               => c_nof_streams_1GbE,
+      g_data_w                    => c_data_w_32,
+      g_bg_block_size             => c_bg_block_size,
+      g_bg_gapsize                => c_bg_gapsize,
+      g_bg_blocks_per_sync        => c_bg_blocks_per_sync,
+      g_def_block_size            => c_def_1GbE_block_size,
+      g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+      g_remove_crc                => TRUE
+    )
+    PORT MAP (
+      mm_rst                         => mm_rst,
+      mm_clk                         => mm_clk,
+  
+      dp_rst                         => dp_rst,
+      dp_clk                         => dp_clk,
+  
+      ID                             => ID,
+  
+      -- blockgen MM
+      reg_diag_bg_mosi               => reg_diag_bg_1GbE_mosi,
+      reg_diag_bg_miso               => reg_diag_bg_1GbE_miso,
+      ram_diag_bg_mosi               => ram_diag_bg_1GbE_mosi,
+      ram_diag_bg_miso               => ram_diag_bg_1GbE_miso,
+  
+      -- dp_offload_tx
+      reg_dp_offload_tx_mosi         => reg_dp_offload_tx_1GbE_mosi,
+      reg_dp_offload_tx_miso         => reg_dp_offload_tx_1GbE_miso,
+      reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+      reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+      dp_offload_tx_src_out_arr      => dp_offload_tx_1GbE_src_out_arr,
+      dp_offload_tx_src_in_arr       => dp_offload_tx_1GbE_src_in_arr,
+  
+      -- dp_offload_rx
+      reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+      reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+      dp_offload_rx_snk_in_arr       => dp_offload_rx_1GbE_snk_in_arr,
+      dp_offload_rx_snk_out_arr      => dp_offload_rx_1GbE_snk_out_arr,
+  
+      -- bsn
+      reg_bsn_monitor_mosi           => reg_bsn_monitor_1GbE_mosi,
+      reg_bsn_monitor_miso           => reg_bsn_monitor_1GbE_miso,
+  
+      -- databuffer
+      reg_diag_data_buf_mosi         => reg_diag_data_buf_1GbE_mosi,
+      reg_diag_data_buf_miso         => reg_diag_data_buf_1GbE_miso,
+      ram_diag_data_buf_mosi         => ram_diag_data_buf_1GbE_mosi,
+      ram_diag_data_buf_miso         => ram_diag_data_buf_1GbE_miso
+    );
+  END GENERATE;
 
-    -- bsn
-    reg_bsn_monitor_mosi           => reg_bsn_monitor_10GbE_mosi,
-    reg_bsn_monitor_miso           => reg_bsn_monitor_10GbE_miso,
 
-    -- databuffer
-    reg_diag_data_buf_mosi         => reg_diag_data_buf_10GbE_mosi,
-    reg_diag_data_buf_miso         => reg_diag_data_buf_10GbE_miso,
-    ram_diag_data_buf_mosi         => ram_diag_data_buf_10GbE_mosi,
-    ram_diag_data_buf_miso         => ram_diag_data_buf_10GbE_miso
-  );
+  gen_udp_stream_10GbE : IF c_use_10GbE = TRUE GENERATE
+    u_udp_stream_10GbE : ENTITY work.udp_stream
+    GENERIC MAP (
+      g_sim                       => g_sim,
+      g_nof_streams               => c_nof_streams_10GbE,
+      g_data_w                    => c_data_w_64,
+      g_bg_block_size             => c_bg_block_size,
+      g_bg_gapsize                => c_bg_gapsize,
+      g_bg_blocks_per_sync        => c_bg_blocks_per_sync,
+      g_def_block_size            => c_def_10GbE_block_size,
+      g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+      g_remove_crc                => FALSE
+    )
+    PORT MAP (
+      mm_rst                         => mm_rst,
+      mm_clk                         => mm_clk,
+  
+      dp_rst                         => dp_rst,
+      dp_clk                         => dp_clk,
+  
+      ID                             => ID,
+  
+      -- blockgen mm
+      reg_diag_bg_mosi               => reg_diag_bg_10GbE_mosi,
+      reg_diag_bg_miso               => reg_diag_bg_10GbE_miso,
+      ram_diag_bg_mosi               => ram_diag_bg_10GbE_mosi,
+      ram_diag_bg_miso               => ram_diag_bg_10GbE_miso,
+  
+      -- dp_offload_tx
+      reg_dp_offload_tx_mosi         => reg_dp_offload_tx_10GbE_mosi,
+      reg_dp_offload_tx_miso         => reg_dp_offload_tx_10GbE_miso,
+      reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
+      reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
+      dp_offload_tx_src_out_arr      => dp_offload_tx_10GbE_src_out_arr,
+      dp_offload_tx_src_in_arr       => dp_offload_tx_10GbE_src_in_arr,
+  
+      -- dp_offload_rx
+      reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
+      reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
+      dp_offload_rx_snk_in_arr       => dp_offload_rx_10GbE_snk_in_arr,
+      dp_offload_rx_snk_out_arr      => dp_offload_rx_10GbE_snk_out_arr,
+  
+      -- bsn
+      reg_bsn_monitor_mosi           => reg_bsn_monitor_10GbE_mosi,
+      reg_bsn_monitor_miso           => reg_bsn_monitor_10GbE_miso,
+  
+      -- databuffer
+      reg_diag_data_buf_mosi         => reg_diag_data_buf_10GbE_mosi,
+      reg_diag_data_buf_miso         => reg_diag_data_buf_10GbE_miso,
+      ram_diag_data_buf_mosi         => ram_diag_data_buf_10GbE_mosi,
+      ram_diag_data_buf_miso         => ram_diag_data_buf_10GbE_miso
+    );
+  END GENERATE;
 
 
 
@@ -814,55 +826,56 @@ BEGIN
   END GENERATE;
 
 
-  u_ddr_stream : ENTITY work.ddr_stream
-  GENERIC MAP (
-    g_sim                       => g_sim,
-    g_technology                => g_technology,
-    g_nof_streams               => c_nof_streams_ddr,
-    g_data_w                    => c_data_w_32,
-    g_bg_block_size             => c_bg_block_size,
-    g_bg_gapsize                => c_bg_gapsize,
-    g_bg_blocks_per_sync        => c_bg_blocks_per_sync,
-    g_tech_ddr                  => c_ddr_master,
-    g_reorder_seq               => c_reorder_seq_same,
-    g_ena_pre_transp            => FALSE
-  )
-  PORT MAP (
-    mm_rst                         => mm_rst,
-    mm_clk                         => mm_clk,
-
-    dp_rst                         => dp_rst,
-    dp_clk                         => dp_clk,
-
-    -- blockgen mm
-    reg_diag_bg_mosi               => reg_diag_bg_ddr_mosi,
-    reg_diag_bg_miso               => reg_diag_bg_ddr_miso,
-    ram_diag_bg_mosi               => ram_diag_bg_ddr_mosi,
-    ram_diag_bg_miso               => ram_diag_bg_ddr_miso,
-
-    -- bsn
-    reg_bsn_monitor_mosi           => reg_bsn_monitor_ddr_mosi,
-    reg_bsn_monitor_miso           => reg_bsn_monitor_ddr_miso,
-
-    -- databuffer
-    reg_diag_data_buf_mosi         => reg_diag_data_buf_ddr_mosi,
-    reg_diag_data_buf_miso         => reg_diag_data_buf_ddr_miso,
-    ram_diag_data_buf_mosi         => ram_diag_data_buf_ddr_mosi,
-    ram_diag_data_buf_miso         => ram_diag_data_buf_ddr_miso,
-
-    -- IO DDR register map        
-    reg_io_ddr_mosi                => reg_io_ddr_mosi,
-    reg_io_ddr_miso                => reg_io_ddr_miso,
-
-    -- Reorder transpose          
-    ram_ss_ss_transp_mosi          => ram_ss_ss_transp_mosi,
-    ram_ss_ss_transp_miso          => ram_ss_ss_transp_miso,
-
-    -- SO-DIMM Memory Bank I
-    MB_I_IN                        => MB_I_IN,
-    MB_I_IO                        => MB_I_IO,
-    MB_I_OU                        => MB_I_OU
-  );
-
+  gen_ddr_stream : IF c_use_ddr = TRUE GENERATE
+    u_ddr_stream : ENTITY work.ddr_stream
+    GENERIC MAP (
+      g_sim                       => g_sim,
+      g_technology                => g_technology,
+      g_nof_streams               => c_nof_streams_ddr,
+      g_data_w                    => c_data_w_32,
+      g_bg_block_size             => c_bg_block_size,
+      g_bg_gapsize                => c_bg_gapsize,
+      g_bg_blocks_per_sync        => c_bg_blocks_per_sync,
+      g_tech_ddr                  => c_ddr_master,
+      g_reorder_seq               => c_reorder_seq_same,
+      g_ena_pre_transp            => FALSE
+    )
+    PORT MAP (
+      mm_rst                         => mm_rst,
+      mm_clk                         => mm_clk,
+  
+      dp_rst                         => dp_rst,
+      dp_clk                         => dp_clk,
+  
+      -- blockgen mm
+      reg_diag_bg_mosi               => reg_diag_bg_ddr_mosi,
+      reg_diag_bg_miso               => reg_diag_bg_ddr_miso,
+      ram_diag_bg_mosi               => ram_diag_bg_ddr_mosi,
+      ram_diag_bg_miso               => ram_diag_bg_ddr_miso,
+  
+      -- bsn
+      reg_bsn_monitor_mosi           => reg_bsn_monitor_ddr_mosi,
+      reg_bsn_monitor_miso           => reg_bsn_monitor_ddr_miso,
+  
+      -- databuffer
+      reg_diag_data_buf_mosi         => reg_diag_data_buf_ddr_mosi,
+      reg_diag_data_buf_miso         => reg_diag_data_buf_ddr_miso,
+      ram_diag_data_buf_mosi         => ram_diag_data_buf_ddr_mosi,
+      ram_diag_data_buf_miso         => ram_diag_data_buf_ddr_miso,
+  
+      -- IO DDR register map        
+      reg_io_ddr_mosi                => reg_io_ddr_mosi,
+      reg_io_ddr_miso                => reg_io_ddr_miso,
+  
+      -- Reorder transpose          
+      ram_ss_ss_transp_mosi          => ram_ss_ss_transp_mosi,
+      ram_ss_ss_transp_miso          => ram_ss_ss_transp_miso,
+  
+      -- SO-DIMM Memory Bank I
+      MB_I_IN                        => MB_I_IN,
+      MB_I_IO                        => MB_I_IO,
+      MB_I_OU                        => MB_I_OU
+    );
+  END GENERATE;
 END str;