diff --git a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
index 9338804f348c41bb87ec38be1e42f20ca05332b0..e46bcffc92296cbd5a7655ccdc339cd618305e70 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
@@ -48,6 +48,7 @@ END tb_diag_block_gen;
ARCHITECTURE tb OF tb_diag_block_gen IS
CONSTANT clk_period : TIME := 10 ns;
+ CONSTANT c_timeout : NATURAL := 1000;
-- Default settings
CONSTANT c_buf : t_c_mem := (latency => 1,
@@ -62,6 +63,7 @@ ARCHITECTURE tb OF tb_diag_block_gen IS
CONSTANT c_cntr_incr : INTEGER := 1;
CONSTANT c_cntr_arr : t_slv_32_arr(c_buf.nof_dat-1 DOWNTO 0) := flip(array_init(c_cntr_init, c_buf.nof_dat, c_cntr_incr));
+ -- Default BG control
CONSTANT c_bg_ctrl : t_diag_block_gen := ( '0',
'0',
TO_UVEC(96, c_diag_bg_samples_per_packet_w),
@@ -70,11 +72,26 @@ ARCHITECTURE tb OF tb_diag_block_gen IS
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
TO_UVEC(95, c_diag_bg_mem_high_adrs_w),
TO_UVEC(42, c_diag_bg_bsn_init_w));
-
- CONSTANT c_alternative_samples_per_packet : NATURAL := c_buf.nof_dat;
+ CONSTANT c_bg_period : NATURAL := TO_UINT(c_bg_ctrl.samples_per_packet) + TO_UINT(c_bg_ctrl.gapsize);
+
+ -- Some alternative BG control settings
+ CONSTANT c_more_samples_per_packet : NATURAL := c_buf.nof_dat;
+ CONSTANT c_less_samples_per_packet : NATURAL := 5;
CONSTANT c_alternative_mem_high_adrs : NATURAL := 64;
CONSTANT c_alternative_data_gap : NATURAL := TO_UINT(c_bg_ctrl.mem_high_adrs)-c_alternative_mem_high_adrs;
+ -- Another BG control for verifying XON
+ CONSTANT c_bg_ctrl2 : t_diag_block_gen := ( '0',
+ '0',
+ TO_UVEC(17, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(10, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( 0, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(16, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
+
+ CONSTANT c_bg_period2 : NATURAL := TO_UINT(c_bg_ctrl2.samples_per_packet) + TO_UINT(c_bg_ctrl2.gapsize);
+
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
@@ -90,6 +107,7 @@ ARCHITECTURE tb OF tb_diag_block_gen IS
SIGNAL bg_ctrl : t_diag_block_gen;
+ SIGNAL out_siso : t_dp_siso;
SIGNAL out_sosi : t_dp_sosi;
SIGNAL prev_out_sosi : t_dp_sosi;
SIGNAL hold_sop : STD_LOGIC;
@@ -99,10 +117,12 @@ ARCHITECTURE tb OF tb_diag_block_gen IS
BEGIN
rst <= '1', '0' AFTER clk_period/10;
+
clk <= NOT clk OR tb_end AFTER clk_period/2;
p_stimuli : PROCESS
BEGIN
+ out_siso <= c_dp_siso_rdy;
bg_ctrl <= c_bg_ctrl;
proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
proc_common_wait_some_cycles(clk, 10);
@@ -137,22 +157,47 @@ BEGIN
bg_ctrl.enable <= '0';
proc_common_wait_some_cycles(clk, 100);
bg_ctrl <= c_bg_ctrl;
- bg_ctrl.mem_high_adrs <= TO_UVEC(c_alternative_mem_high_adrs, c_diag_bg_mem_high_adrs_w);
bg_ctrl.enable <= '1';
proc_dp_verify_run_some_cycles(5, 1500, 0, clk, verify_en);
-- . change gapsize dynamically
- bg_ctrl.gapsize <= c_bg_ctrl.gapsize;
+ bg_ctrl.gapsize <= TO_UVEC(0, c_diag_bg_gapsize_w);
proc_dp_verify_run_some_cycles(0, 1500, 0, clk, verify_en);
+ bg_ctrl.gapsize <= c_bg_ctrl.gapsize;
+ proc_dp_verify_run_some_cycles(0, 1500, 0, clk, verify_en);
+
-- . change mem_high_adrs dynamically
- bg_ctrl.mem_high_adrs <= c_bg_ctrl.mem_high_adrs; -- increase, because decreasing could yield an verify data error
+ bg_ctrl.mem_high_adrs <= TO_UVEC(c_alternative_mem_high_adrs, c_diag_bg_mem_high_adrs_w);
+ proc_dp_verify_run_some_cycles(5, 1500, 0, clk, verify_en);
+
+ bg_ctrl.mem_high_adrs <= c_bg_ctrl.mem_high_adrs;
proc_dp_verify_run_some_cycles(0, 1500, 0, clk, verify_en);
-- . change samples_per_packet dynamically
- bg_ctrl.samples_per_packet <= TO_UVEC(c_alternative_samples_per_packet, c_diag_bg_samples_per_packet_w); -- increase, because decreasing could yield an verify data error
+ proc_common_wait_until_high(c_timeout, clk, out_sosi.sop);
+ proc_common_wait_some_cycles(clk, 10);
+ bg_ctrl.samples_per_packet <= TO_UVEC(c_more_samples_per_packet, c_diag_bg_samples_per_packet_w); -- increase
+ proc_dp_verify_run_some_cycles(0, 1500, 0, clk, verify_en);
+
+ -- . change samples_per_packet dynamically
+ proc_common_wait_until_high(c_timeout, clk, out_sosi.sop);
+ proc_common_wait_some_cycles(clk, c_less_samples_per_packet*2);
+ bg_ctrl.samples_per_packet <= TO_UVEC(c_less_samples_per_packet, c_diag_bg_samples_per_packet_w); -- decrease, could yield proc_dp_verify_block_size() error if it occurs during a packet
proc_dp_verify_run_some_cycles(0, 1500, 0, clk, verify_en);
+ -- Run with XON flow control (verified by proc_dp_verify_block_size)
+ bg_ctrl.enable <= '0';
+ proc_common_wait_some_cycles(clk, 100);
+ bg_ctrl <= c_bg_ctrl2;
+ bg_ctrl.enable <= '1';
+ FOR I IN 0 TO c_bg_period2*3 LOOP
+ out_siso <= c_dp_siso_rdy;
+ proc_common_wait_some_cycles(clk, c_bg_period2*3+1);
+ out_siso <= c_dp_siso_rst;
+ proc_common_wait_some_cycles(clk, c_bg_period2*3);
+ END LOOP;
+
-- End simulation
tb_end <= '1';
WAIT;
@@ -205,6 +250,7 @@ BEGIN
buf_rddat => bg_buf_miso.rddata(c_buf.dat_w-1 DOWNTO 0),
buf_rdval => bg_buf_miso.rdval,
ctrl => bg_ctrl,
+ out_siso => out_siso,
out_sosi => out_sosi
);