From 7e0ada9406c1a17cbcc784932ea0f0ad2d83fb82 Mon Sep 17 00:00:00 2001 From: Erik Kooistra <kooistra@astron.nl> Date: Thu, 20 Nov 2014 14:05:35 +0000 Subject: [PATCH] Created eth_10g to combine mac_10g and 10gbase_r. --- libraries/technology/eth_10g/hdllib.cfg | 23 +++ libraries/technology/eth_10g/tech_eth_10g.vhd | 160 ++++++++++++++++++ .../eth_10g/tech_eth_10g_arria10.vhd | 144 ++++++++++++++++ 3 files changed, 327 insertions(+) create mode 100644 libraries/technology/eth_10g/hdllib.cfg create mode 100644 libraries/technology/eth_10g/tech_eth_10g.vhd create mode 100644 libraries/technology/eth_10g/tech_eth_10g_arria10.vhd diff --git a/libraries/technology/eth_10g/hdllib.cfg b/libraries/technology/eth_10g/hdllib.cfg new file mode 100644 index 0000000000..291c984894 --- /dev/null +++ b/libraries/technology/eth_10g/hdllib.cfg @@ -0,0 +1,23 @@ +hdl_lib_name = tech_eth_10g +hdl_library_clause_name = tech_eth_10g_lib +hdl_lib_uses = technology tech_mac_10g tech_10gbase_r common dp +hdl_lib_technology = + +build_dir_sim = $HDL_BUILD_DIR +build_dir_synth = $HDL_BUILD_DIR + +synth_files = + #tech_eth_10g_stratixiv.vhd + tech_eth_10g_arria10.vhd + tech_eth_10g.vhd + +test_bench_files = + tb_tech_eth_10g.vhd + +modelsim_search_libraries = + altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver + altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip + +modelsim_copy_files = + #wave_tb_tech_eth_10gbase_r.do . + \ No newline at end of file diff --git a/libraries/technology/eth_10g/tech_eth_10g.vhd b/libraries/technology/eth_10g/tech_eth_10g.vhd new file mode 100644 index 0000000000..42ff9117be --- /dev/null +++ b/libraries/technology/eth_10g/tech_eth_10g.vhd @@ -0,0 +1,160 @@ +-------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +-------------------------------------------------------------------------------- + + +-- Purpose: Combine mac_10g and 10gbase_r +-- Description: +-- . For c_tech_arria10: +-- __________________ +-- | | +-- tx_snk --->|tech_ |---> tx_serial +-- rx_src <---|eth_10g_arria10 |<--- rx_serial +-- |________________| +-- | +-- | +-- mac_mm +-- + +LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_mac_10g_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE technology_lib.technology_pkg.ALL; +USE technology_lib.technology_select_pkg.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE common_lib.common_interface_layers_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; +USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL; + +ENTITY tech_eth_10g IS + GENERIC ( + g_technology : NATURAL := c_tech_select_default; + g_sim : BOOLEAN := FALSE; + g_nof_channels : NATURAL := 1; + g_pre_header_padding : BOOLEAN := FALSE + ); + PORT ( + -- Transceiver PLL reference clock + tr_ref_clk_156 : IN STD_LOGIC := '0'; -- 156.26 MHz for XAUI + tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R + + -- MM + mm_clk : IN STD_LOGIC; + mm_rst : IN STD_LOGIC; + + mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR) + mac_miso : OUT t_mem_miso; + + xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- XAUI + xaui_miso : OUT t_mem_miso; + + -- ST + tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data + tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0); + + rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data + rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0); + + -- XAUI + cal_rec_clk : IN STD_LOGIC := '0'; + + crc_rx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- crc = synchronous to Cal_Rec_Clk + crc_tx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); + + a_rx_channelaligned_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); + + xaui_rx_arr : IN t_xaui_arr(g_nof_channels-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0')); + xaui_tx_arr : OUT t_xaui_arr(g_nof_channels-1 DOWNTO 0); + + -- 10GBASE-R + clk_312 : IN STD_LOGiC := '0'; + clk_156 : IN STD_LOGiC := '0'; + rst_156 : IN STD_LOGiC := '0'; + + tx_serial_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); + rx_serial_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0') + ); +END tech_eth_10g; + + +ARCHITECTURE str OF tech_eth_10g IS + + -- MAG_10G control status registers + SIGNAL mac_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0); + SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0); + +BEGIN + + gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE + END GENERATE; + + gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE + u0 : ENTITY work.tech_eth_10g_arria10 + GENERIC MAP ( + g_sim => g_sim, + g_nof_channels => g_nof_channels, + g_pre_header_padding => g_pre_header_padding + ) + PORT MAP ( + -- Transceiver PLL reference clock + tr_ref_clk_644 => tr_ref_clk_644, + + -- MM + mm_clk => mm_clk, + mm_rst => mm_rst, + + mac_mosi_arr => mac_mosi_arr, + mac_miso_arr => mac_miso_arr, + + -- Clocks + clk_312 => clk_312, + clk_156 => clk_156, + rst_156 => rst_156, + + -- ST + tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ clk_156 + tx_snk_out_arr => tx_snk_out_arr, + + rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ clk_156 + rx_src_in_arr => rx_src_in_arr, + + -- Serial + tx_serial_arr => tx_serial_arr, + rx_serial_arr => rx_serial_arr + ); + END GENERATE; + + ----------------------------------------------------------------------------- + -- MM bus mux + ----------------------------------------------------------------------------- + u_common_mem_mux : ENTITY common_lib.common_mem_mux + GENERIC MAP ( + g_nof_mosi => g_nof_channels, + g_mult_addr_w => func_tech_mac_10g_csr_addr_w(g_technology) + ) + PORT MAP ( + mosi => mac_mosi, + miso => mac_miso, + mosi_arr => mac_mosi_arr, + miso_arr => mac_miso_arr + ); + +END str; diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd new file mode 100644 index 0000000000..e859ef8846 --- /dev/null +++ b/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd @@ -0,0 +1,144 @@ +-------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +-------------------------------------------------------------------------------- + + +-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10 +-- Description: +-- XGMII +-- _________ ____________ +-- | | | | +-- tx_snk --->|tech_ |-------|tech_ |---> tx_serial +-- rx_src <---|mac_10g| |10gbase_r |<--- rx_serial +-- |_______| |__________| +-- | +-- | +-- mac_mm +-- + +LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_10gbase_r_lib, tech_mac_10g_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE technology_lib.technology_pkg.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE common_lib.common_interface_layers_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; + +ENTITY tech_eth_10g_arria10 IS + GENERIC ( + g_sim : BOOLEAN := FALSE; + g_nof_channels : NATURAL := 1; + g_pre_header_padding : BOOLEAN := FALSE + ); + PORT ( + -- Transceiver PLL reference clock + tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R + + -- MM + mm_clk : IN STD_LOGIC; + mm_rst : IN STD_LOGIC; + + mac_mosi_arr : IN t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0); -- MAG_10G (CSR) + mac_miso_arr : OUT t_mem_miso_arr(g_nof_channels-1 DOWNTO 0); + + -- Clocks + clk_312 : IN STD_LOGIC := '0'; + clk_156 : IN STD_LOGIC := '0'; + rst_156 : IN STD_LOGIC := '0'; + + -- ST + tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156 + tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0); + + rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156 + rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0); + + -- Serial + tx_serial_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); + rx_serial_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0') + ); +END tech_eth_10g_arria10; + + +ARCHITECTURE str OF tech_eth_10g_arria10 IS + + -- XGMII + SIGNAL xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit + SIGNAL xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit + +BEGIN + + gen_mac : FOR I IN 0 TO g_nof_channels-1 GENERATE + u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g + GENERIC MAP ( + g_technology => c_tech_arria10, + g_pre_header_padding => g_pre_header_padding + ) + PORT MAP ( + -- MM + mm_clk => mm_clk, + mm_rst => mm_rst, + csr_mosi => mac_mosi_arr(I), + csr_miso => mac_miso_arr(I), + + -- ST + tx_clk_312 => clk_312, + tx_clk_156 => clk_156, + tx_rst => rst_156, + tx_snk_in => tx_snk_in_arr(I), -- 64 bit data + tx_snk_out => tx_snk_out_arr(I), + + rx_clk_312 => clk_312, + rx_clk_156 => clk_156, + rx_rst => rst_156, + rx_src_out => rx_src_out_arr(I), -- 64 bit data + rx_src_in => rx_src_in_arr(I), + + -- XGMII + xgmii_tx_data => xgmii_tx_dc_arr(I), + xgmii_rx_data => xgmii_rx_dc_arr(I) + ); + END GENERATE; + + u_tech_10gbase_r: ENTITY tech_10gbase_r_lib.tech_10gbase_r + GENERIC MAP ( + g_technology => c_tech_arria10, + g_sim => g_sim, + g_nof_channels => g_nof_channels + ) + PORT MAP ( + -- Transceiver PLL reference clock + tr_ref_clk_644 => tr_ref_clk_644, + + -- XGMII clocks + clk_156 => clk_156, + rst_156 => rst_156, + + -- XGMII interface + xgmii_tx_dc_arr => xgmii_tx_dc_arr, + xgmii_rx_dc_arr => xgmii_rx_dc_arr, + + -- PHY serial IO + tx_serial_arr => tx_serial_arr, + rx_serial_arr => rx_serial_arr + ); + +END str; -- GitLab