diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index b3b2306413b6652255d06b9cfb92a12b78115698..b98c64e0f13512fafefb82de46b1bee050aee073 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -1,12 +1,19 @@
hdl_lib_name = tech_10gbase_r
hdl_library_clause_name = tech_10gbase_r_lib
-hdl_lib_uses = technology tech_pll ip_arria10_phy_10gbase_r ip_arria10_transceiver_pll_10g ip_arria10_transceiver_reset_controller_1 common
+hdl_lib_uses = technology
+ tech_pll
+ ip_arria10_phy_10gbase_r
+ ip_arria10_transceiver_pll_10g
+ ip_arria10_transceiver_reset_controller_1
+ tech_transceiver
+ common
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
+ sim_10gbase_r.vhd
tech_10gbase_r_component_pkg.vhd
tech_10gbase_r_arria10.vhd
tech_10gbase_r.vhd
diff --git a/libraries/technology/10gbase_r/sim_10gbase_r.vhd b/libraries/technology/10gbase_r/sim_10gbase_r.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6c6831aaab690102056faf38621db7f9d6cffcbe
--- /dev/null
+++ b/libraries/technology/10gbase_r/sim_10gbase_r.vhd
@@ -0,0 +1,143 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Purpose : Fast simulation model for 10G XGMII over 1 lane
+-- Description :
+-- Remark:
+-- . The sim_10gbase_r has the same entity ports and generics as tech_10gbase_r
+-- so that it can directly be mapped in tech_10gbase_r.
+-- . The model uses 10/8 overhead to transport the control signalling. Therefore
+-- the line rate becomes 12.5 Gbps instead of 10.3125 M for the technology.
+
+LIBRARY IEEE, common_lib, tech_transceiver_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+
+ENTITY sim_10gbase_r IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_nof_channels : NATURAL := 1
+ );
+ PORT (
+ -- Transceiver ATX PLL reference clock
+ tr_ref_clk_644 : IN STD_LOGIC; -- 644.531250 MHz
+
+ -- XGMII clocks
+ clk_156 : IN STD_LOGIC; -- 156.25 MHz
+ rst_156 : IN STD_LOGIC;
+
+ -- XGMII interface
+ xgmii_tx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- can be used for xon flow control
+ xgmii_rx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- typically leave not connected
+ xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+ xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+
+ -- PHY serial IO
+ tx_serial_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ rx_serial_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+END sim_10gbase_r;
+
+
+ARCHITECTURE str OF sim_10gbase_r IS
+
+ CONSTANT c_serdes_data_w : NATURAL := c_xgmii_data_w; -- 64 b
+ CONSTANT c_serdes_ctrl_w : NATURAL := c_xgmii_ctrl_w; -- 8 b
+ CONSTANT c_serdes_line_rate : NATURAL := 12500; -- Mbps = 156.25 MHz * 10/8 (encoding) * 64b (data width)
+
+ -- XGMII control bits (one for each XGMII lane):
+ SIGNAL xgmii_tx_c_arr : t_xgmii_c_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL xgmii_rx_c_arr : t_xgmii_c_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- XGMII data
+ SIGNAL xgmii_tx_d_arr : t_xgmii_d_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL xgmii_rx_d_arr : t_xgmii_d_arr(g_nof_channels-1 DOWNTO 0);
+
+BEGIN
+
+ gen_nof_10gbase_r : FOR i IN g_nof_channels-1 DOWNTO 0 GENERATE
+
+ -- Rewire XGMII
+ xgmii_tx_d_arr(i) <= func_xgmii_d(xgmii_tx_dc_arr(i));
+ xgmii_tx_c_arr(i) <= func_xgmii_c(xgmii_tx_dc_arr(i));
+
+ xgmii_rx_dc_arr(i) <= func_xgmii_dc(xgmii_rx_d_arr(i), xgmii_rx_c_arr(i));
+
+ -- Model tx_ready
+ u_areset_tx_rdy : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '0',
+ g_delay_len => 40
+ )
+ PORT MAP(
+ clk => clk_156,
+ in_rst => '0',
+ out_rst => xgmii_tx_ready_arr(i)
+ );
+
+ -- Model rx_ready
+ u_areset_rx_rdy : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '0',
+ g_delay_len => 80
+ )
+ PORT MAP(
+ clk => clk_156,
+ in_rst => '0',
+ out_rst => xgmii_rx_ready_arr(i)
+ );
+
+ u_ser: ENTITY tech_transceiver_lib.sim_transceiver_serializer
+ GENERIC MAP (
+ g_data_w => c_serdes_data_w,
+ g_line_rate => c_serdes_line_rate
+ )
+ PORT MAP (
+ tr_clk => clk_156,
+ tr_rst => rst_156,
+
+ tx_in_data => xgmii_tx_d_arr(i),
+ tx_in_ctrl => xgmii_tx_c_arr(i),
+
+ tx_out => tx_serial_arr(i)
+ );
+
+ u_des: ENTITY tech_transceiver_lib.sim_transceiver_deserializer
+ GENERIC MAP (
+ g_data_w => c_serdes_data_w,
+ g_line_rate => c_serdes_line_rate
+ )
+ PORT MAP (
+ tr_clk => clk_156,
+ tr_rst => rst_156,
+
+ rx_out_data => xgmii_rx_d_arr(i),
+ rx_out_ctrl => xgmii_rx_c_arr(i),
+
+ rx_in => rx_serial_arr(i)
+ );
+
+ END GENERATE;
+
+END str;
+