diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd index 72f970100c9817e4b62249f01d82714b2c731a3f..52060a9656314303d8468e4503dd8434b601cdf7 100644 --- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd +++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd @@ -285,6 +285,8 @@ ARCHITECTURE str OF unb2_test IS SIGNAL i_QSFP_RX : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0); SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0); SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0); + SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0); + SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0); SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back0+g_nof_streams_back1-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back0+g_nof_streams_back1-1 DOWNTO 0); @@ -943,6 +945,15 @@ BEGIN i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+g_nof_streams_back0); END GENERATE; + + + + i_BCK_RX(0) <= BCK_RX(g_nof_streams_back0-1 downto 0); + i_BCK_RX(1) <= BCK_RX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0); + BCK_TX(g_nof_streams_back0-1 downto 0) <= i_BCK_TX(0); + BCK_TX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0) <= i_BCK_TX(1); + + u_back_io : ENTITY unb2_board_lib.unb2_board_back_io GENERIC MAP ( g_nof_back_bus => g_nof_back_bus @@ -953,10 +964,8 @@ BEGIN -- Serial I/O -- back transceivers - BCK_RX(0) => BCK_RX(g_nof_streams_back0-1 downto 0), - BCK_TX(0) => BCK_TX(g_nof_streams_back0-1 downto 0), - BCK_RX(1) => BCK_RX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0), - BCK_TX(1) => BCK_TX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0), + BCK_RX => i_BCK_RX, + BCK_TX => i_BCK_TX, BCK_SDA => BCK_SDA, BCK_SCL => BCK_SCL, diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd index c9b9f289a0e6b84afbadb736b5ff997e9e37bf6e..fb138bea34134e9dc28412b80c2b84427499929b 100644 --- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd +++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd @@ -114,6 +114,7 @@ ARCHITECTURE tb OF tb_unb2_test IS SIGNAL si_lpbk_6 : STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 DOWNTO 0); SIGNAL si_lpbk_7 : STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 DOWNTO 0); + SIGNAL si_lpbk_8 : STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 DOWNTO 0); -- Model I2C sensor slaves as on the UniBoard @@ -200,26 +201,25 @@ BEGIN -- Serial I/O QSFP_0_TX => si_lpbk_0, - QSFP_0_RX => si_lpbk_0 - -- QSFP_1_TX => si_lpbk_1, - -- QSFP_1_RX => si_lpbk_1, - -- QSFP_2_TX => si_lpbk_2, - -- QSFP_2_RX => si_lpbk_2, - -- QSFP_3_TX => si_lpbk_3, - -- QSFP_3_RX => si_lpbk_3, --- QSFP_4_TX => si_lpbk_4, --- QSFP_4_RX => si_lpbk_4, --- QSFP_5_TX => si_lpbk_5, --- QSFP_5_RX => si_lpbk_5, - --- RING_0_TX => si_lpbk_6, --- RING_0_RX => si_lpbk_6, --- RING_1_TX => si_lpbk_7, --- RING_1_RX => si_lpbk_7 - - - --BCK_TX => si_lpbk_1, - --BCK_RX => si_lpbk_1 + QSFP_0_RX => si_lpbk_0, + QSFP_1_TX => si_lpbk_1, + QSFP_1_RX => si_lpbk_1, + QSFP_2_TX => si_lpbk_2, + QSFP_2_RX => si_lpbk_2, + QSFP_3_TX => si_lpbk_3, + QSFP_3_RX => si_lpbk_3, + QSFP_4_TX => si_lpbk_4, + QSFP_4_RX => si_lpbk_4, + QSFP_5_TX => si_lpbk_5, + QSFP_5_RX => si_lpbk_5, + + RING_0_TX => si_lpbk_6, + RING_0_RX => si_lpbk_6, + RING_1_TX => si_lpbk_7, + RING_1_RX => si_lpbk_7, + + BCK_TX => si_lpbk_8, + BCK_RX => si_lpbk_8 ); ------------------------------------------------------------------------------