From 7c781f892b0f26d10bbf0fc6baf47c2ef58ee13e Mon Sep 17 00:00:00 2001 From: Erik Kooistra <kooistra@astron.nl> Date: Thu, 30 Oct 2014 15:44:28 +0000 Subject: [PATCH] Connect tx_clk_2x and rx_clk_2x. --- libraries/technology/mac_10g/tb_tech_mac_10g.vhd | 16 +++++++++++----- libraries/technology/mac_10g/tech_mac_10g.vhd | 6 ++++-- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g.vhd index 9d8b14fc54..1f85e4e564 100644 --- a/libraries/technology/mac_10g/tb_tech_mac_10g.vhd +++ b/libraries/technology/mac_10g/tb_tech_mac_10g.vhd @@ -39,6 +39,7 @@ USE common_lib.common_network_total_header_pkg.ALL; USE common_lib.tb_common_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL; USE technology_lib.technology_pkg.ALL; +USE technology_lib.technology_select_pkg.ALL; USE WORK.tech_mac_10g_pkg.ALL; USE WORK.tb_tech_mac_10g_pkg.ALL; @@ -46,8 +47,7 @@ USE WORK.tb_tech_mac_10g_pkg.ALL; ENTITY tb_tech_mac_10g IS -- Test bench control parameters GENERIC ( - g_technology : NATURAL := c_tech_stratixiv; - --g_technology : NATURAL := c_tech_arria10; + g_technology : NATURAL := c_tech_select_default; -- g_data_type = c_tb_tech_mac_10g_data_type_symbols = 0 -- g_data_type = c_tb_tech_mac_10g_data_type_counter = 1 g_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols @@ -86,8 +86,10 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS SIGNAL tb_end : STD_LOGIC := '0'; SIGNAL mm_clk : STD_LOGIC := '0'; -- memory-mapped bus clock SIGNAL mm_rst : STD_LOGIC; -- reset synchronous with mm_clk + SIGNAL tx_ref_clk_2x : STD_LOGIC := '1'; -- mac_10g SIGNAL tx_ref_clk : STD_LOGIC := '0'; -- mac_10g reference clock SIGNAL tx_rst : STD_LOGIC; -- reset synchronous with tx_ref_clk + SIGNAL rx_phy_clk_2x : STD_LOGIC := '1'; -- mac_10g SIGNAL rx_phy_clk : STD_LOGIC := '0'; -- mac_10g rx clock from phy = tx_ref_clk in this tb SIGNAL rx_rst : STD_LOGIC; -- reset synchronous with rx_phy_clk = tx_ref_clk in this tb @@ -125,9 +127,11 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS BEGIN -- run 50 us - mm_clk <= NOT mm_clk AFTER mm_clk_period/2; -- MM clock - tx_ref_clk <= NOT tx_ref_clk AFTER tx_ref_clk_period/2; -- mac_10g tx reference clock - rx_phy_clk <= tx_ref_clk; -- use tx_ref_clk to model PHY + mm_clk <= NOT mm_clk AFTER mm_clk_period/2; -- MM clock + tx_ref_clk <= NOT tx_ref_clk AFTER tx_ref_clk_period/2; -- mac_10g tx reference clock + tx_ref_clk_2x <= NOT tx_ref_clk_2x AFTER tx_ref_clk_period/4; + rx_phy_clk <= tx_ref_clk; -- use tx_ref_clk to model PHY + rx_phy_clk_2x <= tx_ref_clk_2x; mm_rst <= '1', '0' AFTER mm_clk_period*10; tx_rst <= '1', '0' AFTER tx_ref_clk_period*10; @@ -260,11 +264,13 @@ BEGIN csr_miso => mm_miso, -- ST + tx_clk_2x => tx_ref_clk_2x, tx_clk => tx_ref_clk, -- 156.25 MHz local reference tx_rst => tx_rst, tx_snk_in => tx_sosi, -- 64 bit data tx_snk_out => tx_siso, + rx_clk_2x => rx_phy_clk_2x, rx_clk => rx_phy_clk, -- 156.25 MHz from rx phy rx_rst => rx_rst, rx_src_out => rx_sosi, -- 64 bit data diff --git a/libraries/technology/mac_10g/tech_mac_10g.vhd b/libraries/technology/mac_10g/tech_mac_10g.vhd index 5f783f2e6d..2e15e77901 100644 --- a/libraries/technology/mac_10g/tech_mac_10g.vhd +++ b/libraries/technology/mac_10g/tech_mac_10g.vhd @@ -80,11 +80,13 @@ ENTITY tech_mac_10g IS csr_miso : OUT t_mem_miso; -- ST + tx_clk_2x : IN STD_LOGIC := '0'; -- 312.5 MHz tx_clk : IN STD_LOGIC; -- 156.25 MHz local reference tx_rst : IN STD_LOGIC; tx_snk_in : IN t_dp_sosi; -- 64 bit data tx_snk_out : OUT t_dp_siso; + rx_clk_2x : IN STD_LOGIC := '0'; -- 312.5 MHz rx_clk : IN STD_LOGIC; -- 156.25 MHz from rx phy rx_rst : IN STD_LOGIC; rx_src_out : OUT t_dp_sosi; -- 64 bit data @@ -138,8 +140,8 @@ BEGIN gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE u0 : ENTITY work.tech_mac_10g_arria10 PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso, - tx_clk, tx_rst, tx_mac_snk_in, tx_mac_snk_out, - rx_clk, rx_rst, rx_mac_src_out, rx_mac_src_in, + tx_clk_2x, tx_clk, tx_rst, tx_mac_snk_in, tx_mac_snk_out, + rx_clk_2x, rx_clk, rx_rst, rx_mac_src_out, rx_mac_src_in, xgmii_tx_data, xgmii_rx_data); END GENERATE; -- GitLab