From 7c64cb1176ed00d9d59141e1277cbad959a7b1e6 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Fri, 14 Apr 2017 11:03:23 +0000
Subject: [PATCH] -Added fiber delay compensation: . dp_fifo_fill +
dp_fifo_monitor in top level; . Corresponding registers in MMM and SOPC; .
Verified OK in sim using tb_apertif_unb1_fn_beamformer_base: . No MM
control: dp_fifo_fill forwards data like old situation (fill level 0) .
MM control: dp_fifo_fill delays data with delay as specified using
dp_fifo_monitor control.
---
.../sopc_apertif_unb1_fn_beamformer.sopc | 226 ++++++++++--------
.../src/vhdl/apertif_unb1_fn_beamformer.vhd | 90 ++++++-
.../vhdl/mmm_apertif_unb1_fn_beamformer.vhd | 20 +-
3 files changed, 233 insertions(+), 103 deletions(-)
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc b/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc
index deb198425e..cb1dff8d42 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc
@@ -92,71 +92,68 @@
type = "String";
}
}
- element ram_diag_data_buffer_output.mem
+ element ram_dp_ram_from_mm.mem
{
datum baseAddress
{
- value = "864256";
+ value = "512";
type = "long";
}
}
- element reg_bsn_monitor_output.mem
+ element reg_dp_split.mem
{
datum baseAddress
{
- value = "768";
+ value = "1728";
type = "long";
}
}
- element reg_diagnostics_mesh.mem
+ element reg_tr_10GbE.mem
{
datum baseAddress
{
- value = "256";
+ value = "786432";
type = "long";
}
}
- element reg_dp_split.mem
+ element ram_bf_weights.mem
{
datum baseAddress
{
- value = "1728";
+ value = "262144";
type = "long";
}
}
- element ram_fringe_stop_step.mem
+ element reg_tr_nonbonded_mesh.mem
{
datum baseAddress
{
- value = "872448";
+ value = "1280";
type = "long";
}
}
- element ram_ss_ss_wide_transp.mem
+ element reg_wdi.mem
{
- datum baseAddress
+ datum _lockedAddress
{
- value = "819200";
- type = "long";
+ value = "1";
+ type = "boolean";
}
- }
- element reg_unb_sens.mem
- {
datum baseAddress
{
- value = "1632";
+ value = "12288";
type = "long";
}
}
- element ram_ss_ss_wide.mem
+ element reg_dp_xonoff_output.mem
{
datum baseAddress
{
- value = "524288";
+ value = "2008";
type = "long";
}
}
- element rom_system_info.mem
+ element pio_system_info.mem
{
datum _lockedAddress
{
@@ -165,52 +162,47 @@
}
datum baseAddress
{
- value = "4096";
+ value = "0";
type = "long";
}
}
- element reg_dp_xonoff_output.mem
+ element ram_diag_bg.mem
{
datum baseAddress
{
- value = "2008";
+ value = "32768";
type = "long";
}
}
- element pio_pps.mem
+ element ram_diag_data_buffer_terminal.mem
{
datum baseAddress
{
- value = "2000";
+ value = "65536";
type = "long";
}
}
- element reg_wdi.mem
+ element reg_unb_sens.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "12288";
+ value = "1632";
type = "long";
}
}
- element reg_st_sst.mem
+ element reg_dp_sync_checker.mem
{
datum baseAddress
{
- value = "1408";
+ value = "1968";
type = "long";
}
}
- element ram_bf_weights.mem
+ element reg_dp_ram_from_mm.mem
{
datum baseAddress
{
- value = "262144";
+ value = "1696";
type = "long";
}
}
@@ -222,19 +214,19 @@
type = "long";
}
}
- element reg_mdio_1.mem
+ element reg_diagnostics_mesh.mem
{
datum baseAddress
{
- value = "1824";
+ value = "256";
type = "long";
}
}
- element ram_dp_ram_from_mm.mem
+ element reg_mdio_1.mem
{
datum baseAddress
{
- value = "512";
+ value = "1824";
type = "long";
}
}
@@ -246,71 +238,79 @@
type = "long";
}
}
- element reg_mdio_0.mem
+ element reg_dp_pkt_merge.mem
{
datum baseAddress
{
- value = "1792";
+ value = "1760";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_dat.mem
+ element reg_dp_fifo_monitor.mem
{
datum baseAddress
{
- value = "1024";
+ value = "2048";
type = "long";
}
}
- element reg_diag_bg_output.mem
+ element reg_mdio_0.mem
{
datum baseAddress
{
- value = "1888";
+ value = "1792";
type = "long";
}
}
- element reg_dp_ram_from_mm.mem
+ element reg_mdio_2.mem
{
datum baseAddress
{
- value = "1696";
+ value = "1856";
type = "long";
}
}
- element reg_diag_data_buffer_terminal.mem
+ element ram_fringe_stop_step.mem
{
datum baseAddress
{
- value = "128";
+ value = "872448";
type = "long";
}
}
- element reg_dp_offload_tx.mem
+ element ram_diag_data_buffer_output.mem
{
datum baseAddress
{
- value = "1992";
+ value = "864256";
type = "long";
}
}
- element reg_diag_bg.mem
+ element reg_st_sst.mem
{
datum baseAddress
{
- value = "1664";
+ value = "1408";
type = "long";
}
}
- element reg_dp_pkt_merge.mem
+ element reg_dp_offload_tx.mem
{
datum baseAddress
{
- value = "1760";
+ value = "1992";
type = "long";
}
}
- element pio_system_info.mem
+ element reg_bsn_monitor_output.mem
+ {
+ datum baseAddress
+ {
+ value = "768";
+ type = "long";
+ }
+ }
+ element rom_system_info.mem
{
datum _lockedAddress
{
@@ -319,95 +319,103 @@
}
datum baseAddress
{
- value = "0";
+ value = "4096";
type = "long";
}
}
- element ram_diag_bg.mem
+ element reg_diag_data_buffer_output.mem
{
datum baseAddress
{
- value = "32768";
+ value = "1152";
type = "long";
}
}
- element ram_fringe_stop_offset.mem
+ element ram_st_sst.mem
{
datum baseAddress
{
- value = "868352";
+ value = "16384";
type = "long";
}
}
- element reg_diag_data_buffer_output.mem
+ element reg_dp_switch.mem
{
datum baseAddress
{
- value = "1152";
+ value = "2016";
type = "long";
}
}
- element reg_dp_switch.mem
+ element pio_pps.mem
{
datum baseAddress
{
- value = "2016";
+ value = "2000";
type = "long";
}
}
- element ram_diag_data_buffer_terminal.mem
+ element reg_diag_bg.mem
{
datum baseAddress
{
- value = "65536";
+ value = "1664";
type = "long";
}
}
- element ram_st_sst.mem
+ element reg_bsn_monitor.mem
{
datum baseAddress
{
- value = "16384";
+ value = "1344";
type = "long";
}
}
- element reg_mdio_2.mem
+ element reg_diag_bg_output.mem
{
datum baseAddress
{
- value = "1856";
+ value = "1888";
type = "long";
}
}
- element reg_tr_nonbonded_mesh.mem
+ element ram_fringe_stop_offset.mem
{
datum baseAddress
{
- value = "1280";
+ value = "868352";
type = "long";
}
}
- element reg_dp_sync_checker.mem
+ element ram_ss_ss_wide.mem
{
datum baseAddress
{
- value = "1968";
+ value = "524288";
type = "long";
}
}
- element reg_bsn_monitor.mem
+ element reg_dp_offload_tx_hdr_dat.mem
{
datum baseAddress
{
- value = "1344";
+ value = "1024";
type = "long";
}
}
- element reg_tr_10GbE.mem
+ element ram_ss_ss_wide_transp.mem
{
datum baseAddress
{
- value = "786432";
+ value = "819200";
+ type = "long";
+ }
+ }
+ element reg_diag_data_buffer_terminal.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
type = "long";
}
}
@@ -644,6 +652,14 @@
type = "int";
}
}
+ element reg_dp_fifo_monitor
+ {
+ datum _sortIndex
+ {
+ value = "47";
+ type = "int";
+ }
+ }
element reg_dp_offload_tx
{
datum _sortIndex
@@ -804,11 +820,16 @@
type = "long";
}
}
- element pio_debug_wave.s1
+ element pio_wdi.s1
{
+ datum _lockedAddress
+ {
+ value = "0";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "1936";
+ value = "1952";
type = "long";
}
}
@@ -825,16 +846,11 @@
type = "long";
}
}
- element pio_wdi.s1
+ element pio_debug_wave.s1
{
- datum _lockedAddress
- {
- value = "0";
- type = "boolean";
- }
datum baseAddress
{
- value = "1952";
+ value = "1936";
type = "long";
}
}
@@ -866,10 +882,10 @@
<parameter name="globalResetBus" value="true" />
<parameter name="hdlLanguage" value="VHDL" />
<parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName">apertif_unb1_fn_beamformer_trans.qpf</parameter>
+ <parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="true" />
- <parameter name="systemHash" value="-124834403840" />
- <parameter name="timeStamp" value="1484667397267" />
+ <parameter name="systemHash" value="-127538139982" />
+ <parameter name="timeStamp" value="1492163736749" />
<parameter name="useTestBenchNamingPattern" value="false" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" />
@@ -970,7 +986,7 @@
<parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_terminal.mem' start='0x80' end='0x100' /><slave name='reg_diagnostics_mesh.mem' start='0x100' end='0x200' /><slave name='ram_dp_ram_from_mm.mem' start='0x200' end='0x300' /><slave name='reg_bsn_monitor_output.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x400' end='0x480' /><slave name='reg_diag_data_buffer_output.mem' start='0x480' end='0x500' /><slave name='reg_tr_nonbonded_mesh.mem' start='0x500' end='0x540' /><slave name='reg_bsn_monitor.mem' start='0x540' end='0x580' /><slave name='reg_st_sst.mem' start='0x580' end='0x5C0' /><slave name='avs_eth_0.mms_reg' start='0x5C0' end='0x600' /><slave name='reg_io_ddr.mem' start='0x600' end='0x640' /><slave name='timer_0.s1' start='0x640' end='0x660' /><slave name='reg_unb_sens.mem' start='0x660' end='0x680' /><slave name='reg_diag_bg.mem' start='0x680' end='0x6A0' /><slave name='reg_dp_ram_from_mm.mem' start='0x6A0' end='0x6C0' /><slave name='reg_dp_split.mem' start='0x6C0' end='0x6E0' /><slave name='reg_dp_pkt_merge.mem' start='0x6E0' end='0x700' /><slave name='reg_mdio_0.mem' start='0x700' end='0x720' /><slave name='reg_mdio_1.mem' start='0x720' end='0x740' /><slave name='reg_mdio_2.mem' start='0x740' end='0x760' /><slave name='reg_diag_bg_output.mem' start='0x760' end='0x780' /><slave name='altpll_0.pll_slave' start='0x780' end='0x790' /><slave name='pio_debug_wave.s1' start='0x790' end='0x7A0' /><slave name='pio_wdi.s1' start='0x7A0' end='0x7B0' /><slave name='reg_dp_sync_checker.mem' start='0x7B0' end='0x7C0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x7C0' end='0x7C8' /><slave name='reg_dp_offload_tx.mem' start='0x7C8' end='0x7D0' /><slave name='pio_pps.mem' start='0x7D0' end='0x7D8' /><slave name='reg_dp_xonoff_output.mem' start='0x7D8' end='0x7E0' /><slave name='reg_dp_switch.mem' start='0x7E0' end='0x7E8' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_st_sst.mem' start='0x4000' end='0x8000' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer_terminal.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x80000' /><slave name='ram_ss_ss_wide.mem' start='0x80000' end='0xC0000' /><slave name='reg_tr_10GbE.mem' start='0xC0000' end='0xC8000' /><slave name='ram_ss_ss_wide_transp.mem' start='0xC8000' end='0xD0000' /><slave name='reg_tr_xaui.mem' start='0xD0000' end='0xD2000' /><slave name='avs_eth_0.mms_ram' start='0xD2000' end='0xD3000' /><slave name='ram_diag_data_buffer_output.mem' start='0xD3000' end='0xD4000' /><slave name='ram_fringe_stop_offset.mem' start='0xD4000' end='0xD5000' /><slave name='ram_fringe_stop_step.mem' start='0xD5000' end='0xD6000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_terminal.mem' start='0x80' end='0x100' /><slave name='reg_diagnostics_mesh.mem' start='0x100' end='0x200' /><slave name='ram_dp_ram_from_mm.mem' start='0x200' end='0x300' /><slave name='reg_bsn_monitor_output.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x400' end='0x480' /><slave name='reg_diag_data_buffer_output.mem' start='0x480' end='0x500' /><slave name='reg_tr_nonbonded_mesh.mem' start='0x500' end='0x540' /><slave name='reg_bsn_monitor.mem' start='0x540' end='0x580' /><slave name='reg_st_sst.mem' start='0x580' end='0x5C0' /><slave name='avs_eth_0.mms_reg' start='0x5C0' end='0x600' /><slave name='reg_io_ddr.mem' start='0x600' end='0x640' /><slave name='timer_0.s1' start='0x640' end='0x660' /><slave name='reg_unb_sens.mem' start='0x660' end='0x680' /><slave name='reg_diag_bg.mem' start='0x680' end='0x6A0' /><slave name='reg_dp_ram_from_mm.mem' start='0x6A0' end='0x6C0' /><slave name='reg_dp_split.mem' start='0x6C0' end='0x6E0' /><slave name='reg_dp_pkt_merge.mem' start='0x6E0' end='0x700' /><slave name='reg_mdio_0.mem' start='0x700' end='0x720' /><slave name='reg_mdio_1.mem' start='0x720' end='0x740' /><slave name='reg_mdio_2.mem' start='0x740' end='0x760' /><slave name='reg_diag_bg_output.mem' start='0x760' end='0x780' /><slave name='altpll_0.pll_slave' start='0x780' end='0x790' /><slave name='pio_debug_wave.s1' start='0x790' end='0x7A0' /><slave name='pio_wdi.s1' start='0x7A0' end='0x7B0' /><slave name='reg_dp_sync_checker.mem' start='0x7B0' end='0x7C0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x7C0' end='0x7C8' /><slave name='reg_dp_offload_tx.mem' start='0x7C8' end='0x7D0' /><slave name='pio_pps.mem' start='0x7D0' end='0x7D8' /><slave name='reg_dp_xonoff_output.mem' start='0x7D8' end='0x7E0' /><slave name='reg_dp_switch.mem' start='0x7E0' end='0x7E8' /><slave name='reg_dp_fifo_monitor.mem' start='0x800' end='0x820' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_st_sst.mem' start='0x4000' end='0x8000' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer_terminal.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x80000' /><slave name='ram_ss_ss_wide.mem' start='0x80000' end='0xC0000' /><slave name='reg_tr_10GbE.mem' start='0xC0000' end='0xC8000' /><slave name='ram_ss_ss_wide_transp.mem' start='0xC8000' end='0xD0000' /><slave name='reg_tr_xaui.mem' start='0xD0000' end='0xD2000' /><slave name='avs_eth_0.mms_ram' start='0xD2000' end='0xD3000' /><slave name='ram_diag_data_buffer_output.mem' start='0xD3000' end='0xD4000' /><slave name='ram_fringe_stop_offset.mem' start='0xD4000' end='0xD5000' /><slave name='ram_fringe_stop_step.mem' start='0xD5000' end='0xD6000' /></address-map>]]></parameter>
<parameter name="dataAddrWidth" value="20" />
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
<parameter name="cpuReset" value="false" />
@@ -1506,6 +1522,15 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_fifo_monitor">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
<connection
kind="avalon"
version="11.1"
@@ -2125,4 +2150,17 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000d5000" />
</connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_dp_fifo_monitor.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_fifo_monitor.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0800" />
+ </connection>
</system>
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
index fb2316ba0f..5a56d391bc 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
@@ -18,7 +18,7 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, technology_lib, io_ddr_lib, eth_lib, tech_tse_lib, bf_lib, tech_ddr_lib, tr_10GbE_lib, reorder_lib, diag_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, technology_lib, io_ddr_lib, eth_lib, tech_tse_lib, bf_lib, tech_ddr_lib, tr_10GbE_lib, tech_mac_10g_lib, reorder_lib, diag_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -39,6 +39,7 @@ USE reorder_lib.reorder_pkg.ALL;
USE bf_lib.bf_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE work.apertif_unb1_fn_beamformer_pkg.ALL;
+USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
ENTITY apertif_unb1_fn_beamformer IS
GENERIC (
@@ -164,6 +165,8 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
-- Interface: 10GbE
CONSTANT c_nof_10GbE_offload_streams : NATURAL := 1;
CONSTANT c_pkt_len : NATURAL := 176; -- Let tr_10GbE FIFO buffer one full packet before releasing it
+ CONSTANT c_nof_pkt_hdr_words : NATURAL := 7;
+ CONSTANT c_tr_10GbE_pkt_len : NATURAL := c_pkt_len + c_nof_pkt_hdr_words; -- 176+7=183
SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
@@ -179,7 +182,10 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
SIGNAL dp_xonoff_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
SIGNAL dp_xonoff_src_in_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
-
+
+ SIGNAL tr_10GbE_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
+ SIGNAL tr_10GbE_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
+
----------------------------------------------------
-- Constants and signals for the reorder function --
--------------------------------------------------
@@ -364,6 +370,15 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
SIGNAL reg_dp_switch_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_switch_miso : t_mem_miso;
+ -- FIFO monitor to control fill level (optical fiber delay compensation)
+ SIGNAL reg_dp_fifo_monitor_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_dp_fifo_monitor_miso : t_mem_miso;
+
+ SIGNAL dp_fifo_fill_rd_usedw_32b : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_rd_emp : STD_LOGIC;
+ SIGNAL dp_fifo_fill_wr_full : STD_LOGIC;
+ SIGNAL dp_fifo_fill_rd_fill_32b : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
BEGIN
-----------------------------------------------------------------------------
@@ -655,7 +670,7 @@ BEGIN
bsn_in_sosi_arr(0) <= beamlets_offload_snk_in_arr(0);
bsn_in_sosi_arr(1) <= dp_offload_tx_src_out_arr(0);
- bsn_in_sosi_arr(2) <= dp_xonoff_src_out_arr(0);
+ bsn_in_sosi_arr(2) <= tr_10GbE_snk_in_arr(0);
-----------------------------------------------------------------------------
-- Data buffer to monitor beamlet offload input
@@ -765,6 +780,62 @@ BEGIN
src_out_arr => dp_xonoff_src_out_arr
);
+ -----------------------------------------------------------------------------
+ -- Optical fiber delay compensation using dp_fifo_fill
+ -- . Maximum fill level:
+ -- . RT6 (closest to correlator): 130m
+ -- . RTD (furthest away from correlator): 2274m
+ -- . Difference: 2274-130=2144m
+ -- . Speed of light through optical fiber = 200Mm/sec = 5ns/m
+ -- . We need to be able to buffer 2144m = 2144*5ns=10.72us
+ -- . Packet rate: 781250 packets/sec = 1 packet/1.28us
+ -- . We need to be able to buffer 10.72/1.28=8.375 packets -> 9 packets
+ -----------------------------------------------------------------------------
+ u_dp_fifo_fill : ENTITY dp_lib.dp_fifo_fill
+ GENERIC MAP (
+ g_data_w => c_xgmii_data_w,
+ g_empty_w => c_tech_mac_10g_empty_w,
+ g_use_bsn => FALSE,
+ g_use_empty => TRUE,
+ g_use_channel => FALSE,
+ g_use_error => FALSE,
+ g_use_sync => FALSE,
+ g_fifo_fill => 9*c_tr_10GbE_pkt_len,
+ g_fifo_size => 9*c_tr_10GbE_pkt_len
+ )
+ PORT MAP (
+ clk => dp_clk,
+ rst => dp_rst,
+ wr_ful => dp_fifo_fill_wr_full,
+ rd_emp => dp_fifo_fill_rd_emp,
+
+ rd_usedw_32b=> dp_fifo_fill_rd_usedw_32b,
+ rd_fill_32b => dp_fifo_fill_rd_fill_32b,
+
+ snk_in => dp_xonoff_src_out_arr(0),
+ snk_out => dp_xonoff_src_in_arr(0),
+
+ src_out => tr_10GbE_snk_in_arr(0),
+ src_in => tr_10GbE_snk_out_arr(0)
+ );
+
+ u_dp_fifo_monitor: ENTITY dp_lib.dp_fifo_monitor
+ PORT MAP (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ reg_mosi => reg_dp_fifo_monitor_mosi,
+ reg_miso => reg_dp_fifo_monitor_miso,
+
+ rd_usedw_32b => dp_fifo_fill_rd_usedw_32b,
+ rd_emp => dp_fifo_fill_rd_emp,
+ wr_full => dp_fifo_fill_wr_full,
+ rd_fill_32b => dp_fifo_fill_rd_fill_32b
+ );
+
-----------------------------------------------------------------------------
-- Interface : 10GbE
-----------------------------------------------------------------------------
@@ -786,9 +857,9 @@ BEGIN
g_nof_macs => c_nof_10GbE_offload_streams,
g_use_mdio => TRUE,
g_direction => "TX_ONLY",
- g_tx_fifo_fill => c_pkt_len,
- g_tx_fifo_size => 2*c_pkt_len,
- g_rx_fifo_size => 2*c_pkt_len
+ g_tx_fifo_fill => c_tr_10GbE_pkt_len,
+ g_tx_fifo_size => 2*c_tr_10GbE_pkt_len,
+ g_rx_fifo_size => 2*c_tr_10GbE_pkt_len
)
PORT MAP (
@@ -812,8 +883,8 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
- snk_out_arr => dp_xonoff_src_in_arr,
- snk_in_arr => dp_xonoff_src_out_arr,
+ snk_in_arr => tr_10GbE_snk_in_arr,
+ snk_out_arr => tr_10GbE_snk_out_arr,
xaui_tx_arr => xaui_tx_arr,
xaui_rx_arr => xaui_rx_arr,
@@ -1049,6 +1120,9 @@ BEGIN
reg_dp_switch_mosi => reg_dp_switch_mosi,
reg_dp_switch_miso => reg_dp_switch_miso,
+ reg_dp_fifo_monitor_mosi => reg_dp_fifo_monitor_mosi,
+ reg_dp_fifo_monitor_miso => reg_dp_fifo_monitor_miso,
+
ram_fringe_stop_offset_mosi => ram_fringe_stop_offset_mosi,
ram_fringe_stop_offset_miso => ram_fringe_stop_offset_miso,
ram_fringe_stop_step_mosi => ram_fringe_stop_step_mosi,
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd
index ee865af09f..5f1aead398 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd
@@ -172,7 +172,11 @@ ENTITY mmm_apertif_unb1_fn_beamformer IS
-- . dp_switch
reg_dp_switch_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
- reg_dp_switch_miso : IN t_mem_miso;
+ reg_dp_switch_miso : IN t_mem_miso;
+
+ -- . dp_fifo_monitor
+ reg_dp_fifo_monitor_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_fifo_monitor_miso : IN t_mem_miso;
-- . fringe stop
ram_fringe_stop_offset_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
@@ -224,6 +228,8 @@ ARCHITECTURE str OF mmm_apertif_unb1_fn_beamformer IS
CONSTANT c_reg_dp_pkt_merge_nof_words : NATURAL := 1;
CONSTANT c_reg_dp_pkt_merge_adr_w : NATURAL := ceil_log2(c_eth_nof_udp_ports * pow2(ceil_log2(c_reg_dp_pkt_merge_nof_words)));
+ CONSTANT c_reg_dp_fifo_monitor_adr_w : NATURAL := 3;
+
-- 10GbE offload
CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1;
CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(c_apertif_udp_offload_hdr_field_arr, c_word_w); -- = 26 32b words
@@ -388,6 +394,9 @@ BEGIN
u_mm_file_reg_dp_switch : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SWITCH")
PORT MAP(mm_rst, i_mm_clk, reg_dp_switch_mosi, reg_dp_switch_miso );
+
+ u_mm_file_reg_dp_fifo_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_FIFO_MONITOR")
+ PORT MAP(mm_rst, i_mm_clk, reg_dp_fifo_monitor_mosi, reg_dp_fifo_monitor_miso );
u_mm_file_ram_fringe_stop_offset : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FRINGE_STOP_OFFSET")
PORT MAP(mm_rst, i_mm_clk, ram_fringe_stop_offset_mosi, ram_fringe_stop_offset_miso );
@@ -576,6 +585,15 @@ BEGIN
coe_reset_export_from_the_reg_dp_switch => OPEN,
coe_write_export_from_the_reg_dp_switch => reg_dp_switch_mosi.wr,
coe_writedata_export_from_the_reg_dp_switch => reg_dp_switch_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_dp_fifo_monitor
+ coe_address_export_from_the_reg_dp_fifo_monitor => reg_dp_fifo_monitor_mosi.address(c_reg_dp_fifo_monitor_adr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_reg_dp_fifo_monitor => OPEN,
+ coe_read_export_from_the_reg_dp_fifo_monitor => reg_dp_fifo_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_fifo_monitor => reg_dp_fifo_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_dp_fifo_monitor => OPEN,
+ coe_write_export_from_the_reg_dp_fifo_monitor => reg_dp_fifo_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_fifo_monitor => reg_dp_fifo_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_debug_wave
out_port_from_the_pio_debug_wave => OPEN,
--
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