From 7c2dd67944ee80e31540644daf585a648ea68dbb Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Mon, 9 May 2016 10:55:13 +0000
Subject: [PATCH] Made tb self stopping.
---
libraries/base/common/tb/vhdl/tb_resize.vhd | 24 ++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/libraries/base/common/tb/vhdl/tb_resize.vhd b/libraries/base/common/tb/vhdl/tb_resize.vhd
index f324cf1bef..900976fc66 100644
--- a/libraries/base/common/tb/vhdl/tb_resize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_resize.vhd
@@ -59,16 +59,34 @@ ARCHITECTURE tb OF tb_resize IS
SIGNAL out_sovr : STD_LOGIC;
SIGNAL out_uovr : STD_LOGIC;
- SIGNAL rst : STD_LOGIC;
+ SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL rst : STD_LOGIC;
CONSTANT c_init : STD_LOGIC_VECTOR(in_dat'RANGE) := (OTHERS=>'0');
BEGIN
-- Stimuli
- clk <= NOT(clk) AFTER clk_period/2;
+ clk <= NOT clk OR tb_end AFTER clk_period/2;
rst <= '1', '0' AFTER 3*clk_period;
+
+ -- Testbench end
+ p_tb_end : PROCESS
+ VARIABLE v_dat : STD_LOGIC_VECTOR(in_dat'RANGE);
+ BEGIN
+ tb_end <= '0';
+ WAIT UNTIL in_val='1';
+ WAIT UNTIL rising_edge(clk);
+ v_dat := in_dat; -- keep first in_dat
+ WAIT UNTIL rising_edge(clk);
+ WAIT UNTIL v_dat=in_dat; -- wait until all incrementing in_dat values have been applied at least once
+ WAIT UNTIL rising_edge(clk);
+ WAIT UNTIL rising_edge(clk);
+ WAIT UNTIL rising_edge(clk);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
p_clk : PROCESS (rst, clk)
BEGIN
@@ -136,7 +154,7 @@ BEGIN
out_ovr => out_uovr
);
- -- Vericfication
+ -- Verification
p_verify_increase : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
--
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