From 7be625a6788951e7ea3015d2878352bea0960efe Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Mon, 23 Nov 2015 10:58:29 +0000
Subject: [PATCH] Added tb_end to make the tb self stopping.
---
.../base/common_mult/tb/vhdl/tb_common_mult_add2.vhd | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
index cb167790bc..dc7aef2237 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
@@ -19,6 +19,13 @@
--
-------------------------------------------------------------------------------
+-- Purpose: Tb for common_mult_add2 architectures
+-- Description:
+-- The tb is self verifying.
+-- Usage:
+-- > as 10
+-- > run -all
+
LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
@@ -77,6 +84,7 @@ ARCHITECTURE tb OF tb_common_mult_add2 IS
RETURN STD_LOGIC_VECTOR(v_result);
END;
+ SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '0';
SIGNAL in_a0 : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
@@ -92,7 +100,7 @@ ARCHITECTURE tb OF tb_common_mult_add2 IS
BEGIN
- clk <= NOT clk AFTER clk_period/2;
+ clk <= NOT clk OR tb_end AFTER clk_period/2;
-- run 1 us
p_in_stimuli : PROCESS
@@ -161,6 +169,8 @@ BEGIN
END LOOP;
END LOOP;
END LOOP;
+
+ tb_end <= '1';
WAIT;
END PROCESS;
--
GitLab