diff --git a/libraries/technology/mac_10g/tech_mac_10g.vhd b/libraries/technology/mac_10g/tech_mac_10g.vhd
index 5e2370274f34669c2b07d7e52f474e9028107fcc..e468d6b5052cccd10239ccff1b7dce5fba2fd88c 100644
--- a/libraries/technology/mac_10g/tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g.vhd
@@ -23,36 +23,51 @@
-- Purpose:
-- Description:
+-- . Block diagram:
+-- <-- tx_clk_312
+-- <-- tx_clk_156
+-- <-- rx_clk_312
+-- <-- rx_clk_156
+-- g_pre_header_padding |
+-- | tx_remove_snk tx_mac_snk
+-- __________ | . ______________ . __________________
+-- | | | . | | . | |
+-- | dp_pad | | . | dp_latency | . | |
+-- tx_snk -->| remove |----------------------|---->| adapter |---->| |
+-- | | | | RL=1 --> 0 | | |
+-- |________| | |____________| | |
+-- | |tech_mac_10g |
+-- __________ ______________ | ______________ |ip_<device_name>|---XGMII
+-- | | | | | | | | |
+-- | dp_pad | | dp_latency | | | dp_latency | | |
+-- rx_src <--| insert |<----| fifo |<--|-----| adapter |<----| |
+-- | | . | | | . | RL=1 --> 0 | . | |
+-- |________| . |____________| | . |____________| . |________________|
+-- . | . . |
+-- x_fifo_src | rx_mac_src_rl1 rx_mac_src |
+-- | |
+-- | csr
--
+-- . Clocks:
+-- The 312.5 MHz and 156.25 MHz clocks are inputs to the MAC-10G.
+-- - For 10GBASE-R the Tx and Rx clocks come from the same local reference PLL.
+-- - For XAUI the 312.5 MHz is not used. The Tx clock comes from the local
+-- reference PLL. The Rx clock comes from the Rx PHY, so the Rx clock is
+-- then a different clock domain than the Tx clock and the Rx clock may then
+-- have some ppm drift with respect to the Tx clock.
+--
+-- . dp_latency_adapter:
+-- The dp_latency_adapters are needed to adjust to RL=1 for the DP interface.
+--
+-- . g_pre_header_padding:
-- If g_pre_header_padding is TRUE then remove pre header padding from ST tx
-- and insert it in ST rx, because the 10G MAC IP does not use pre header
-- padding. When g_pre_header_padding is FALSE then the ST frame is directly
-- passed on via the dp_latency_adapters. The dp_latency_adapters are needed
-- because the ST interface uses RL=1 whereas e.g. the Altera mac_10g IP uses
-- RL=0.
---
--- tx_remove_snk tx_mac_snk
--- __________ . ______________ . __________________
--- | | . | | . | |
--- | dp_pad | . | dp_latency | . | |
--- tx_snk -->| remove |----------------------->| adapter |---->| |
--- | | | RL=1 --> 0 | | |
--- |________| |____________| | |
--- |tech_mac_10g |
--- __________ ______________ ______________ |ip_<device_name>|---XGMII
--- | | | | | | | |
--- | dp_pad | | dp_latency | | dp_latency | | |
--- rx_src <--| insert |<----| fifo |<----| adapter |<----| |
--- | | . | | . | RL=1 --> 0 | . | |
--- |________| . |____________| . |____________| . |________________|
--- . . . |
--- x_fifo_src rx_mac_src_rl1 rx_mac_src |
--- |
--- csr
---
--- Remarks:
--- . The dp_latency_fifo is necessary because the rx_mac_src_in.ready must remain
--- active during a reception, otherwise the rx frame gets truncated due to
+-- The dp_latency_fifo is necessary because the rx_mac_src_in.ready must remain
+-- active during a receptiothe Rx clockn, otherwise the rx frame gets truncated due to
-- back pressure by dp_pad_insert.
--
@@ -80,15 +95,15 @@ ENTITY tech_mac_10g IS
csr_miso : OUT t_mem_miso;
-- ST
- tx_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz
- tx_clk_156 : IN STD_LOGIC; -- 156.25 MHz local reference
- tx_rst : IN STD_LOGIC;
+ tx_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz from local reference or not used, dependent on g_technology
+ tx_clk_156 : IN STD_LOGIC; -- 156.25 MHz from local reference
+ tx_rst : IN STD_LOGIC; -- for tx_clk_156 clock domain
tx_snk_in : IN t_dp_sosi; -- 64 bit data
tx_snk_out : OUT t_dp_siso;
- rx_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz
- rx_clk_156 : IN STD_LOGIC; -- 156.25 MHz from rx phy
- rx_rst : IN STD_LOGIC;
+ rx_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz from local reference or not used, dependent on g_technology
+ rx_clk_156 : IN STD_LOGIC; -- 156.25 MHz from local reference or from rx phy, dependent on g_technology
+ rx_rst : IN STD_LOGIC; -- for rx_clk_156 clock domain
rx_src_out : OUT t_dp_sosi; -- 64 bit data
rx_src_in : IN t_dp_siso;