From 7b94f81eae55dff5797af6dea75e25b2a3a2b241 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 13 Jun 2014 09:53:42 +0000
Subject: [PATCH] Added g_technology.
---
libraries/io/eth/src/vhdl/eth.vhd | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/libraries/io/eth/src/vhdl/eth.vhd b/libraries/io/eth/src/vhdl/eth.vhd
index a432470814..b9378d07df 100644
--- a/libraries/io/eth/src/vhdl/eth.vhd
+++ b/libraries/io/eth/src/vhdl/eth.vhd
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib, tech_tse_lib;
+LIBRARY IEEE, common_lib, dp_lib, tech_tse_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
@@ -28,6 +28,7 @@ USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.eth_layers_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE work.eth_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
-- Purpose:
-- Provide Ethernet control access to a node and some UDP ports for streaming
@@ -39,8 +40,9 @@ USE work.eth_pkg.ALL;
ENTITY eth IS
GENERIC (
- g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_ETH_PHY : STRING := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ g_technology : NATURAL := c_tech_select_default;
+ g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_ETH_PHY : STRING := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
g_ihl20 : BOOLEAN := FALSE
);
PORT (
@@ -575,8 +577,9 @@ BEGIN
tse_tx_mac_in.crc_fwd <= '0'; -- when '0' then TSE MAC generates the TX CRC field
- u_tse : ENTITY work.tse
+ u_tech_tse : ENTITY tech_tse_lib.tech_tse
GENERIC MAP (
+ g_technology => g_technology,
g_ETH_PHY => g_ETH_PHY
)
PORT MAP (
--
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