diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
index 15c8d9491520943af0974a751f9a88452407ecdf..9fb3e69c10091de3095e880c8d86d45364df93a5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
@@ -51,39 +51,39 @@ peripherals:
mm_port_names:
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
-
+
- peripheral_name: unb2b_board/ram_scrap
mm_port_names:
- RAM_SCRAP
-
+
- peripheral_name: eth/eth
mm_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
- AVS_ETH_0_RAM
-
+
- peripheral_name: ppsh/ppsh
mm_port_names:
- PIO_PPS
-
+
- peripheral_name: epcs/epcs
mm_port_names:
- REG_EPCS
-
+
- peripheral_name: dp/dpmm
mm_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
-
+
- peripheral_name: dp/mmdp
mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
-
+
- peripheral_name: remu/remu
mm_port_names:
- REG_REMU
-
+
#############################################################################
# AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
#############################################################################
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index 4703e1799ee43a64a566f6b0394ad2ee42622311..51d668cbecb859f0d5302bf339874cb805f80944 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -17,20 +17,20 @@ peripherals:
participates in one band."
mm_port_type: REG
fields:
- - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x0 }
- - - { field_name: antenna_band_index, width: 1, access_mode: RO, address_offset: 0x4 }
- - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x8 }
- - - { field_name: nyquist_zone_index, width: 2, access_mode: RW, address_offset: 0xC }
- - - { field_name: f_adc, width: 1, access_mode: RO, address_offset: 0x10 }
- - - { field_name: fsub_type, width: 1, access_mode: RO, address_offset: 0x14 }
- - - { field_name: beam_repositioning_flag, width: 1, access_mode: RW, address_offset: 0x18 }
- - - { field_name: subband_calibrated_flag, width: 1, access_mode: RW, address_offset: 0x1C }
- - - { field_name: O_si, width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: N_si, width: 8, access_mode: RW, address_offset: 0x24 }
- - - { field_name: O_rn, width: 8, access_mode: RW, address_offset: 0x28 }
- - - { field_name: N_rn, width: 8, access_mode: RW, address_offset: 0x2C }
- - - { field_name: block_period, width: 16, access_mode: RO, address_offset: 0x30 }
- - - { field_name: beamlet_scale, width: 16, access_mode: RW, address_offset: 0x34 }
+ - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x0 }
+ - - { field_name: antenna_band_index, mm_width: 1, access_mode: RO, address_offset: 0x4 }
+ - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: nyquist_zone_index, mm_width: 2, access_mode: RW, address_offset: 0xC }
+ - - { field_name: f_adc, mm_width: 1, access_mode: RO, address_offset: 0x10 }
+ - - { field_name: fsub_type, mm_width: 1, access_mode: RO, address_offset: 0x14 }
+ - - { field_name: beam_repositioning_flag, mm_width: 1, access_mode: RW, address_offset: 0x18 }
+ - - { field_name: subband_calibrated_flag, mm_width: 1, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: O_si, mm_width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: N_si, mm_width: 8, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: O_rn, mm_width: 8, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: N_rn, mm_width: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: block_period, mm_width: 16, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: beamlet_scale, mm_width: 16, access_mode: RW, address_offset: 0x34 }
- peripheral_name: sdp_subband_equalizer # pi_sdp_subband_equalizer.py
@@ -54,8 +54,8 @@ peripherals:
- - field_name: coef
field_description: |
"Complex coefficient to calibrate the gain and phase per subband. Packed as imaginary in high part,
- real in low part of width = N_complex * W_sub_weight = 2 * 16 = 32 bit."
- width: 32 # = N_complex * W_sub_weight
+ real in low part of mm_width = N_complex * W_sub_weight = 2 * 16 = 32 bit."
+ mm_width: 32 # = N_complex * W_sub_weight
address_offset: 0x0
number_of_fields: 1024 # = Q_fft * N_sub = 2 signal inputs * 512 subbands
radix: complx
@@ -102,8 +102,8 @@ peripherals:
- - field_name: coef
field_description: |
"Complex weight per subband. Packed as imaginary in high part, real in low part
- of width = N_complex * W_bf_weight = 2 * 16 = 32 bit."
- width: 32 # = N_complex * W_bf_weight
+ of mm_width = N_complex * W_bf_weight = 2 * 16 = 32 bit."
+ mm_width: 32 # = N_complex * W_bf_weight
address_offset: 0x0
number_of_fields: g_nof_gains
radix: complx
@@ -133,7 +133,7 @@ peripherals:
fields:
- - field_name: scale
field_description: ""
- width: g_gain_w
+ mm_width: g_gain_w
address_offset: 0x0
number_of_fields: 1
radix: unsigned
@@ -175,50 +175,50 @@ peripherals:
mm_port_type: REG
fields:
# eth field group
- - - { field_name: eth_destination_mac, width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
- - - { field_name: eth_source_mac, width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
- - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
# udp field group
- - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
# application field group
- - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- "source_info":
- - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: beamlet_width, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, width: 32, user_width: 40, access_mode: RW, address_offset: 0x1C }
- - - { field_name: beamlet_scale, width: 16, access_mode: RW, address_offset: 0x18 }
- - - { field_name: beamlet_index, width: 16, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_blocks_per_packet, width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_beamlets_per_block, width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
+ - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beamlet_width, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, mm_width: 32, user_width: 40, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: beamlet_scale, mm_width: 16, access_mode: RW, address_offset: 0x18 }
+ - - { field_name: beamlet_index, mm_width: 16, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_blocks_per_packet, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_beamlets_per_block, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_sst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -239,57 +239,57 @@ peripherals:
mm_port_type: REG
fields:
# eth field group
- - - { field_name: word_align, width: 16, access_mode: RW, address_offset: 0x8C }
- - - { field_name: eth_destination_mac, width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
- - - { field_name: eth_source_mac, width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
- - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
# udp field group
- - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
# application field group
- - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- "source_info":
- - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: beam_repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: subband_calibrated_flag, width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
- - { field_name: reserved, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: integration_interval, width: 24, access_mode: RW, address_offset: 0x1C }
- - - { field_name: data_id, width: 32, access_mode: RW, address_offset: 0x18 }
+ - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
+ - { field_name: reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
- "data_id_sst":
- - { field_name: reserved, width: 24, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
- - { field_name: signal_input_index, width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+ - { field_name: reserved, mm_width: 24, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_index, mm_width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
- - - { field_name: nof_signal_inputs, width: 8, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
+ - - { field_name: nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_bst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -310,57 +310,57 @@ peripherals:
mm_port_type: REG
fields:
# eth field group
- - - { field_name: word_align, width: 16, access_mode: RW, address_offset: 0x8C }
- - - { field_name: eth_destination_mac, width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
- - - { field_name: eth_source_mac, width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
- - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
# udp field group
- - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
# application field group
- - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- "source_info":
- - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: beam_repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: subband_calibrated_flag, width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
- - { field_name: reserved, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: integration_interval, width: 24, access_mode: RW, address_offset: 0x1C }
- - - { field_name: data_id, width: 32, access_mode: RW, address_offset: 0x18 }
+ - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
+ - { field_name: reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
- "data_id_bst":
- - { field_name: reserved, width: 16, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
- - { field_name: beamlet_index, width: 16, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+ - { field_name: reserved, mm_width: 16, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
+ - { field_name: beamlet_index, mm_width: 16, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
- - - { field_name: nof_signal_inputs, width: 8, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
+ - - { field_name: nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_xst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -382,57 +382,57 @@ peripherals:
mm_port_type: REG
fields:
# eth field group
- - - { field_name: word_align, width: 16, access_mode: RW, address_offset: 0x8C }
- - - { field_name: eth_destination_mac, width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
- - - { field_name: eth_source_mac, width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
- - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
# udp field group
- - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
# application field group
- - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- "source_info":
- - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: beam_repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: subband_calibrated_flag, width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
- - { field_name: reserved, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: integration_interval, width: 24, access_mode: RW, address_offset: 0x1C }
- - - { field_name: data_id, width: 32, access_mode: RW, address_offset: 0x18 }
+ - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
+ - { field_name: reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
- "data_id_xst":
- - { field_name: reserved, width: 7, bit_offset: 25, access_mode: RW, address_offset: 0x18 }
- - { field_name: subband_index, width: 9, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
- - { field_name: signal_input_A_index, width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
- - { field_name: signal_input_B_index, width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
-
- - - { field_name: nof_signal_inputs, width: 8, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
+ - { field_name: reserved, mm_width: 7, bit_offset: 25, access_mode: RW, address_offset: 0x18 }
+ - { field_name: subband_index, mm_width: 9, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_A_index, mm_width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_B_index, mm_width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+
+ - - { field_name: nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
diff --git a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
index e85ac86d90071a13a312f2a805e5a9ac0be32bba..f9c7e041629aa64c58f7eba0281b6c4bcd903a1d 100644
--- a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
+++ b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
@@ -51,7 +51,7 @@ peripherals:
mm_port_type : REG
fields:
- - field_name : nios_reset
- width : 32
+ mm_width : 32
access_mode : WO
address_offset : 0x0
number_of_fields: 1
@@ -92,7 +92,7 @@ peripherals:
mm_port_type : REG
fields:
- - field_name : sens_data
- width : 8
+ mm_width : 8
access_mode : RO
address_offset: 0x0
number_of_fields: 4
@@ -104,14 +104,14 @@ peripherals:
0x3 = hot_swap_v_source"
- - field_name : sens_err
- width : 1
+ mm_width : 1
access_mode : RO
address_offset: 0x10
radix : unsigned
field_description: ""
- - field_name : temp_high
- width : 7
+ mm_width : 7
address_offset: 0x14
reset_value : g_temp_high
software_value: g_temp_high
diff --git a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
index 01243fd42502200dbbc1ec823b7c66f6cb3da100..678ac4ecf5d194ca2db33c22031bf92dd773ca73 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
+++ b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
@@ -24,11 +24,11 @@ peripherals:
mm_port_names:
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
-
+
- peripheral_name: unb2b_board/ram_scrap
mm_port_names:
- RAM_SCRAP
-
+
- peripheral_name: eth/eth
mm_port_names:
- AVS_ETH_0_TSE
@@ -42,17 +42,17 @@ peripherals:
- peripheral_name: epcs/epcs
mm_port_names:
- REG_EPCS
-
+
- peripheral_name: dp/dpmm
mm_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
-
+
- peripheral_name: dp/mmdp
mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
-
+
- peripheral_name: remu/remu
mm_port_names:
- REG_REMU
diff --git a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
index 1446b091aecfe4be79ec88229d6da1a960ed82e2..adcdf622aee27b92cfcf0d1bc9a5336324597be2 100644
--- a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
+++ b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
@@ -52,56 +52,56 @@ peripherals:
# Each field specified
- - field_name: info
field_description: "Info"
- width: 32
+ mm_width: 32
bit_offset: 0
access_mode: RO
address_offset: 0x0
- "info": # field_group
- field_name: gn_index
field_description: "Global node index, unb2 FPGA id = gn_index % 4, unb2 backplane id = gn_index // 4"
- width: 8
+ mm_width: 8
bit_offset: 0
access_mode: RO
address_offset: 0x0
- field_name: hw_version
field_description: "UniBoard2 hardware (HW) version."
- width: 2
+ mm_width: 2
bit_offset: 8
access_mode: RO
address_offset: 0x0
- field_name: cs_sim
field_description: "0 when running on HW, 1 when running in simulation."
- width: 1
+ mm_width: 1
bit_offset: 10
access_mode: RO
address_offset: 0x0
- field_name: fw_version_major
field_description: "FPGA Firmware (FW) version major number, not used use version stamp instead."
- width: 4
+ mm_width: 4
bit_offset: 16
access_mode: RO
address_offset: 0x0
- field_name: fw_version_minor
field_description: "FPGA Firmware (FW) version minor number, not used use version stamp instead."
- width: 4
+ mm_width: 4
bit_offset: 20
access_mode: RO
address_offset: 0x0
- field_name: rom_version
field_description: "Version of the mmap schema in ROM_SYSTEM_INFO."
- width: 3
+ mm_width: 3
bit_offset: 24
access_mode: RO
address_offset: 0x0
- field_name: technology
field_description: "FPGA technology"
- width: 5
+ mm_width: 5
bit_offset: 27
access_mode: RO
address_offset: 0x0
- - field_name: use_phy
field_description: "PHY interfaces that are active in the FPGA, not used."
- width: 8
+ mm_width: 8
access_mode: RO
address_offset: 0x4
- - field_name: design_name
diff --git a/libraries/base/common/common.peripheral.yaml b/libraries/base/common/common.peripheral.yaml
index b9ad15bbbc80f89fafefa2a7b4e206061810d813..e59577af29c67ebbd2b74a5090337502014ade1a 100644
--- a/libraries/base/common/common.peripheral.yaml
+++ b/libraries/base/common/common.peripheral.yaml
@@ -21,6 +21,6 @@ peripherals:
fields:
- - field_name: enable
field_description: "When 1 pass on delayed pulse to the output, else disable the output pulse."
- width: 1
+ mm_width: 1
access_mode: RW
address_offset: 0x0
diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml
index c92c4a5823e36e62d9b5d26da9d022fb043b7b96..c5ed1b5fd9c9b168c7c93aad8e1a6fcefacd904e 100644
--- a/libraries/base/diag/diag.peripheral.yaml
+++ b/libraries/base/diag/diag.peripheral.yaml
@@ -20,7 +20,7 @@ peripherals:
fields:
- - field_name: nof_samples
field_description: "Number of samples in WG period."
- width: 16
+ mm_width: 16
bit_offset: 16
address_offset: 0x0
- - field_name: mode
@@ -30,22 +30,22 @@ peripherals:
1 = calc, uses WG buffer waveform to output sinus with ampl * sin(freq * t + phase
2 = repeat, outputs WG buffer waveform repeatedly
3 = single, outputs WG buffer waveform once"
- width: 8
+ mm_width: 8
bit_offset: 0
address_offset: 0x0
- - field_name: phase
field_description: "Phase of WG sinus, phase = int('phase in degrees' * 2**width / 360)."
- width: 16
+ mm_width: 16
bit_offset: 0
address_offset: 0x4
- - field_name: freq
field_description: "Frequency of WG sinus, freq = int('frequency in range 0 to 1' * f_adc * 2**width), where f_adc is sample frequency in Hz."
- width: 31
+ mm_width: 31
bit_offset: 0
address_offset: 0x8
- - field_name: ampl
field_description: "Amplitude of WG sinus, ampl = int('amplitude in range 0 to 2' * 2**(width-1), where amplitude > 1 causes clipping."
- width: 17
+ mm_width: 17
bit_offset: 0
address_offset: 0xC
# MM port for mms_diag_wg_wideband.vhd
@@ -56,7 +56,7 @@ peripherals:
fields:
- - field_name: data
field_description: "Waveform default is one sinus period (diag_sin_1024x18.hex)."
- width: 18 # = c_wg_buf_dat_w in node_adc_input_and_timing.vhd
+ mm_width: 18 # = c_wg_buf_dat_w in node_adc_input_and_timing.vhd
address_offset: 0x0
number_of_fields: 1024 # = 2**c_wg_buf_addr_w in node_adc_input_and_timing.vhd
@@ -91,7 +91,7 @@ peripherals:
fields:
- - field_name: data
field_description: ""
- width: g_data_w
+ mm_width: g_data_w
address_offset: 0x0
number_of_fields: g_nof_data
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 2b8a2d2c526b0493f40e9c2debbe8270d88a4ca2..f8074a6c5e7c3810f4d81524dfce44a3d745f3eb 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -73,7 +73,7 @@ peripherals:
field_description: |
"When enable_stream = 0 the data stream is stopped, else when 1 then the data stream is passed on.
Toggling the data stream on or off happens at block or packet boundaries."
- width: 1
+ mm_width: 1
access_mode: RW
address_offset: 0x0
number_of_fields: 1 #g_nof_streams #sel_a_b(g_combine_streams, 1, g_nof_streams)
@@ -95,7 +95,7 @@ peripherals:
fields:
- - field_name: shift
field_description: "Fill level of the sample delay buffer in number of data samples."
- width: ceil_log2(g_nof_words)
+ mm_width: ceil_log2(g_nof_words)
access_mode: RW
address_offset: 0x0
@@ -116,12 +116,12 @@ peripherals:
"When 1 then enable BSN source, else when 0 disable BSN source. If dp_on_pps is 0,
then dp_on = 1 enables the BSN source immediately. To enable the BSN source at
the next PPS, then first set dp_on_pps = 1. Clearing dp_on stops the BSN source."
- width: 1
+ mm_width: 1
access_mode: RW
address_offset: 0x0
- - field_name: dp_on_pps
field_description: "When 1 and dp_on = 1 then enable BSN source at next PPS."
- width: 1
+ mm_width: 1
bit_offset: 1
access_mode: RW
address_offset: 0x0
@@ -162,12 +162,12 @@ peripherals:
"When 1 then enable BSN source, else when 0 disable BSN source. If dp_on_pps is 0,
then dp_on = 1 enables the BSN source immediately. To enable the BSN source at
the next PPS, then first set dp_on_pps = 1. Clearing dp_on stops the BSN source."
- width: 1
+ mm_width: 1
access_mode: RW
address_offset: 0x0
- - field_name: dp_on_pps
field_description: "When 1 and dp_on = 1, then enable BSN source at next PPS."
- width: 1
+ mm_width: 1
bit_offset: 1
access_mode: RW
address_offset: 0x0
@@ -190,7 +190,7 @@ peripherals:
address_offset: 0x8
- - field_name: bsn_time_offset
field_description: "The BSN block time offset in number of clock cycles, with respect to the PPS."
- width: g_bsn_time_offset_w
+ mm_width: g_bsn_time_offset_w
access_mode: RW
address_offset: 0x10
@@ -232,19 +232,19 @@ peripherals:
fields:
- - field_name: xon_stable
field_description: "Data block flow control xon signal was active and stable during last sync interval."
- width: 1
+ mm_width: 1
bit_offset: 0
access_mode: RO
address_offset: 0x0
- - field_name: ready_stable
field_description: "Clock cycle flow control ready signal was active and stable during last sync interval."
- width: 1
+ mm_width: 1
bit_offset: 1
access_mode: RO
address_offset: 0x0
- - field_name: sync_timeout
field_description: "Data stream sync did not occur during last sync interval."
- width: 1
+ mm_width: 1
bit_offset: 2 # EK TODO: 2 is correct, but using 1 cause gen_doc.py to fail without clear error, because fields then overlap
access_mode: RO
address_offset: 0x0
@@ -306,19 +306,19 @@ peripherals:
fields:
- - field_name: xon_stable
field_description: "Data block flow control xon signal was active and stable during last sync interval."
- width: 1
+ mm_width: 1
bit_offset: 0
access_mode: RO
address_offset: 0x0
- - field_name: ready_stable
field_description: "Clock cycle flow control ready signal was active and stable during last sync interval."
- width: 1
+ mm_width: 1
bit_offset: 1
access_mode: RO
address_offset: 0x0
- - field_name: sync_timeout
field_description: "Data stream sync did not occur during last sync interval."
- width: 1
+ mm_width: 1
bit_offset: 1
access_mode: RO
address_offset: 0x0
@@ -365,6 +365,6 @@ peripherals:
field_description: |
"When input_select = 0 select the reference data stream(s), else when 1 select the other data stream(s).
The input_select is synchronsized to the start of a sync interval."
- width: 1
+ mm_width: 1
access_mode: RW
address_offset: 0x0
diff --git a/libraries/base/reorder/reorder.peripheral.yaml b/libraries/base/reorder/reorder.peripheral.yaml
index d74d0333fecd7b8a8243da6ffa36e6847b71716a..30e5ecff51b449a4b2ccbf02aee3570f23c93c9d 100644
--- a/libraries/base/reorder/reorder.peripheral.yaml
+++ b/libraries/base/reorder/reorder.peripheral.yaml
@@ -28,7 +28,7 @@ peripherals:
fields:
- - field_name: index
field_description: ""
- width: ceil_log2(g_nof_ch_in)
+ mm_width: ceil_log2(g_nof_ch_in)
address_offset: 0x0
number_of_fields: g_nof_ch_sel
diff --git a/libraries/dsp/bf/bf.peripheral.yaml b/libraries/dsp/bf/bf.peripheral.yaml
index 12c36e3e1a9c95371dbcca9f63b5a2f2d83604fb..547dc9a11ae7cb9fb5c29a64f63a0128d77ca811 100644
--- a/libraries/dsp/bf/bf.peripheral.yaml
+++ b/libraries/dsp/bf/bf.peripheral.yaml
@@ -23,7 +23,7 @@ peripherals:
mm_port_type: RAM
fields:
- - field_name : bf_weights
- width : g_bf.in_weights_w * c_nof_complex
+ mm_width : g_bf.in_weights_w * c_nof_complex
number_of_fields: g_bf.nof_signal_paths
field_description: |
@@ -38,7 +38,7 @@ peripherals:
mm_port_type: RAM
fields:
- - field_name : ss_ss_wide
- width : 32
+ mm_width : 32
number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream # 16*4=64, nof_input_streams*nof_signal_paths_per_stream
field_description: |
"Contains the addresses to select from the stored subbands."
@@ -51,7 +51,7 @@ peripherals:
mm_port_type: RAM
fields:
- - field_name : st_sst_bf
- width : 56
+ mm_width : 56
number_of_fields: 512
access_mode : RO
field_description: |
diff --git a/libraries/dsp/filter/filter.peripheral.yaml b/libraries/dsp/filter/filter.peripheral.yaml
index af75840c8d526380dcf05aeb4acab04678f8e6de..58e11c6ffe70779d39724e90474a9752e39ff743 100644
--- a/libraries/dsp/filter/filter.peripheral.yaml
+++ b/libraries/dsp/filter/filter.peripheral.yaml
@@ -39,6 +39,6 @@ peripherals:
fields:
- - field_name: coef
field_description: "Real FIR filter coefficient"
- width: g_coef_dat_w
+ mm_width: g_coef_dat_w
address_offset: 0x0
number_of_fields: g_nof_bands / g_wb_factor
diff --git a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
index 2872466d08baf491453e722ba3bd0403fb03ed53..67772e418753ee5bfae3ee7530e80abd9be46167 100644
--- a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
+++ b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
@@ -19,7 +19,7 @@ peripherals:
mm_port_type : RAM
fields:
- - field_name : fringe_stop_step
- width: g_fs_step_w
+ mm_width: g_fs_step_w
number_of_fields: g_nof_channels
field_description: |
"Contains the step size for all nof_channels channels."
@@ -30,7 +30,7 @@ peripherals:
mm_port_type : RAM
fields:
- - field_name: fringe_stop_offset
- width: g_fs_offset_w
+ mm_width: g_fs_offset_w
number_of_fields: g_nof_channels
field_description: |
"Contains the offset for all nof_channels channels."
diff --git a/libraries/dsp/si/si.peripheral.yaml b/libraries/dsp/si/si.peripheral.yaml
index 470bac8cdd0d81af50ff66cb9e581e19edb23db2..d738cebd2225f68bbb139bfa6e46ddea50622cb2 100644
--- a/libraries/dsp/si/si.peripheral.yaml
+++ b/libraries/dsp/si/si.peripheral.yaml
@@ -16,5 +16,5 @@ peripherals:
fields:
- - field_name: enable
field_description: "When 0 then pass on the array of input signals, when 1 then enable spectral inversion for all the input signals."
- width: 1
+ mm_width: 1
address_offset: 0x0
diff --git a/libraries/dsp/st/st.peripheral.yaml b/libraries/dsp/st/st.peripheral.yaml
index 9b44ee5f6e297b4fc638aafd0f0f19809669d498..c029d6f7d5b6a9b9157f4a475cdddd9fa183f3b6 100644
--- a/libraries/dsp/st/st.peripheral.yaml
+++ b/libraries/dsp/st/st.peripheral.yaml
@@ -17,8 +17,8 @@ peripherals:
# Parameters of st_sst.vhd
- { name: g_nof_stat, value: 512 } # nof accumulators
- { name: g_xst_enable, value: False } # False for auto powers, True for cross powers
- - { name: g_stat_data_w, value: 64 } # statistics accumulator width in bits
- - { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words
+ - { name: g_stat_data_w, value: 64 } # statistics accumulator user_width in bits
+ - { name: g_stat_data_sz, value: 2 } # statistics accumulator user_width in 32b MM words
mm_ports:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
@@ -33,7 +33,7 @@ peripherals:
fields:
- - field_name: power
field_description: ""
- width: g_stat_data_w
+ mm_width: g_stat_data_w
address_offset: 0x0
number_of_fields: g_nof_stat * g_stat_data_sz
@@ -46,8 +46,8 @@ peripherals:
- { name: g_nof_instances, value: 6 }
# Parameters of st_sst.vhd, fixed in node_sdp_filterbank.vhd / sdp_pkg.vhd
- { name: g_nof_stat, value: 1024 } # nof accumulators: N_sub * Q_fft = 512 * 2 = 1024
- - { name: g_stat_data_w, value: 54 } # statistics accumulator width in bits: W_statistic = 64
- - { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words: W_statistic_sz = 2
+ - { name: g_stat_data_w, value: 54 } # statistics accumulator user_width in bits: W_statistic = 64
+ - { name: g_stat_data_sz, value: 2 } # statistics accumulator user_width in 32b MM words: W_statistic_sz = 2
mm_ports:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
@@ -63,7 +63,7 @@ peripherals:
fields:
- - field_name: power
field_description: ""
- width: 32
+ mm_width: 32
user_width: g_stat_data_w
address_offset: 0x0
number_of_fields: g_nof_stat * g_stat_data_sz
@@ -77,8 +77,8 @@ peripherals:
- { name: g_nof_instances, value: 6 }
# Parameters of st_sst.vhd, fixed in node_sdp_filterbank.vhd / sdp_pkg.vhd
- { name: g_nof_stat, value: 976 } # nof accumulators: S_sub_bf * N_pol_bf = 488 * 2 = 976
- - { name: g_stat_data_w, value: 54 } # statistics accumulator width in bits: W_statistic = 64
- - { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words: W_statistic_sz = 2
+ - { name: g_stat_data_w, value: 54 } # statistics accumulator user_width in bits: W_statistic = 64
+ - { name: g_stat_data_sz, value: 2 } # statistics accumulator user_width in 32b MM words: W_statistic_sz = 2
mm_ports:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
@@ -93,7 +93,7 @@ peripherals:
fields:
- - field_name: power
field_description: ""
- width: 32
+ mm_width: 32
user_width: g_stat_data_w
address_offset: 0x0
number_of_fields: g_nof_stat * g_stat_data_sz
diff --git a/libraries/io/aduh/aduh.peripheral.yaml b/libraries/io/aduh/aduh.peripheral.yaml
index c364451f0f3de254af4406b59b016b9535923307..83c37cd7e7dbad3dd50b3c5dbf5b50aa29378f6e 100644
--- a/libraries/io/aduh/aduh.peripheral.yaml
+++ b/libraries/io/aduh/aduh.peripheral.yaml
@@ -53,7 +53,7 @@ peripherals:
fields:
- - field_name: data
field_description: ""
- width: g_symbol_w * g_nof_symbols_per_data
+ mm_width: g_symbol_w * g_nof_symbols_per_data
address_offset: 0x0
number_of_fields: g_buffer_nof_symbols / g_nof_symbols_per_data
diff --git a/libraries/io/epcs/epcs.peripheral.yaml b/libraries/io/epcs/epcs.peripheral.yaml
index 2026d2bdf28c1bf9ae67ec48f00edf13fb94b0f5..a0cd36b980cbef177fd8c0b0f8a2176cd50768f4 100644
--- a/libraries/io/epcs/epcs.peripheral.yaml
+++ b/libraries/io/epcs/epcs.peripheral.yaml
@@ -27,45 +27,45 @@ peripherals:
fields:
- - field_name: addr
field_description: "Address to write to or read from."
- width: 24
+ mm_width: 24
access_mode: WO
address_offset: 0x0
- - field_name: rden
field_description: "Read enable bit."
- width: 1
+ mm_width: 1
access_mode: WO
address_offset: 0x4
- - field_name: read_bit
field_description: "Read bit."
- width: 1
+ mm_width: 1
access_mode: WO
side_effect: PW
address_offset: 0x8
- - field_name: write_bit
field_description: "Write bit."
- width: 1
+ mm_width: 1
access_mode: WO
side_effect: PW
address_offset: 0xc
- - field_name: sector_erase
field_description: "Sector erase bit."
- width: 1
+ mm_width: 1
access_mode: WO
address_offset: 0x10
- - field_name: busy
field_description: "Busy bit."
- width: 1
+ mm_width: 1
access_mode: RO
address_offset: 0x14
- - field_name: unprotect
field_description: "Use 0xBEDA221E (= Bedazzle) as password to unprotect address range."
- width: 32
+ mm_width: 32
access_mode: WO
address_offset: 0x18
diff --git a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
index 704335142b480d22362f0fec75559eede8bdea8e..768fc28810ecf90f9c87c1f2fc03047f1c905048 100644
--- a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
+++ b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
@@ -31,120 +31,120 @@ peripherals:
mm_port_description: "MAC registers"
number_of_mm_ports: g_nof_macs
fields:
- - - {field_name: rx_transfer_control, width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
- - - {field_name: rx_transfer_status, width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
- - - {field_name: rx_padcrc_control, width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
- - - {field_name: rx_crccheck_control, width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
- - - {field_name: rx_pktovrflow_error, width: 32, user_width: 36, access_mode: RO, address_offset: 0x0300 } # = 0x00C0
- - - {field_name: rx_pktovrflow_etherStatsDropEvents, width: 32, user_width: 36, access_mode: RO, address_offset: 0x0308 } # = 0x00C2
- - - {field_name: rx_lane_decoder_preamble_control, width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
- - - {field_name: rx_preamble_inserter_control, width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
- - - {field_name: rx_frame_control, width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
- - - {field_name: rx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
- - - {field_name: rx_frame_addr0, width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
- - - {field_name: rx_frame_addr1, width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
- - - {field_name: rx_frame_spaddr0_0, width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
- - - {field_name: rx_frame_spaddr0_1, width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
- - - {field_name: rx_frame_spaddr1_0, width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
- - - {field_name: rx_frame_spaddr1_1, width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
- - - {field_name: rx_frame_spaddr2_0, width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
- - - {field_name: rx_frame_spaddr2_1, width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
- - - {field_name: rx_frame_spaddr3_0, width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
- - - {field_name: rx_frame_spaddr3_1, width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
- - - {field_name: rx_pfc_control, width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
- - - {field_name: tx_transfer_control, width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
- - - {field_name: tx_transfer_status, width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
- - - {field_name: tx_padins_control, width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
- - - {field_name: tx_crcins_control, width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
- - - {field_name: tx_pktunderflow_error, width: 32, user_width: 36, access_mode: RO, address_offset: 0x4300 } # = 0x10C0
- - - {field_name: tx_preamble_control, width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
- - - {field_name: tx_pauseframe_control, width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
- - - {field_name: tx_pauseframe_quanta, width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
- - - {field_name: tx_pauseframe_enable, width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
+ - - {field_name: rx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
+ - - {field_name: rx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
+ - - {field_name: rx_padcrc_control, mm_width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
+ - - {field_name: rx_crccheck_control, mm_width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
+ - - {field_name: rx_pktovrflow_error, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x0300 } # = 0x00C0
+ - - {field_name: rx_pktovrflow_etherStatsDropEvents, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x0308 } # = 0x00C2
+ - - {field_name: rx_lane_decoder_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
+ - - {field_name: rx_preamble_inserter_control, mm_width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
+ - - {field_name: rx_frame_control, mm_width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
+ - - {field_name: rx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
+ - - {field_name: rx_frame_addr0, mm_width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
+ - - {field_name: rx_frame_addr1, mm_width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
+ - - {field_name: rx_frame_spaddr0_0, mm_width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
+ - - {field_name: rx_frame_spaddr0_1, mm_width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
+ - - {field_name: rx_frame_spaddr1_0, mm_width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
+ - - {field_name: rx_frame_spaddr1_1, mm_width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
+ - - {field_name: rx_frame_spaddr2_0, mm_width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
+ - - {field_name: rx_frame_spaddr2_1, mm_width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
+ - - {field_name: rx_frame_spaddr3_0, mm_width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
+ - - {field_name: rx_frame_spaddr3_1, mm_width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
+ - - {field_name: rx_pfc_control, mm_width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
+ - - {field_name: tx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
+ - - {field_name: tx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
+ - - {field_name: tx_padins_control, mm_width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
+ - - {field_name: tx_crcins_control, mm_width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
+ - - {field_name: tx_pktunderflow_error, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x4300 } # = 0x10C0
+ - - {field_name: tx_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
+ - - {field_name: tx_pauseframe_control, mm_width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
+ - - {field_name: tx_pauseframe_quanta, mm_width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
+ - - {field_name: tx_pauseframe_enable, mm_width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
# Altera is unclear about the width of the quanta registers. Assuming 32 bits, where bits 16:31 are reserved:
- - - {field_name: pfc_pause_quanta_0, width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
- - - {field_name: pfc_pause_quanta_1, width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
- - - {field_name: pfc_pause_quanta_2, width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
- - - {field_name: pfc_pause_quanta_3, width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
- - - {field_name: pfc_pause_quanta_4, width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
- - - {field_name: pfc_pause_quanta_5, width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
- - - {field_name: pfc_pause_quanta_6, width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
- - - {field_name: pfc_pause_quanta_7, width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
- - - {field_name: pfc_holdoff_quanta_0, width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
- - - {field_name: pfc_holdoff_quanta_1, width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
- - - {field_name: pfc_holdoff_quanta_2, width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
- - - {field_name: pfc_holdoff_quanta_3, width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
- - - {field_name: pfc_holdoff_quanta_4, width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
- - - {field_name: pfc_holdoff_quanta_5, width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
- - - {field_name: pfc_holdoff_quanta_6, width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
- - - {field_name: pfc_holdoff_quanta_7, width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
- - - {field_name: tx_pfc_priority_enable, width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
- - - {field_name: tx_addrins_control, width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
- - - {field_name: tx_addrins_macaddr0, width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
- - - {field_name: tx_addrins_macaddr1, width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
- - - {field_name: tx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
- - - {field_name: rx_stats_clr, width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
- - - {field_name: tx_stats_clr, width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
- - - {field_name: rx_stats_framesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3008 } # = 0x0C02
- - - {field_name: tx_stats_framesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7008 } # = 0x1C02
- - - {field_name: rx_stats_framesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3010 } # = 0x0C04
- - - {field_name: tx_stats_framesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7010 } # = 0x1C04
- - - {field_name: rx_stats_framesCRCErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3018 } # = 0x0C06
- - - {field_name: tx_stats_framesCRCErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7018 } # = 0x1C06
- - - {field_name: rx_stats_octetsOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3020 } # = 0x0C08
- - - {field_name: tx_stats_octetsOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7020 } # = 0x1C08
- - - {field_name: rx_stats_pauseMACCtrl_Frames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3028 } # = 0x0C0A
- - - {field_name: tx_stats_pauseMACCtrl_Frames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7028 } # = 0x1C0A
- - - {field_name: rx_stats_ifErrors, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3030 } # = 0x0C0C
- - - {field_name: tx_stats_ifErrors, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7030 } # = 0x1C0C
- - - {field_name: rx_stats_unicast_FramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3038 } # = 0x0C0E
- - - {field_name: tx_stats_unicast_FramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7038 } # = 0x1C0E
- - - {field_name: rx_stats_unicast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3040 } # = 0x0C10
- - - {field_name: tx_stats_unicast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7040 } # = 0x1C10
- - - {field_name: rx_stats_multicastFramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3048 } # = 0x0C12
- - - {field_name: tx_stats_multicastFramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7048 } # = 0x1C12
- - - {field_name: rx_stats_multicast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3050 } # = 0x0C14
- - - {field_name: tx_stats_multicast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7050 } # = 0x1C14
- - - {field_name: rx_stats_broadcastFramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3058 } # = 0x0C16
- - - {field_name: tx_stats_broadcastFramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7058 } # = 0x1C16
- - - {field_name: rx_stats_broadcast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3060 } # = 0x0C18
- - - {field_name: tx_stats_broadcast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7060 } # = 0x1C18
- - - {field_name: rx_stats_etherStatsOctets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3068 } # = 0x0C1A
- - - {field_name: tx_stats_etherStatsOctets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7068 } # = 0x1C1A
- - - {field_name: rx_stats_etherStatsPkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3070 } # = 0x0C1C
- - - {field_name: tx_stats_etherStatsPkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7070 } # = 0x1C1C
- - - {field_name: rx_stats_etherStats_UndersizePkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3078 } # = 0x0C1E
- - - {field_name: tx_stats_etherStats_UndersizePkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7078 } # = 0x1C1E
- - - {field_name: rx_stats_etherStats_OversizePkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3080 } # = 0x0C20
- - - {field_name: tx_stats_etherStats_OversizePkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7080 } # = 0x1C20
- - - {field_name: rx_stats_etherStats_Pkts64Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3088 } # = 0x0C22
- - - {field_name: tx_stats_etherStats_Pkts64Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7088 } # = 0x1C22
- - - {field_name: rx_stats_etherStats_Pkts65to127Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3090 } # = 0x0C24
- - - {field_name: tx_stats_etherStats_Pkts65to127Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7090 } # = 0x1C24
- - - {field_name: rx_stats_etherStats_Pkts128to255Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3098 } # = 0x0C26
- - - {field_name: tx_stats_etherStats_Pkts128to255Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7098 } # = 0x1C26
- - - {field_name: rx_stats_etherStats_Pkts256to511Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30a0 } # = 0x0C28
- - - {field_name: tx_stats_etherStats_Pkts256to511Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70a0 } # = 0x1C28
- - - {field_name: rx_stats_etherStats_Pkts512to1023Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30a8 } # = 0x0C2A
- - - {field_name: tx_stats_etherStats_Pkts512to1023Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70a8 } # = 0x1C2A
- - - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30b0 } # = 0x0C2C
- - - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70b0 } # = 0x1C2C
- - - {field_name: rx_stats_etherStats_Pkts1519toXOctets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30b8 } # = 0x0C2E
- - - {field_name: tx_stats_etherStats_Pkts1519toXOctets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70b8 } # = 0x1C2E
- - - {field_name: rx_stats_etherStats_Fragments, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30c0 } # = 0x0C30
- - - {field_name: tx_stats_etherStats_Fragments, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70c0 } # = 0x1C30
- - - {field_name: rx_stats_etherStats_Jabbers, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30c8 } # = 0x0C32
- - - {field_name: tx_stats_etherStats_Jabbers, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70c8 } # = 0x1C32
- - - {field_name: rx_stats_etherStatsCRCErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30d0 } # = 0x0C34
- - - {field_name: tx_stats_etherStatsCRCErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70d0 } # = 0x1C34
- - - {field_name: rx_stats_unicastMACCtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30d8 } # = 0x0C36
- - - {field_name: tx_stats_unicastMACCtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70d8 } # = 0x1C36
- - - {field_name: rx_stats_multicastMAC_CtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30e0 } # = 0x0C38
- - - {field_name: tx_stats_multicastMAC_CtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70e0 } # = 0x1C38
- - - {field_name: rx_stats_broadcastMAC_CtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30e8 } # = 0x0C3A
- - - {field_name: tx_stats_broadcastMAC_CtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70e8 } # = 0x1C3A
- - - {field_name: rx_stats_PFCMACCtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30f0 } # = 0x0C3C
- - - {field_name: tx_stats_PFCMACCtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70f0 } # = 0x1C3C
+ - - {field_name: pfc_pause_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
+ - - {field_name: pfc_pause_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
+ - - {field_name: pfc_pause_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
+ - - {field_name: pfc_pause_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
+ - - {field_name: pfc_pause_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
+ - - {field_name: pfc_pause_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
+ - - {field_name: pfc_pause_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
+ - - {field_name: pfc_pause_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
+ - - {field_name: pfc_holdoff_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
+ - - {field_name: pfc_holdoff_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
+ - - {field_name: pfc_holdoff_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
+ - - {field_name: pfc_holdoff_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
+ - - {field_name: pfc_holdoff_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
+ - - {field_name: pfc_holdoff_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
+ - - {field_name: pfc_holdoff_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
+ - - {field_name: pfc_holdoff_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
+ - - {field_name: tx_pfc_priority_enable, mm_width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
+ - - {field_name: tx_addrins_control, mm_width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
+ - - {field_name: tx_addrins_macaddr0, mm_width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
+ - - {field_name: tx_addrins_macaddr1, mm_width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
+ - - {field_name: tx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
+ - - {field_name: rx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
+ - - {field_name: tx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
+ - - {field_name: rx_stats_framesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3008 } # = 0x0C02
+ - - {field_name: tx_stats_framesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7008 } # = 0x1C02
+ - - {field_name: rx_stats_framesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3010 } # = 0x0C04
+ - - {field_name: tx_stats_framesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7010 } # = 0x1C04
+ - - {field_name: rx_stats_framesCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3018 } # = 0x0C06
+ - - {field_name: tx_stats_framesCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7018 } # = 0x1C06
+ - - {field_name: rx_stats_octetsOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3020 } # = 0x0C08
+ - - {field_name: tx_stats_octetsOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7020 } # = 0x1C08
+ - - {field_name: rx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3028 } # = 0x0C0A
+ - - {field_name: tx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7028 } # = 0x1C0A
+ - - {field_name: rx_stats_ifErrors, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3030 } # = 0x0C0C
+ - - {field_name: tx_stats_ifErrors, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7030 } # = 0x1C0C
+ - - {field_name: rx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3038 } # = 0x0C0E
+ - - {field_name: tx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7038 } # = 0x1C0E
+ - - {field_name: rx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3040 } # = 0x0C10
+ - - {field_name: tx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7040 } # = 0x1C10
+ - - {field_name: rx_stats_multicastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3048 } # = 0x0C12
+ - - {field_name: tx_stats_multicastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7048 } # = 0x1C12
+ - - {field_name: rx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3050 } # = 0x0C14
+ - - {field_name: tx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7050 } # = 0x1C14
+ - - {field_name: rx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3058 } # = 0x0C16
+ - - {field_name: tx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7058 } # = 0x1C16
+ - - {field_name: rx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3060 } # = 0x0C18
+ - - {field_name: tx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7060 } # = 0x1C18
+ - - {field_name: rx_stats_etherStatsOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3068 } # = 0x0C1A
+ - - {field_name: tx_stats_etherStatsOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7068 } # = 0x1C1A
+ - - {field_name: rx_stats_etherStatsPkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3070 } # = 0x0C1C
+ - - {field_name: tx_stats_etherStatsPkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7070 } # = 0x1C1C
+ - - {field_name: rx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3078 } # = 0x0C1E
+ - - {field_name: tx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7078 } # = 0x1C1E
+ - - {field_name: rx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3080 } # = 0x0C20
+ - - {field_name: tx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7080 } # = 0x1C20
+ - - {field_name: rx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3088 } # = 0x0C22
+ - - {field_name: tx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7088 } # = 0x1C22
+ - - {field_name: rx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3090 } # = 0x0C24
+ - - {field_name: tx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7090 } # = 0x1C24
+ - - {field_name: rx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x3098 } # = 0x0C26
+ - - {field_name: tx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x7098 } # = 0x1C26
+ - - {field_name: rx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30a0 } # = 0x0C28
+ - - {field_name: tx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70a0 } # = 0x1C28
+ - - {field_name: rx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30a8 } # = 0x0C2A
+ - - {field_name: tx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70a8 } # = 0x1C2A
+ - - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30b0 } # = 0x0C2C
+ - - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70b0 } # = 0x1C2C
+ - - {field_name: rx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30b8 } # = 0x0C2E
+ - - {field_name: tx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70b8 } # = 0x1C2E
+ - - {field_name: rx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30c0 } # = 0x0C30
+ - - {field_name: tx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70c0 } # = 0x1C30
+ - - {field_name: rx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30c8 } # = 0x0C32
+ - - {field_name: tx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70c8 } # = 0x1C32
+ - - {field_name: rx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30d0 } # = 0x0C34
+ - - {field_name: tx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70d0 } # = 0x1C34
+ - - {field_name: rx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30d8 } # = 0x0C36
+ - - {field_name: tx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70d8 } # = 0x1C36
+ - - {field_name: rx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30e0 } # = 0x0C38
+ - - {field_name: tx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70e0 } # = 0x1C38
+ - - {field_name: rx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30e8 } # = 0x0C3A
+ - - {field_name: tx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70e8 } # = 0x1C3A
+ - - {field_name: rx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x30f0 } # = 0x0C3C
+ - - {field_name: tx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, access_mode: RO, address_offset: 0x70f0 } # = 0x1C3C
- peripheral_name: nw_10GbE_eth10g # pi_nw_10GbE_eth10g.py / pi_10GbE.py
@@ -161,19 +161,19 @@ peripherals:
fields:
- - field_name: tx_snk_out_xon
field_description: ""
- width: 1
+ mm_width: 1
bit_offset: 0
access_mode: RO
address_offset: 0x0
- - field_name: xgmii_tx_ready
field_description: ""
- width: 1
+ mm_width: 1
bit_offset: 1
access_mode: RO
address_offset: 0x0
- - field_name: xgmii_link_status
field_description: ""
- width: 2
+ mm_width: 2
bit_offset: 2
access_mode: RO
address_offset: 0x0
diff --git a/libraries/io/ppsh/ppsh.peripheral.yaml b/libraries/io/ppsh/ppsh.peripheral.yaml
index e732647b7504398f8be33e9bb3c96763b2d1396b..c04c8fffc46255c29e00d050d890f69558810f5a 100644
--- a/libraries/io/ppsh/ppsh.peripheral.yaml
+++ b/libraries/io/ppsh/ppsh.peripheral.yaml
@@ -27,35 +27,35 @@ peripherals:
fields:
- - field_name: capture_cnt
field_description: "Measured number of clock cycles between captured PPS pulses."
- width: 30
+ mm_width: 30
bit_offset: 0
access_mode: RO
address_offset: 0x0
- - field_name: stable
field_description: "PPS is stable (1) when capture_cnt = expected_cnt for all PPS periods since last time status was read, else PPS is not stable (0)."
- width: 1
+ mm_width: 1
bit_offset: 30
access_mode: RO
address_offset: 0x0
- - field_name: toggle
field_description: "Level bit that toggles after every PPS."
- width: 1
+ mm_width: 1
bit_offset: 31
access_mode: RO
address_offset: 0x0
- - field_name: expected_cnt
field_description: "Expected number of clock cycles between captured PPS pulses."
- width: ceil_log2(g_st_clk_freq)
+ mm_width: ceil_log2(g_st_clk_freq)
bit_offset: 0
access_mode: RW
address_offset: 0x4
- - field_name: edge
field_description: "When 0 then clock PPS in on rising edge of clock, else when 1 use falling edge of clock."
- width: 1
+ mm_width: 1
bit_offset: 31
access_mode: RW
address_offset: 0x4
@@ -63,6 +63,6 @@ peripherals:
- - field_name: offset_cnt
field_description: "Number of clock cycles at read access, that has passed since last PPS."
address_offset: 0x8
- width: ceil_log2(g_st_clk_freq)
+ mm_width: ceil_log2(g_st_clk_freq)
access_mode: RO
diff --git a/libraries/io/remu/remu.peripheral.yaml b/libraries/io/remu/remu.peripheral.yaml
index eb13be5b392fb259f245e132111fe583b06b5837..a2e8775b11d4f7c540ea6fd38a1215051e6c7e81 100644
--- a/libraries/io/remu/remu.peripheral.yaml
+++ b/libraries/io/remu/remu.peripheral.yaml
@@ -24,45 +24,45 @@ peripherals:
fields:
- - field_name: reconfigure
field_description: "Use 0xB007FAC7 (= boot factory) as password to reconfigure."
- width: c_word_w
+ mm_width: c_word_w
access_mode: WO
address_offset: 0x0
- - field_name: param
field_description: "param"
- width: 3
+ mm_width: 3
access_mode: WO
address_offset: 0x4
- - field_name: read_param
field_description: "read_param"
- width: 1
+ mm_width: 1
access_mode: WO
side_effect: PW
address_offset: 0x8
- - field_name: write_param
field_description: "write_param"
- width: 1
+ mm_width: 1
access_mode: WO
side_effect: PW
address_offset: 0xc
- - field_name: data_out
field_description: "data_out"
- width: g_data_w
+ mm_width: g_data_w
access_mode: RO
address_offset: 0x10
- - field_name: data_in
field_description: "data_in"
- width: g_data_w
+ mm_width: g_data_w
access_mode: WO
address_offset: 0x14
- - field_name: busy
field_description: "busy"
- width: 1
+ mm_width: 1
access_mode: RO
address_offset: 0x18
diff --git a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
index 4c748e535c27266b3077edf9f05275364aedd2d1..2fe119edf4f93399e7732af647922fc73ed66582 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
+++ b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
@@ -16,13 +16,13 @@ peripherals:
fields:
- - field_name: reset
field_description: "Write 1 to reset the full JESD interface for all JESD signal inputs."
- width: 1
+ mm_width: 1
bit_offset: 31
access_mode: RW
address_offset: 0x0
- - field_name: enable
field_description: "Enable JESD signal input i by setting bit i = 1, disable by clearing bit i = 0."
- width: 31
+ mm_width: 31
bit_offset: 0
access_mode: RW
address_offset: 0x0
@@ -36,31 +36,31 @@ peripherals:
mm_port_type: REG
mm_port_description: ""
fields:
- - - {field_name: rx_dll_ctrl, width: 17, bit_offset: 0, access_mode: RW, address_offset: 0x50}
- - - {field_name: rx_syncn_sysref_ctrl, width: 25, bit_offset: 0, access_mode: RW, address_offset: 0x54}
- - - {field_name: rx_csr_lmfc_offset, width: 8, bit_offset: 12, access_mode: RW, address_offset: 0x54}
- - - {field_name: rx_csr_rbd_offset, width: 8, bit_offset: 3, access_mode: RW, address_offset: 0x54}
- - - {field_name: rx_csr_sysref_always_on, width: 1, bit_offset: 1, access_mode: RW, address_offset: 0x54}
- - - {field_name: rx_err0, width: 9, bit_offset: 0, access_mode: RW, address_offset: 0x60}
- - - {field_name: rx_err1, width: 10, bit_offset: 0, access_mode: RW, address_offset: 0x64}
- - - {field_name: csr_rbd_count, width: 8, bit_offset: 3, access_mode: RO, address_offset: 0x80}
- - - {field_name: csr_dev_syncn, width: 1, bit_offset: 0, access_mode: RO, address_offset: 0x80}
- - - {field_name: rx_status1, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x84}
- - - {field_name: rx_status2, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x88}
- - - {field_name: rx_status3, width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x8C}
- - - {field_name: rx_ilas_csr_m, width: 8, bit_offset: 24, access_mode: RW, address_offset: 0x94}
- - - {field_name: rx_ilas_csr_k, width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x94}
- - - {field_name: rx_ilas_csr_f, width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x94}
- - - {field_name: rx_ilas_csr_l, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x94}
- - - {field_name: rx_ilas_csr_hd, width: 1, bit_offset: 31, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_cf, width: 5, bit_offset: 24, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_jesdv, width: 3, bit_offset: 21, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_s, width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_subclassv, width: 3, bit_offset: 13, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_np, width: 5, bit_offset: 8, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_cs, width: 2, bit_offset: 6, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_n, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_status4, width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF0}
- - - {field_name: rx_status5, width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF4}
- - - {field_name: rx_status6, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0xF8}
- - - {field_name: rx_status7, width: 32, bit_offset: 0, access_mode: RO, address_offset: 0xFC}
+ - - {field_name: rx_dll_ctrl, mm_width: 17, bit_offset: 0, access_mode: RW, address_offset: 0x50}
+ - - {field_name: rx_syncn_sysref_ctrl, mm_width: 25, bit_offset: 0, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_lmfc_offset, mm_width: 8, bit_offset: 12, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_rbd_offset, mm_width: 8, bit_offset: 3, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_sysref_always_on, mm_width: 1, bit_offset: 1, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_err0, mm_width: 9, bit_offset: 0, access_mode: RW, address_offset: 0x60}
+ - - {field_name: rx_err1, mm_width: 10, bit_offset: 0, access_mode: RW, address_offset: 0x64}
+ - - {field_name: csr_rbd_count, mm_width: 8, bit_offset: 3, access_mode: RO, address_offset: 0x80}
+ - - {field_name: csr_dev_syncn, mm_width: 1, bit_offset: 0, access_mode: RO, address_offset: 0x80}
+ - - {field_name: rx_status1, mm_width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x84}
+ - - {field_name: rx_status2, mm_width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x88}
+ - - {field_name: rx_status3, mm_width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x8C}
+ - - {field_name: rx_ilas_csr_m, mm_width: 8, bit_offset: 24, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_k, mm_width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_f, mm_width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_l, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_hd, mm_width: 1, bit_offset: 31, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_cf, mm_width: 5, bit_offset: 24, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_jesdv, mm_width: 3, bit_offset: 21, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_s, mm_width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_subclassv, mm_width: 3, bit_offset: 13, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_np, mm_width: 5, bit_offset: 8, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_cs, mm_width: 2, bit_offset: 6, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_n, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_status4, mm_width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF0}
+ - - {field_name: rx_status5, mm_width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF4}
+ - - {field_name: rx_status6, mm_width: 24, bit_offset: 0, access_mode: RW, address_offset: 0xF8}
+ - - {field_name: rx_status7, mm_width: 32, bit_offset: 0, access_mode: RO, address_offset: 0xFC}