From 7b7329cac7935655d216d92c78bc041011fca806 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 10 Apr 2015 12:13:26 +0000
Subject: [PATCH] Use default reg_io_ddr_mosi input value to allow not
connecting it.
---
libraries/io/ddr/src/vhdl/io_ddr.vhd | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 35a0f996a9..270cd0d619 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -181,11 +181,11 @@ ENTITY io_ddr IS
ctlr_rst_in : IN STD_LOGIC; -- connect ctlr_rst_out to ctlr_rst_in at top level
-- MM clock + reset
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC := '1';
+ mm_clk : IN STD_LOGIC := '0';
- -- MM register map for DDR controller status info
- reg_io_ddr_mosi : IN t_mem_mosi;
+ -- MM interface
+ reg_io_ddr_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- register for DDR controller status info
reg_io_ddr_miso : OUT t_mem_miso;
-- Driver clock domain
--
GitLab