diff --git a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
index 1c30f85c5def51b858e5e9d54ef0649fa5c406e9..aa28a3132f03411a44f9c4c11e42ce395cf56dc4 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
@@ -33,6 +33,7 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY corr_accumulator IS
GENERIC (
+ g_sim : BOOLEAN;
g_nof_inputs : NATURAL; -- Number of input streams
g_nof_accumulators : NATURAL; -- Number of accumulators to keep per input stream
g_integration_period : NATURAL; -- Number of timesamples to accumulate
@@ -77,7 +78,6 @@ ARCHITECTURE str OF corr_accumulator IS
SIGNAL dp_block_gen_snk_in_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
SIGNAL dp_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
- SIGNAL nxt_dp_block_gen_snk_in_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
SIGNAL sim_snk_in_val_cnt : NATURAL;
SIGNAL nxt_sim_snk_in_val_cnt : NATURAL;
@@ -167,10 +167,10 @@ BEGIN
-- of zeros initially.
-----------------------------------------------------------------------------
gen_src_out_arr : FOR i IN 0 TO g_nof_inputs-1 GENERATE
- nxt_dp_block_gen_snk_in_arr(i).re <= RESIZE_DP_DSP_DATA(dp_fifo_sc_src_out_arr(i).re);
- nxt_dp_block_gen_snk_in_arr(i).im <= RESIZE_DP_DSP_DATA(dp_fifo_sc_src_out_arr(i).im);
+ dp_block_gen_snk_in_arr(i).re <= RESIZE_DP_DSP_DATA(dp_fifo_sc_src_out_arr(i).re);
+ dp_block_gen_snk_in_arr(i).im <= RESIZE_DP_DSP_DATA(dp_fifo_sc_src_out_arr(i).im);
- nxt_dp_block_gen_snk_in_arr(i).valid <= '1' WHEN TO_UINT(acc_cnt_arr(i))<g_nof_accumulators AND dp_fifo_sc_src_out_arr(i).valid='1' ELSE '0';
+ dp_block_gen_snk_in_arr(i).valid <= '1' WHEN TO_UINT(acc_cnt_arr(i))<g_nof_accumulators AND dp_fifo_sc_src_out_arr(i).valid='1' ELSE '0';
END GENERATE;
END GENERATE;
@@ -193,11 +193,11 @@ BEGIN
FOR i IN 0 TO g_nof_inputs-1 LOOP
IF snk_in_arr(i).valid = '1' AND sim_snk_in_val_cnt<g_nof_accumulators THEN
- nxt_dp_block_gen_snk_in_arr(i).re <= RESIZE_DP_DSP_DATA(TO_SVEC(g_integration_period*TO_SINT(snk_in_arr(i).re),c_acc_data_w));
- nxt_dp_block_gen_snk_in_arr(i).im <= RESIZE_DP_DSP_DATA(TO_SVEC(g_integration_period*TO_SINT(snk_in_arr(i).im),c_acc_data_w));
- nxt_dp_block_gen_snk_in_arr(i).valid <= '1';
+ dp_block_gen_snk_in_arr(i).re <= RESIZE_DP_DSP_DATA(TO_SVEC(g_integration_period*TO_SINT(snk_in_arr(i).re),c_acc_data_w));
+ dp_block_gen_snk_in_arr(i).im <= RESIZE_DP_DSP_DATA(TO_SVEC(g_integration_period*TO_SINT(snk_in_arr(i).im),c_acc_data_w));
+ dp_block_gen_snk_in_arr(i).valid <= '1';
ELSE
- nxt_dp_block_gen_snk_in_arr(i) <= c_dp_sosi_rst;
+ dp_block_gen_snk_in_arr(i) <= c_dp_sosi_rst;
END IF;
END LOOP;
END PROCESS;
@@ -207,23 +207,29 @@ BEGIN
-----------------------------------------------------------------------------
-- Add SOP and EOP for easier verification
-----------------------------------------------------------------------------
- gen_dp_block_gen : FOR i IN 0 TO g_nof_inputs-1 GENERATE
- u_dp_block_gen: ENTITY dp_lib.dp_block_gen
- GENERIC MAP (
- g_use_src_in => FALSE,
- g_nof_data => g_nof_accumulators,
- g_nof_blk_per_sync => g_integration_period
- )
- PORT MAP (
- rst => rst,
- clk => clk,
+ gen_sim_sop_eop : IF g_sim = TRUE GENERATE
+ gen_dp_block_gen : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+ u_dp_block_gen: ENTITY dp_lib.dp_block_gen
+ GENERIC MAP (
+ g_use_src_in => FALSE,
+ g_nof_data => g_nof_accumulators,
+ g_nof_blk_per_sync => g_integration_period
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_block_gen_snk_in_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
+ END GENERATE;
- snk_in => dp_block_gen_snk_in_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ src_out_arr <= dp_block_gen_src_out_arr;
END GENERATE;
- src_out_arr <= dp_block_gen_src_out_arr;
+ no_sim_sop_eop : IF g_sim = FALSE GENERATE
+ src_out_arr <= dp_block_gen_snk_in_arr;
+ END GENERATE;
-----------------------------------------------------------------------------
-- Registers
@@ -234,13 +240,11 @@ BEGIN
acc_cnt_arr <= (OTHERS=>(OTHERS=>'0'));
corr_adder_snk_in_2arr_2 <= (OTHERS=>(OTHERS=>c_dp_sosi_rst));
reg_snk_in_arr <= (OTHERS=>c_dp_sosi_rst);
- dp_block_gen_snk_in_arr <= (OTHERS=>c_dp_sosi_rst);
sim_snk_in_val_cnt <= 0;
ELSIF rising_edge(clk) THEN
acc_cnt_arr <= nxt_acc_cnt_arr;
corr_adder_snk_in_2arr_2 <= nxt_corr_adder_snk_in_2arr_2;
reg_snk_in_arr <= snk_in_arr;
- dp_block_gen_snk_in_arr <= nxt_dp_block_gen_snk_in_arr;
sim_snk_in_val_cnt <= nxt_sim_snk_in_val_cnt;
END IF;
END PROCESS;
diff --git a/libraries/dsp/correlator/src/vhdl/correlator.vhd b/libraries/dsp/correlator/src/vhdl/correlator.vhd
index 09800c098999a2dbf195ebd65b07e69fbeb70bac..7e2f6d9a6007181f403aea125763e20756b22d7d 100644
--- a/libraries/dsp/correlator/src/vhdl/correlator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/correlator.vhd
@@ -32,6 +32,7 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY correlator IS
GENERIC (
+ g_sim : BOOLEAN;
g_nof_input_streams : NATURAL;
g_input_unfold_factor : NATURAL := 0; -- 2**g_input_unfold_factor = number of inputs carried on one input stream
g_nof_pre_mult_folds : NATURAL := 0; -- Number of pre-multiplier stage folds.
@@ -250,6 +251,7 @@ BEGIN
-----------------------------------------------------------------------------
u_corr_accumulator : ENTITY work.corr_accumulator
GENERIC MAP (
+ g_sim => g_sim,
g_nof_inputs => c_nof_mults,
g_nof_accumulators => c_nof_accumulators,
g_integration_period => c_integration_period,
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
index cf57ad21d442b6a653da2bfcc2354e753f2ae96b..26a88542fb03d1c8e2f439ed48a6b46d319f4ed8 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
@@ -203,6 +203,7 @@ BEGIN
-----------------------------------------------------------------------------
u_correlator : ENTITY work.correlator
GENERIC MAP (
+ g_sim => TRUE,
g_nof_input_streams => c_nof_input_streams,
g_input_unfold_factor => g_nof_input_folds,
g_nof_pre_mult_folds => g_nof_pre_mult_folds,