diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml index af6d7597820a47f309ad1172cd801911690575cd..dc9b8b805a4c6f04e9da0b69b7b019340f280c6d 100644 --- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml +++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml @@ -8,14 +8,14 @@ hdl_library_description: "Station Digital Processor (SDP) for LOFAR2.0" peripherals: - peripheral_name: sdp_info # pi_sdp_info.py ? peripheral_description: "SDP info." - slave_ports: + mm_ports: # MM port for sdp_info.vhd - - slave_name: REG_SDP_INFO - slave_description: | + - mm_port_name: REG_SDP_INFO + mm_port_description: | "The SDP info contains central SDP information. The station_id applies to the entire station. The other info fields apply per antenna band (low band or high band). An FPGA node only participates in one band." - slave_type: REG + mm_port_type: REG fields: - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x0 } - - { field_name: antenna_band_index, width: 1, access_mode: RO, address_offset: 0x4 } @@ -38,18 +38,18 @@ peripherals: parameters: # Parameters of pi_sdp_subband_equalizer.py, fixed in sdp_subband_equalizer.vhd / sdp_pkg.vhd - { name: g_nof_instances, value: 6 } # P_pfb = S_pn / Q_fft = 12 / 2 = 6 - slave_ports: + mm_ports: # MM port for sdp_subband_equalizer.vhd - - slave_name: RAM_EQUALIZER_GAINS - slave_description: | + - mm_port_name: RAM_EQUALIZER_GAINS + mm_port_description: | "The subband weigths are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of Q_fft * N_sub = 2 * 512 = 1024 complex coefficients as: (cint16)subband_weights[S_pn/Q_fft]_[Q_fft][N_sub] where S_pn = 12, Q_fft = 2 and N_sub = 512 are defined in sdp_pkg.vhd." - slave_type: RAM - number_of_slaves: g_nof_instances + mm_port_type: RAM + number_of_mm_ports: g_nof_instances fields: - - field_name: coef field_description: | @@ -67,10 +67,10 @@ peripherals: # Parameters of pi_sdp_bf_weights.py, fixed in sdp_bf_weights.vhd / sdp_pkg.vhd - { name: g_nof_instances, value: 12 } # = N_pol_bf * P_pfb - { name: g_nof_gains, value: 976 } # = Q_fft * S_sub_bf - slave_ports: + mm_ports: # MM port for sdp_beamformer_local.vhd / sdp_bf_weights.vhd / mms_dp_gain_serial_arr.vhd - - slave_name: RAM_BF_WEIGHTS - slave_description: | + - mm_port_name: RAM_BF_WEIGHTS + mm_port_description: | "The beamlet weigths are stored in g_nof_instances = N_pol_bf * P_pfb = 2 * 6 = 12, where P_pfb = S_pn / Q_fft = 6. Per instance there is a block of Q_fft * S_sub_bf = 2 * 488 = 976 complex BF weights. The N_pol_bf = 2 represents the two beamformer @@ -96,8 +96,8 @@ peripherals: when index of N_pol_bf and index of N_pol are the same. The cross-polarization BF weights (XY, YX) are set when index of N_pol_bf and index of N_pol are different. If no cross-polarization weighting is needed, then these weights can be kept 0." - slave_type: RAM - number_of_slaves: g_nof_instances + mm_port_type: RAM + number_of_mm_ports: g_nof_instances fields: - - field_name: coef field_description: | @@ -115,10 +115,10 @@ peripherals: # Parameters fixed in node_sdp_beamformer.vhd / mms_dp_scale.vhd / sdp_pkg.vhd - { name: g_gain_w, value: 16 } - { name: g_lsb_w, value: 15 } - slave_ports: + mm_ports: # MM port for node_sdp_beamformer.vhd / mms_dp_scale.vhd / mms_dp_gain.vhd / mms_dp_gain_arr.vhd - - slave_name: REG_BF_SCALE - slave_description: | + - mm_port_name: REG_BF_SCALE + mm_port_description: | "The beamlet scale function scales the beamlet sum with a real scale factor and then requantizes the result to beamlet data output with less bits. The beamlet scale factor has g_gain_w bits and the value 2**g_lsb_w represents a gain of 1. @@ -129,7 +129,7 @@ peripherals: . 2**11 rounds the lowest 4 bits, selects the next 8 bits of the beamlet sum and clips the highest 6 bits, . 2**5 rounds the lowest 10 bits and selects the highest 8 bits of the beamlet sum." - slave_type: REG + mm_port_type: REG fields: - - field_name: scale field_description: "" @@ -146,10 +146,10 @@ peripherals: - peripheral_name: sdp_beamformer_output_hdr_dat # pi_dp_offload_tx_hdr_dat_lofar2_beamformer_output.py peripheral_description: "SDP BF beamlet data output header." - slave_ports: + mm_ports: # MM port for sdp_beamformer_output.vhd / dp_offload_tx_v3.vhd - - slave_name: REG_DP_OFFLOAD_TX_HDR_DAT - slave_description: | + - mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT + mm_port_description: | "The ETH/IP/UDP/application header fields for the beamlet data output offload UDP packets. The header fields are described in ICD STAT-CEP [1]. @@ -172,7 +172,7 @@ peripherals: 21 0x84 [31:0] = eth_dst_mac[31:0] 22 0x88 [15:0] = eth_dst_mac[47:32] " - slave_type: REG + mm_port_type: REG fields: # eth field group - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 } @@ -223,10 +223,10 @@ peripherals: - peripheral_name: sdp_statistics_offload_hdr_dat_sst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py peripheral_description: "SDP statistics offload header for the subband statistics (SST)." - slave_ports: + mm_ports: # MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd - - slave_name: REG_DP_OFFLOAD_TX_HDR_DAT - slave_description: | + - mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT + mm_port_description: | "The ETH/IP/UDP/application header fields for the SST offload UDP packets. The Subband statistics (SST) are integrated auto power values of the subbands per signal input. @@ -236,7 +236,7 @@ peripherals: [1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD " - slave_type: REG + mm_port_type: REG fields: # eth field group - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 } @@ -293,10 +293,10 @@ peripherals: - peripheral_name: sdp_statistics_offload_hdr_dat_bst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py peripheral_description: "SDP statistics offload header for the beamlet statistics (BST)." - slave_ports: + mm_ports: # MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd - - slave_name: REG_DP_OFFLOAD_TX_HDR_DAT - slave_description: | + - mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT + mm_port_description: | "The ETH/IP/UDP/application header fields for the BST offload UDP packets. The beamlet statistics (BST) are integrated auto power values of the beamlets per beamset @@ -306,7 +306,7 @@ peripherals: [1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD " - slave_type: REG + mm_port_type: REG fields: # eth field group - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 } @@ -363,10 +363,10 @@ peripherals: - peripheral_name: sdp_statistics_offload_hdr_dat_xst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py peripheral_description: "SDP statistics offload header for the cross-subband statistics (XST)." - slave_ports: + mm_ports: # MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd - - slave_name: REG_DP_OFFLOAD_TX_HDR_DAT - slave_description: | + - mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT + mm_port_description: | "The ETH/IP/UDP/application header fields for the XST offload UDP packets. The crosslet statistics (XST) are integrated cross power values of the subbands from all @@ -377,7 +377,7 @@ peripherals: [1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD " - slave_type: REG + mm_port_type: REG fields: # eth field group - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 } diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml index fbb717f3be92bedc7edc2edf2c8f484da390c21b..64ecbf278f19b1d721781f8656e88c3168a46dc2 100644 --- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml +++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml @@ -10,29 +10,29 @@ fpga_description: | peripherals: - peripheral_name: unb1_board/system - slave_port_names: + mm_port_names: - pio_system_info lock_base_address: 0x0 - peripheral_name: unb1_board/rom_system - slave_port_names: + mm_port_names: - rom_system_info lock_base_address: 0x1000 - peripheral_name: unb1_board/ctrl - slave_port_names: + mm_port_names: - pio_wdi - peripheral_name: unb1_board/wdi - slave_port_names: + mm_port_names: - reg_wdi - peripheral_name: eth/eth1g - slave_port_names: + mm_port_names: - avs_eth_0_tse - avs_eth_0_reg - avs_eth_0_ram - peripheral_name: ppsh/ppsh - slave_port_names: + mm_port_names: - pio_pps - peripheral_name: epcs/epcs - slave_port_names: + mm_port_names: - reg_epcs - reg_dpmm_ctrl - reg_dpmm_data @@ -41,10 +41,10 @@ peripherals: parameter_overrides: - { name : g_sim_flash_model, value: FALSE } - peripheral_name: remu/remu - slave_port_names: + mm_port_names: - reg_remu - peripheral_name: unb1_board/sens - slave_port_names: + mm_port_names: - reg_unb_sens parameter_overrides: - { name : g_sim, value: FALSE } diff --git a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml index eb6ec2e24c49510c75a88a64aa6432fbab490f5d..e85ac86d90071a13a312f2a805e5a9ac0be32bba 100644 --- a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml +++ b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml @@ -5,14 +5,14 @@ schema_type : peripheral hdl_library_name : unb1_board hdl_library_description: " This is the description for the unb1_board package " -# <peripheral_group>_<peripheral_name>_<slave_name>_<slave_type> +# <peripheral_group>_<peripheral_name>_<mm_port_name>_<mm_port_type> peripherals: - peripheral_name: rom_system - slave_ports: + mm_ports: # rom_system_info - - slave_name : info - slave_type : REG + - mm_port_name : info + mm_port_type : REG fields: - - field_name : info access_mode : RO @@ -20,16 +20,16 @@ peripherals: number_of_fields: 1024 field_description: | "address place for rom_system_info" - slave_description: " rom_info " + mm_port_description: " rom_info " peripheral_description: | " settings for rom_system_info register " - peripheral_name: system - slave_ports: + mm_ports: # reg_system_info - - slave_name : info - slave_type : REG + - mm_port_name : info + mm_port_type : REG fields: - - field_name : info access_mode : RO @@ -37,7 +37,7 @@ peripherals: number_of_fields: 32 field_description: | "address place for reg_system_info" - slave_description: " reg_info " + mm_port_description: " reg_info " peripheral_description: | " settings for reg_system_info register " @@ -45,10 +45,10 @@ peripherals: # peripheral, unb1_board_wdi_reg - peripheral_name: ctrl - slave_ports: + mm_ports: # actual hdl name: unb1_board_wdi_reg - - slave_name : pio_wdi - slave_type : REG + - mm_port_name : pio_wdi + mm_port_type : REG fields: - - field_name : nios_reset width : 32 @@ -57,24 +57,24 @@ peripherals: number_of_fields: 1 field_description: " Reset done by nios " - slave_description: "Reset register, for nios " + mm_port_description: "Reset register, for nios " peripheral_description: " " # peripheral, unb1_board_wdi_reg - peripheral_name: wdi - slave_ports: + mm_ports: # actual hdl name: unb1_board_wdi_reg - - slave_name : wdi - slave_type : REG + - mm_port_name : wdi + mm_port_type : REG fields: - - field_name : reset_word access_mode : WO address_offset: 0x0 field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset " - slave_description: "Reset register, if the right value is provided the factory image will be reloaded " + mm_port_description: "Reset register, if the right value is provided the factory image will be reloaded " peripheral_description: " " @@ -86,10 +86,10 @@ peripherals: - { name: g_clk_freq, value: c_unb1_board_mm_clk_freq_125M } - { name: g_temp_high, value: 85 } - slave_ports: + mm_ports: # actual hdl name: reg_unb1_sens - - slave_name : sens - slave_type : REG + - mm_port_name : sens + mm_port_type : REG fields: - - field_name : sens_data width : 8 @@ -117,7 +117,7 @@ peripherals: software_value: g_temp_high field_description: "" - slave_description: " " + mm_port_description: " " peripheral_description: | " diff --git a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml index d565fd51e20fcc034393508de0e0949b45f2fdc7..01243fd42502200dbbc1ec823b7c66f6cb3da100 100644 --- a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml +++ b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml @@ -11,49 +11,49 @@ peripherals: # Factory / minimal (from ctrl_unb2b_board.vhd) ############################################################################# - peripheral_name: unb2b_board/system_info - slave_port_names: + mm_port_names: - ROM_SYSTEM_INFO - PIO_SYSTEM_INFO lock_base_address: 0x10000 - peripheral_name: unb2b_board/wdi - slave_port_names: + mm_port_names: - PIO_WDI - peripheral_name: unb2b_board/unb2_fpga_sens - slave_port_names: + mm_port_names: - REG_FPGA_TEMP_SENS - REG_FPGA_VOLTAGE_SENS - peripheral_name: unb2b_board/ram_scrap - slave_port_names: + mm_port_names: - RAM_SCRAP - peripheral_name: eth/eth - slave_port_names: + mm_port_names: - AVS_ETH_0_TSE - AVS_ETH_0_REG - AVS_ETH_0_RAM - peripheral_name: ppsh/ppsh - slave_port_names: + mm_port_names: - PIO_PPS - peripheral_name: epcs/epcs - slave_port_names: + mm_port_names: - REG_EPCS - peripheral_name: dp/dpmm - slave_port_names: + mm_port_names: - REG_DPMM_CTRL - REG_DPMM_DATA - peripheral_name: dp/mmdp - slave_port_names: + mm_port_names: - REG_MMDP_CTRL - REG_MMDP_DATA - peripheral_name: remu/remu - slave_port_names: + mm_port_names: - REG_REMU diff --git a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml index b0fbfe3593fed32e2294895b053bd2a590eb965b..254ac5e1c7e182c50a91e78df03f08789fb39790 100644 --- a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml +++ b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml @@ -9,11 +9,11 @@ hdl_library_description: "Peripherals in unb2b_board." peripherals: - peripheral_name: ram_scrap # pi_ram_scrap.py peripheral_description: "" - slave_ports: + mm_ports: # MM port for common_ram_r_w.vhd - - slave_name: RAM_SCRAP - slave_type: RAM - slave_description: "One memory mapped block RAM for MM access test purposes." + - mm_port_name: RAM_SCRAP + mm_port_type: RAM + mm_port_description: "One memory mapped block RAM for MM access test purposes." fields: - - field_name: rw_data field_description: "Void data" @@ -23,12 +23,12 @@ peripherals: - peripheral_name: system_info # pi_system_info.py peripheral_description: "" - slave_ports: + mm_ports: # MM port for mms_unb2b_board_system_info.vhd / common_rom.vhd - - slave_name: ROM_SYSTEM_INFO # for c_rom_version = 1 in ctrl_unb2b_board.vhd - #- slave_name: ROM_SYSTEM_INFO_V2 # for c_rom_version = 2 in ctrl_unb2b_board.vhd - slave_type: RAM - slave_description: "Memory that stores the MM map system info of the mmap file." + - mm_port_name: ROM_SYSTEM_INFO # for c_rom_version = 1 in ctrl_unb2b_board.vhd + #- mm_port_name: ROM_SYSTEM_INFO_V2 # for c_rom_version = 2 in ctrl_unb2b_board.vhd + mm_port_type: RAM + mm_port_description: "Memory that stores the MM map system info of the mmap file." fields: - - field_name: ro_data field_description: "FPGA info memory map data" @@ -38,9 +38,9 @@ peripherals: radix: char # MM port for mms_unb2b_board_system_info.vhd / unb2b_board_system_info_reg.vhd - - slave_name: PIO_SYSTEM_INFO - slave_type: REG - slave_description: "FPGA design name, design note, version and location index info." + - mm_port_name: PIO_SYSTEM_INFO + mm_port_type: REG + mm_port_description: "FPGA design name, design note, version and location index info." fields: # All registers in one array #- - field_name: info @@ -137,11 +137,11 @@ peripherals: - peripheral_name: wdi # pi_wdi.py peripheral_description: "" - slave_ports: + mm_ports: # MM port for unb2b_board_wdi_reg.vhd - - slave_name: REG_WDI - slave_type: REG - slave_description: "Reset register, if the right value is provided the factory image will be reloaded in the FPGA." + - mm_port_name: REG_WDI + mm_port_type: REG + mm_port_description: "Reset register, if the right value is provided the factory image will be reloaded in the FPGA." fields: - - field_name: wdi_override field_description: "Write value 0xB007FAC7 = 'Boot factory' to disable the watchdog interrupt (WDI), to cause an FPGA image reload." @@ -150,11 +150,11 @@ peripherals: - peripheral_name: unb2_fpga_sens peripheral_description: "" - slave_ports: + mm_ports: # MM ports for mms_unb2b_fpga_sens.vhd / unb2b_fpga_sens_reg.vhd - - slave_name: REG_FPGA_TEMP_SENS # pi_unb_fpga_sens.py - slave_type: REG - slave_description: | + - mm_port_name: REG_FPGA_TEMP_SENS # pi_unb_fpga_sens.py + mm_port_type: REG + mm_port_description: | "FPGA temperature = (AxC)/1024 - B (where A=708; B=273; C=adc value), see page 10 in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_alttemp_sense.pdf" fields: @@ -164,9 +164,9 @@ peripherals: address_offset: 0x0 number_of_fields: 1 - - slave_name: REG_FPGA_VOLTAGE_SENS # pi_unb_fpga_voltagesens.py - slave_type: REG - slave_description: "Not used, FPGA voltages are monitored via DC-DC converter power supply volages" + - mm_port_name: REG_FPGA_VOLTAGE_SENS # pi_unb_fpga_voltagesens.py + mm_port_type: REG + mm_port_description: "Not used, FPGA voltages are monitored via DC-DC converter power supply volages" fields: - - field_name: voltages field_description: "Not used" diff --git a/libraries/dsp/bf/bf.peripheral.yaml b/libraries/dsp/bf/bf.peripheral.yaml index 85987668999582e19448a14b902807b067f9e30e..12c36e3e1a9c95371dbcca9f63b5a2f2d83604fb 100644 --- a/libraries/dsp/bf/bf.peripheral.yaml +++ b/libraries/dsp/bf/bf.peripheral.yaml @@ -16,11 +16,11 @@ peripherals: - { name: g_bf.nof_input_streams , value: 16 } - { name: c_nof_signal_paths_per_stream, value: g_bf.nof_signal_paths / g_bf.nof_input_streams } - slave_ports: + mm_ports: # ram_bf_weights - - slave_name : WEIGHTS - number_of_slaves: g_bf.nof_weights - slave_type: RAM + - mm_port_name : WEIGHTS + number_of_mm_ports: g_bf.nof_weights + mm_port_type: RAM fields: - - field_name : bf_weights width : g_bf.in_weights_w * c_nof_complex @@ -29,26 +29,26 @@ peripherals: field_description: | "Contains the weights. The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part." - slave_discription: > + mm_port_description: > " " # ram_ss_ss_wide - - slave_name : SS_SS_WIDE - number_of_slaves: g_bf.nof_weights - slave_type: RAM + - mm_port_name : SS_SS_WIDE + number_of_mm_ports: g_bf.nof_weights + mm_port_type: RAM fields: - - field_name : ss_ss_wide width : 32 number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream # 16*4=64, nof_input_streams*nof_signal_paths_per_stream field_description: | "Contains the addresses to select from the stored subbands." - slave_discription: > + mm_port_description: > " " # ram_st_sst_bf - - slave_name : ST_SST - number_of_slaves: g_bf.nof_weights - slave_type: RAM + - mm_port_name : ST_SST + number_of_mm_ports: g_bf.nof_weights + mm_port_type: RAM fields: - - field_name : st_sst_bf width : 56 @@ -57,13 +57,13 @@ peripherals: field_description: | "Contains the weights. The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part." - slave_discription: > + mm_port_description: > " " # reg_st_sst_bf - - slave_name : treshold - number_of_slaves: 1 - slave_type: REG + - mm_port_name : treshold + number_of_mm_ports: 1 + mm_port_type: REG fields: - - field_name : treshold address_offset: 0x0 @@ -72,7 +72,7 @@ peripherals: In case the treshold register is set to a non-zero value, it allows to create a sample & hold function for the a-input of the multiplier. The a-input of the multiplier is updated every treshold clockcycle. Thereby cross statistics can be created." - slave_discription: > + mm_port_description: > " " peripheral_description: | diff --git a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml index 04e707fbea28f020d5a47173567f77811cad3291..2872466d08baf491453e722ba3bd0403fb03ed53 100644 --- a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml +++ b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml @@ -13,28 +13,28 @@ peripherals: - { name: g_fs_offset_w , value: 10 } - { name: g_fs_step_w , value: 17 } - slave_ports: + mm_ports: # actual hdl name: ram_fringe_stop_step - - slave_name : STEP - slave_type : RAM + - mm_port_name : STEP + mm_port_type : RAM fields: - - field_name : fringe_stop_step width: g_fs_step_w number_of_fields: g_nof_channels field_description: | "Contains the step size for all nof_channels channels." - slave_discription: " " + mm_port_description: " " # actual hdl name: fringe_stop_offset - - slave_name : STOP_OFFSET - slave_type : RAM + - mm_port_name : STOP_OFFSET + mm_port_type : RAM fields: - - field_name: fringe_stop_offset width: g_fs_offset_w number_of_fields: g_nof_channels field_description: | "Contains the offset for all nof_channels channels." - slave_discription: " " + mm_port_description: " " peripheral_description: | "The fringe stopping peripheral is based on piecewise linear coefficients. The coefficients are indicated as offset and step. diff --git a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml index c4632c5a4dabd728e680b782578f57d77e06c7f4..4c748e535c27266b3077edf9f05275364aedd2d1 100644 --- a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml +++ b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml @@ -8,11 +8,11 @@ hdl_library_description: "JESD204b peripherals for ADC interface." peripherals: - peripheral_name: jesd_ctrl # pi_jesd_ctrl.py peripheral_description: "Reset JESD, and enable/disable individual JESD inputs" - slave_ports: + mm_ports: # MM port for node_adc_input_and_timing.vhd - - slave_name: PIO_JESD_CTRL - slave_type: REG - slave_description: "" + - mm_port_name: PIO_JESD_CTRL + mm_port_type: REG + mm_port_description: "" fields: - - field_name: reset field_description: "Write 1 to reset the full JESD interface for all JESD signal inputs." @@ -30,11 +30,11 @@ peripherals: - peripheral_name: jesd204b_arria10 # pi_jesd204b_unb2.py peripheral_description: | "M&C of Intel Arria10 JESD204B ADC interface IP, see https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf" - slave_ports: + mm_ports: # MM port for tech_jesd204b.vhd - - slave_name: REG_JESD204B - slave_type: REG - slave_description: "" + - mm_port_name: REG_JESD204B + mm_port_type: REG + mm_port_description: "" fields: - - {field_name: rx_dll_ctrl, width: 17, bit_offset: 0, access_mode: RW, address_offset: 0x50} - - {field_name: rx_syncn_sysref_ctrl, width: 25, bit_offset: 0, access_mode: RW, address_offset: 0x54}