diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 9260356e07c5ae4dc0ae0cb67188bfc601653dc5..59c761de88644857e1b6434664cd499730650e62 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -1045,13 +1045,14 @@ BEGIN
---------------
u_nw_10GbE_beamlet_output: ENTITY nw_10GbE_lib.nw_10GbE
GENERIC MAP (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_10GbE_beamlet_output,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill_beamlet_output,
- g_tx_fifo_size => c_fifo_tx_size_beamlet_output,
- g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_beamlet_output,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill_beamlet_output,
+ g_tx_fifo_size => c_fifo_tx_size_beamlet_output,
+ g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_xon_backpressure => TRUE
)
PORT MAP (
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
index ead48b48a7d79a60e916b27ef1e746237bca17de..37e704250c6f5a32d96f54bcc80a5fa734afee49 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
@@ -167,21 +167,21 @@ BEGIN
CASE TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
-- Read Block Sync
WHEN 0 =>
- sla_out.rddata(0) <= mm_on_status;
- sla_out.rddata(1) <= mm_on_pps;
+ sla_out.rddata(0) <= mm_on_status;
+ sla_out.rddata(1) <= mm_on_pps;
WHEN 1 =>
- sla_out.rddata(31 DOWNTO 0) <= mm_nof_clk_per_sync;
+ sla_out.rddata(c_word_w - 1 DOWNTO 0) <= mm_nof_clk_per_sync;
-- Read current BSN
WHEN 2 =>
- sla_out.rddata(31 DOWNTO 0) <= mm_current_bsn(31 DOWNTO 0);
- mm_current_bsn_hi <= mm_current_bsn(63 DOWNTO 32); -- first read low part and preserve high part
+ sla_out.rddata(c_word_w - 1 DOWNTO 0) <= mm_current_bsn(31 DOWNTO 0);
+ mm_current_bsn_hi <= mm_current_bsn(63 DOWNTO 32); -- first read low part and preserve high part
WHEN 3 =>
- sla_out.rddata(31 DOWNTO 0) <= mm_current_bsn_hi; -- then read preserved high part
+ sla_out.rddata(c_word_w - 1 DOWNTO 0) <= mm_current_bsn_hi; -- then read preserved high part
-- Read current bsn_time_offset
WHEN 4 =>
- sla_out.rddata <= RESIZE_UVEC(mm_bsn_time_offset, c_word_w);
+ sla_out.rddata(c_word_w - 1 DOWNTO 0) <= RESIZE_UVEC(mm_bsn_time_offset, c_word_w);
WHEN OTHERS => NULL; -- not used MM addresses
END CASE;
diff --git a/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd b/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
index 2df5755b77df0eb5972e90bcb37344756cd6b1a9..b35b0ad82280486c67c72a9cd83aed33be87f67b 100644
--- a/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
+++ b/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
@@ -52,6 +52,7 @@ ENTITY nw_10GbE IS
g_tx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
g_rx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
g_word_alignment_padding : BOOLEAN := FALSE;
+ g_xon_backpressure : BOOLEAN := FALSE;
g_arp_period_s : NATURAL := 30;
g_ip_hdr_field_arr : t_common_field_arr
);
@@ -232,7 +233,8 @@ BEGIN
g_tx_fifo_fill => g_tx_fifo_fill,
g_tx_fifo_size => g_tx_fifo_size,
g_rx_fifo_size => g_rx_fifo_size,
- g_word_alignment_padding => g_word_alignment_padding
+ g_word_alignment_padding => g_word_alignment_padding,
+ g_xon_backpressure => g_xon_backpressure
)
PORT MAP (
-- Transceiver PLL reference clock
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
index df979c50d6399d4f9b3b0b1ea33b536025b8cf28..280f008eb693f5c4f4962d86fae11725d9b8644b 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
@@ -45,7 +45,19 @@
--
-- to avoid that the packet transmission will get a gap that will abort it.
-- The average DP data rate depends on dp_clk and on the DP data valid.
---
+--
+-- g_xon_backpressure can be enabled to set xon = 0 when the TX fill fifo is
+-- full. This also makes use of an extra fifo of size g_tx_fifo_size to
+-- buffer the last incoming frame when xon = 0 to prevent corrupting the frame.
+--
+-- Remark
+-- . Note that the snk_out_arr().xon is used to indicate when the MAC cannot
+-- receive new frames. If xon = 0 is ignored, the TX FIFO can overflow.
+-- . xon can become low when the MAC has no link. When g_xon_backpressure
+-- = TRUE, xon = 0 can also occur when the ready of the MAC is 0 for a long
+-- time filling up the TX fifo. If this fifo is almost full xon is set to 0,
+-- the remainder of the incoming frame is captured by an extra fifo. Therefore
+-- using g_xon_backpressure = TRUE uses extra RAM.
LIBRARY IEEE, common_lib, dp_lib, diag_lib, technology_lib, tech_mac_10g_lib, tech_eth_10g_lib, tr_xaui_lib;
USE IEEE.std_logic_1164.ALL;
@@ -72,7 +84,8 @@ ENTITY tr_10GbE IS
g_tx_fifo_fill : NATURAL := 10; -- Release tx packet only when sufficiently data is available,
g_tx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
g_rx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
- g_word_alignment_padding : BOOLEAN := FALSE
+ g_word_alignment_padding : BOOLEAN := FALSE;
+ g_xon_backpressure : BOOLEAN := FALSE
);
PORT (
-- Transceiver PLL reference clock
@@ -146,11 +159,12 @@ ARCHITECTURE str OF tr_10GbE IS
SIGNAL eth_rx_clk_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL eth_rx_rst_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
- SIGNAL dp_fifo_dc_tx_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
- SIGNAL dp_fifo_dc_tx_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_fifo_sc_tx_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_fifo_sc_tx_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL dp_fifo_fill_tx_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL dp_fifo_fill_tx_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_tx_snk_out_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL mac_10g_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL mac_10g_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
@@ -227,7 +241,48 @@ BEGIN
eth_rx_clk_arr => eth_rx_clk_arr,
eth_rx_rst_arr => eth_rx_rst_arr
);
-
+
+ ---------------------------------------------------------------------------------------
+ -- TX FIFO for buffering last packet when xon = 0 to prevent corrupt frames.
+ ---------------------------------------------------------------------------------------
+ gen_xon_backpressure : IF g_xon_backpressure GENERATE
+ gen_dp_fifo_sc_tx : FOR i IN 0 TO g_nof_macs-1 GENERATE
+ u_dp_fifo_sc_tx : ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_data_w => c_xgmii_data_w,
+ g_empty_w => c_tech_mac_10g_empty_w,
+ g_use_empty => TRUE,
+ g_fifo_size => g_tx_fifo_size
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+
+ src_in => dp_fifo_sc_tx_src_in_arr(i),
+ src_out => dp_fifo_sc_tx_src_out_arr(i)
+ );
+ END GENERATE;
+
+ -- When MAC receives pause frames, it's ready signal is low for a long time
+ -- Set xon to (xon AND ready) to enable flushing frames using external dp_xonoff.
+ p_fifo_sc_tx : PROCESS(dp_fifo_fill_tx_snk_out_arr)
+ BEGIN
+ dp_fifo_sc_tx_src_in_arr <= dp_fifo_fill_tx_snk_out_arr;
+ FOR i IN 0 TO g_nof_macs-1 LOOP
+ dp_fifo_sc_tx_src_in_arr(i).xon <= dp_fifo_fill_tx_snk_out_arr(i).xon AND dp_fifo_fill_tx_snk_out_arr(i).ready;
+ END LOOP;
+ END PROCESS;
+ END GENERATE;
+
+ gen_no_xon_backpressure : IF NOT g_xon_backpressure GENERATE
+ dp_fifo_sc_tx_src_out_arr <= snk_in_arr;
+ snk_out_arr <= dp_fifo_fill_tx_snk_out_arr;
+ END GENERATE;
+
---------------------------------------------------------------------------------------
-- TX: FIFO: dp_clk -> tx_clk and with fill level/eop trigger so we can deliver packets to the MAC fast enough
---------------------------------------------------------------------------------------
@@ -248,19 +303,17 @@ BEGIN
rd_rst => eth_tx_rst_arr(i),
rd_clk => eth_tx_clk_arr(i),
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
+ snk_out => dp_fifo_fill_tx_snk_out_arr(i),
+ snk_in => dp_fifo_sc_tx_src_out_arr(i),
src_in => dp_fifo_fill_tx_src_in_arr(i),
src_out => dp_fifo_fill_tx_src_out_arr(i)
);
END GENERATE;
-
---------------------------------------------------------------------------------------
-- ETH MAC + PHY
---------------------------------------------------------------------------------------
-
u_tech_eth_10g : ENTITY tech_eth_10g_lib.tech_eth_10g
GENERIC MAP (
g_technology => g_technology,